IC Passive Components (1/13/00)
Page 1 -1
INTEGRATED CIRCUIT PASSIVE COMPONENTS
INTRODUCTION
Objective
The objective of this presentation is:
1.) Show the passive components that are compatible with BJT and CMOS technologies
2.) Modifications to the standard BJT and CMOS processes
3.) Physical influence on passive components
Outline
• Capacitors
• Resistors
• Inductors
• Modifications to the standard BJT and CMOS processes
• Diodes
• Summary
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -2
INTEGRATED CIRCUIT CAPACITORS
PN Junction
Concept:
Metallurgical Junction
n-type semiconductor
p-type semiconductor
iD
+vD Depletion
region
n-type
semiconductor
p-type
semiconductor
iD
+vD xd
xp
0
xn
x
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field which opposes the diffusion
mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -3
PN Junction Characterization
Cross section of an ideal pn junction:
Impurity concentration (cm-3)
xd
xp
x
0
n-type
semiconductor
p-type
semiconductor
iD
ND
xn
-NA
Depletion charge concentration (cm-3)
+vD -
qND
xp
0
xn
x
-qNA
Electric Field (V/cm)
x
E0
Potential (V)
φ0− vD
x
xd
ECE 6421 - Analog IC Design
Fig. 2.3-2A
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -4
Summary of PN Junction Analysis
Barrier potentialkT NAND
 NAND
φo = φB =
ln


=
V
ln
t  n2 
q  ni2 
 i 
Depletion region widthsxn =
2εsi(φo-vD)NA
qND(NA+ND)
xp =
2εsi(φo-vD)ND
qND(NA+ND)



x ∝
1
N
Depletion capacitanceCj = A
εsiqNAND
2(NA+ND)
Cj
1
φo-vD
Breakdown voltageεsi(NA+ND)
1
2
∝
BV =
E
max
N
2qNAND
ECE 6421 - Analog IC Design
=
Cj0
Cj0
vD
1- φ
o
Fig. 2.3-3B
0
φ0 vD
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -5
Summary of PN Junction Analysis - Continued
Graded junction:
Impurity Concentration (cm-3)
ND
x
0
NA
Above expressions become:
Depletion region widths 2εsi(φo-vD)NA m
x n =  qN (N +N ) 

D A D 
 2εsi(φo-vD)ND m
x p =  qN (N +N ) 

D A D 



PC00
3
 1 m
x ∝ 
 N
2.5
2
Cj
Depletion capacitance1.5
Cj0
Cj0
1
 εsiqNAND  m
1
=
Cj = A2(N +N )
v D m

A D  ( φo-vD) m

1 0.5
φ o 

where 0.33 ≤m ≤ 0.5. (Note that m = MJ)
ECE 6421 - Analog IC Design
m=0.333
m=0.5
0
-10
-8
-6
-4
vD
φ0
-2
0
2
PC01A
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -6
Summary of PN Junction Analysis - Continued
Current-Voltage Relationship2
 -VGO


 vD
 Dppno D n n p o qAD ni
3
iD = Isexp  - 1
where
I
=
qA

+

≈
=
KT
exp


s
Ln 
L N


 Vt 
 Lp
 Vt 
25
20
iD 15
Is 10
5
0
-5
-4
-3
-2
-1
0
vD/Vt
1
2
3
4
10 x1016
8 x1016
16
iD 6 x10
Is
4 x1016
2 x1016
0
-40
ECE 6421 - Analog IC Design
-30
-20
-10
0
vD/Vt
10
20
30
40
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -7
Cross-Section of an NPN BJT
All passive components must be compatible with this structure.
Collector
Substrate
p
Base
Emitter
p
n+
n+
n-epitaxial layer
n+ buried layer
p- substrate
Heavily
Doped p
ECE 6421 - Analog IC Design
Lightly
Doped p
Intrinsic
Doping
Lightly
Doped n
Heavily Metal
Doped n
BJTNPN
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -8
Collector-Base Capacitance (C µ )
Illustration:
Substrate
p
Collector
Base
p
n+
n-epitaxial layer
n+ buried layer
p- substrate
Model:
C
Sidewall contribution:
CCB = Cµ
π
Asidewall = P·d 2
B
CCS
where
Substrate
PC02
P = perimeter of the capacitor
d = depth of the diffusion
Values:
Includes the bottom plus sidewall capacitance.
Cµ ≈ 1fF/µm2 (dependent on the reverse bias voltage)
Can also have base-emitter capacitance and collector-substrate capacitance
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -9
MOS Capacitors
Polysilicon-Oxide-Channel for Enhancement MOSFETs
Bulk connected to V SS
G
VSS
VDG =VGS >V T
D,S
Gate
VGS>VT
VSS
Source
Bulk
p+
p-
Poly
n+
CGS
Channel
Drain
n+
Substrate/Bulk
Comments:
• Capacitance = CGS ≈ CoxW·L
• Channel must be formed, therefore VGS > VT
• With VGS > VT and VDS = 0, the transistor is in the active region.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -10
MOS Capacitors - Continued
Bulk tuning of the polysilicon-oxide-channel capacitor (0.35µm CMOS)
0.8
-0.65V
CG
vB
Fig. 2.5-3
VT
0.6
0.4
Volts or pF
1.0
CG
0.2
0.0
-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5
vB (Volts)
Cmax/Cmin ≈ 4
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -11
MOS Capacitors - Continued
Bulk connected to Source-Drain
G
VDG =VGS >V T
D,S
Gate
VGS>VT
Source
Bulk
p+
p-
Poly
n+
Drain
CGS
Channel
CGB
n+
Substrate/Bulk
CG-D,S
CG-D,S = CGS(oxide) + CGB(depletion)
Comments:
• Capacitance is more constant as a function of VG-D,S
CGS
CBG
VT
VG-D,S
• Still not a good capacitor for large voltage swings
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -12
MOS Capacitors - Continued
Accumulation-Mode Capacitor12
=
CG-D,S
Source
Oxide
n+
Drain
Substrate
Polysilicon
n+
Source
n+
p+
Channel
n-well
Fig. 2.5-4
Comments:
• ±30% tuning range (Tuned by the voltage across the capacitor terminals)
• Q ≈ 25 for 3.1pF at 1.8 GHz (optimization leads to Qs of 200 or greater)
1
T. Soorapanth, et. al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs,” Proc. 1998 Symposium on VLSI Circuits, Digest of
Papers, pp. 32-33, 1998.
2
R. Castello, et. al., “A ±30% Tuning Range Varactor Compatible with future Scaled Technologies,” Proc. 1998 Symposium on VLSI Circuits,
Digest of Papers, pp. 34-35, 1998.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -13
MOS Capacitors - Continued
Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs
A
IOX
IOX
poly
FOX
B
B
A
IOX
FOX
n-active
poly
n-well
p-substrate
n-active
n-well
p-substrate
Unit capacitance ≈ 1.2 fF/µm2
Voltage dependence:
C(V) ≈ C(0) + a1V + a2V2, where a1 ≈ 0 and a2 ≈ 210 ppm/V2
(Not as good linearity as poly-poly capacitors)
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -14
MOS Capacitors - Continued
Polysilicon-Oxide-Polysilicon (Poly-Poly)
A
B
IOX
IOX
Polysilicon II
IOX
Polysilicon I
FOX
FOX
substrate
Best possible capacitor for analog circuits
Less parasitics
Voltage independent
Approach for increasing the voltage linearity:
ECE 6421 - Analog IC Design
Top Plate
Top Plate
Bottom Plate
Bottom Plate
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -15
Implementation of Capacitors using Available Metal and Poly Interconnect Layers
M3
M2
B
M1
T
Poly
T
M3
T
M2
M1
B
M2
B
T
ECE 6421 - Analog IC Design
B
M1
Poly
T
M2
M1
B
Fig. 2.5-8
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -16
Fractal Capacitors
Capacitance between conductors on the same level and use lateral flux..
Fringing Capacitance
Top View of a Lateral Flux Capacitor
PC10
These capacitors are called fractal capacitors because the fractal patterns are structures that enclose a finite
area with an infinite perimeter.
In certain cases, the capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -17
Capacitor Errors
1.) Oxide gradients
2.) Edge effects
3.) Parasitics
4.) Voltage dependence
5.) Temperature dependence
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -18
Capacitor Errors - Oxide Gradients
Error due to a variation in oxide thickness across the wafer.
A1
A2
B
A1
B
A2
x1
x2
x1
No common centroid
layout
Common centroid
layout
y
Only good for one-dimensional errors.
An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical
error balanced over the entire area of interest.
A
B
C
A
B
C
A
B
C
C
A
B
C
A
B
C
A
B
B
C
A
B
C
A
B
C
A
0.2% matching of poly resistors was achieved using an array of 50 unit resistors.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -19
Capacitor Errors - Edge Effects
There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.
C
A
B
Improved matching achieve by matching the surroundings of A and B.
C
A
ECE 6421 - Analog IC Design
B
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -20
Capacitor Errors - Area/Periphery Ratio
The best match between two structures occurs when their area-to-periphery ratios are identical.
Let C’1 = C1 ± ∆C1 and C’2 = C2 ± ∆C2
where
C’ = the actual capacitance
C = the desired capacitance (which is proportional to area)
∆C = edge uncertainty (which is proportional to the periphery)
Solve for the ratio of C’2/C’1,
∆C2


1
±
C2 
C’2 C 2ʱ ∆ C 2 C2 
C’1 = C 1ʱ ∆ C 1 = C1 
∆ C 1
1
±
 C 
1
∆ C 2 
∆ C 1  C2 
∆ C 2 ∆ C 1
C2 
≈ C 1 ± C  1 +- C  ≈ C 1 ± C +- C 
1
2  
1 
1
2
1 
∆C2 ∆C1
C’ 2 C 2
If C = C , then C’ = C
2
1
1
1
Therefore, the best matching results are obtained when the area/periphery ratio of C2 is equal to the
area/periphery ratio of C1.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -21
Capacitor Errors - Relative Accuracy
Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the
difference in values between the two capacitors.
For example,
0.04
Relative Accuracy
Unit Capacitance = 0.5pF
0.03
Unit Capacitance = 1pF
0.02
0.01
Unit Capacitance = 4pF
0.00
ECE 6421 - Analog IC Design
1
2
4
8
16
Ratio of Capacitors
32
64
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -22
Capacitor Errors - Parasitics
Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate.
Top Plate
Top
plate
parasitic
Desired
Capacitor
Bottom Plate
Bottom
plate
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired
Bottom plate parasitic is 0.05 to 0.2 Cdesired
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -23
Other Considerations on Capacitor Accuracy
Decreasing Sensitivity to Edge Variation:
A
A'
B
B'
Sensitive to edge variation in
both upper andlower plates
A
A'
B'
B
Sensitive to edge varation in
upper plate only.
Fig. 2.6-13
A structure that minimizes the ratio of perimeter to area (circle is best).
Top Plate
of Capacitor
Bottom plate
of capacitor
Fig. 2.6-14
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -24
Capacitor Errors - Temperature and Voltage Dependence
Polysilicon-Oxide-Semiconductor Capacitors
Absolute accuracy ≈ ±10%
Relative accuracy ≈ ±0.2%
Temperature coefficient ≈ +25 ppm/C°
Voltage coefficient ≈ -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors
Absolute accuracy ≈ ±10%
Relative accuracy ≈ ±0.2%
Temperature coefficient ≈ +25 ppm/C°
Voltage coefficient ≈ -20ppm/V
Accuracies depend upon the size of the capacitors.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -25
Capacitor Layout
Double-polysilicon capacitor
Metal
Triple-level metal capacitor.
Polysilicon 2
Metal 3
FOX
Substrate
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
FOX
Substrate
Polysilicon gate
Polysilicon 2
Cut
ECE 6421 - Analog IC Design
Metal 2 Metal 1
Polysilicon gate
Metal 3
Metal 2 Metal 1 Metal 3
Via 2
Via 2
Cut
Metal 2
Via 1
Metal 1
Metal 1
Fig. 2.6-17
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -26
INTEGRATED CIRCUIT RESISTORS
Resistor Layout
Direction of current flow
W
T
Area, A
L
Fig. 2.6-15
Resistance of a conductive sheet is expressed in terms of
ρL ρL
R = A = W T (Ω)
where
ρ = resistivity in Ω-m
Ohms/square:
L
ρ  L
R= 
=
ρ
S W (Ω)
T  W
where
ρS is a sheet resistivity and has the units of ohms/square
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -27
Base and Emitter Diffused Resistors
Cross-section of a Base Resistor:
Collector
Substrate
A
B
A
p
B
p
n+
Cj
2
n-epitaxial layer
p- substrate
Comments:
RAB
Sheet resistance ≈ 100 Ω/
n+ buried layer
Cj
2
Collector
PC03
to 200 Ω/
TCR = +1500ppm/¡C
Note:
1% 104
=
¡C ¡C
Emitter Resistor:
Sheet resistance ≈ 52 Ω/
area)
to 10 Ω/
(Generally too small to make sufficient resistance in reasonable
TCR = +600ppm/¡C
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -28
Base Pinched Resistor
Good for large value of sheet resistance.
Cross-section:
Substrate
A
B
p
p
n+
n+
n-epitaxial layer
p- substrate
PC06
IV Curves and Model:
iAB
Pinched operation
A
vAB
RAB
Collector
B
PC05
Comments:
Sheet resistance is 5 to 15kΩ/
Voltage across the resistor is limited to 6V or less because of breakdown
TCR ≈ 2500ppm/¡C
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -29
Epitaxial Pinched Resistors
Cross section:
Substrate
A
B
p
p
n+
n-epitaxial layer
p- substrate
PC06
Sheet resistance ≈ 1-10kΩ/
Top View:
A
B
PC07
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -30
MOS Resistors - Source/Drain Resistor
Metal
SiO2
p+
FOX
FOX
n- well
p- substrate
Fig. 2.5-16
Diffusion:
10-100 ohms/square
Absolute accuracy = ±35%
Relative accuracy = 2% (5 µm), 0.2% (50 µm)
Temperature coefficient = +1500 ppm/°C
Voltage coefficient ≈ -200 ppm/V
Ion Implanted:
500-2000 ohms/square
Absolute accuracy = ±15%
Relative accuracy = 2% (5 µm), 0.15% (50 µm)
Temperature coefficient = +400 ppm/°C
Voltage coefficient ≈ -800 ppm/V
Comments:
• Parasitic capacitance to well is voltage dependent.
• Piezoresistance effects occur due to chip strain from mounting.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -31
Polysilicon Resistor
Metal
,,,,,
Polysilicon resistor
,,
FOX
p- substrate
Fig. 2.5-17
30-100 ohms/square (unshielded)
100-500 ohms/square (shielded)
Absolute accuracy = ±30%
Relative accuracy = 2% (5 µm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient ≈ -100 ppm/V
Comments:
• Used for fuzes and laser trimming
• Good general resistor with low parasitics
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -32
N-well Resistor
Metal
n+
FOX
FOX
FOX
n- well
p- substrate
Fig. 2.5-18
1000-5000 ohms/square
Absolute accuracy = ±40%
Relative accuracy ≈ 5%
Temperature coefficient = 4000 ppm/°C
Voltage coefficient is large ≈ +8000 ppm/V
Comments:
• Good when large values of resistance are needed.
• Parasitics are large and resistance is voltage dependent
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -33
Example of Resistor Layouts
Metal
Metal
FOX
FOX
FOX
Substrate
Active area (diffusion)
FOX
Substrate
Active area (diffusion) Well diffusion
Active area
Contact
FOX
Active area or Polysilicon W
Well diffusion
W
Contact
Cut
Cut
L
Metal 1
Diffusion or polysilicon resistor
Metal 1
L
Well resistor
Fig. 2.6-16
Corner corrections:
0.5
1.45
1.25
Fig. 2.6-16B
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -34
Example 2.6-1 Resistance Calculation
Given a polysilicon resistor like that drawn above with W=0.8µm and L=20µm, calculate ρs (in Ω/❑), the
number of squares of resistance, and the resistance value. Assume that ρ for polysilicon is 9 × 10-4 Ωcm and polysilicon is 3000 Å thick. Ignore any contact resistance.
Solution
First calculate ρs.
9 × 10 -4 Ω - c m
ρ
ρs = T =
= 30 Ω/❑
3000 × 10 -8 c m
The number of squares of resistance, N, is
20µm
L
N = W = 0.8µm = 25
giving the total resistance as
R = ρs × Ν = 30 × 25 = 750 Ω
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -35
Integrated Circuit Passive Component Performance Summary
Component Type
Range of Values
Temperature
Coefficient
Voltage
Coefficient
Poly-oxide-semiconductor Capacitor
0.35-1.0 fF/µm2
10%
0.1%
20ppm/°C
±20ppm/V
Poly-Poly Capacitor
0.3-1.0 fF/µm2
20%
0.1%
25ppm/°C
±50ppm/V
100-200Ω/sq.
±20%
0.2%
+1750ppm/°C
-
2-10Ω/sq.
±20%
±2%
+600ppm/°C
-
Base Pinched
2k-10kΩ/sq.
±50%
±10%
+2500ppm/°C
Poor
Epitaxial Pinched
2k-5kΩ/sq.
±50%
±7%
+3000ppm/°C
Poor
Source/Drain Diffused
10-100 Ω/sq.
35%
2%
1500ppm/°C
-200ppm/V
Ion Implanted Resistor
0.5-2 kΩ/sq.
15%
2%
400ppm/°C
-800ppm/V
Poly Resistor
30-200 Ω/sq.
30%
2%
1500ppm/°C
-100ppm/V
n-well Resistor
1-10 kΩ/sq.
40%
5%
8000ppm/°C
-10kppm/V
Thin Film
0.1k-2kΩ/sq.
±10 to ±200ppm/°C
-
Base Diffused
Emitter Diffused
ECE 6421 - Analog IC Design
Absolute Relative
Accuracy Accuracy
±5-±20% ±0.2-±2%
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -36
INDUCTORS
Inductors
What is the range of values for on-chip inductors?
,,,,,,
,,,,,,
12
Inductor area is too large
Inductance (nH)
10
8
6
ωL = 50Ω
4
Interconnect parasitics
are too large
2
0 0
10
20
30
40
Frequency (GHz)
50
Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz.
1
1
= 5nH
L= 2 2 =
4π fo C (2π·109)2·5x10-12
Note: Off-chip connections will result in inductance as well.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -37
Candidates for inductors in CMOS technology are:
1.) Bond wires
2.) Spiral inductors
3.) Multi-level spiral
4.) Solenoid
Bond wire Inductors:
β
β
d
•
•
•
•
Fig.6-6
Function of the pad distance d and the bond angle β
Typical value is 1nH/mm which gives 2nH to 5nH in typical packages
Series loss is 0.2 /mm for 1 mil diameter aluminum wire
Q 60 at 2 GHz
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -38
Planar Spiral Inductors
Spiral Inductors on a Lossy Substrate:
L
R
C1
C2
R1
R2
Fig. 16-7
• Design Parameters:
Inductance,
L = Σ(Lself + Lmutual)
Quality factor, Q =
ωL
R
1
Self-resonant frequency: fself =
LC
• Trade-off exists between the Q and self-resonant frequency
• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -39
Planar Spiral Inductors - Continued
Inductor Design
I
,,,,,
W
SiO2
I
ID
I
S
I
Nturns = 2.5
Silicon
Fig. 6-9
Typically: 3<Nturns <5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow through the
center.
Loss Mechanisms:
• Skin effect
• Capacitive substrate losses
• Eddy currents in the silicon
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -40
Planar Spiral Inductors - Continued
Influence of a Lossy Substrate
L
R
C1
C2
R1
R2
CLoad
Fig. 12.2-13
where:
L is the desired inductance
R is the series resistance
C1 and C2 are the capacitance from the inductor to the ground plane
R1 and R2 are the eddy current losses in the silicon
Guidelines for using spiral inductors on chip:
• Lossy substrate degrades Q at frequencies close to fself
• To achieve an inductor, one must select frequencies less than fself
• The Q of the capacitors associated with the inductor should be very high
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -41
Planar Spiral Inductors - Continued
Comments concerning implementation:
1.) Put a metal ground shield between the inductor and the silicon to reduce the capacitance.
• Should be patterned so flux goes through but electric field is grounded
• Metal strips should be orthogonal to the spiral to avoid induced loop current
• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to keep the series resistance low.
3.) Use the metal with the lowest resistance and furtherest away from the substrate.
4.) Parallel metal strips if other metal levels are available to reduce the resistance.
Example:
Fig. 6-10
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -42
Multi-Level Spiral Inductors
Use of more than one level of metal to make the inductor.
• Can get more inductance per area
• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.
• Multi-level spiral inductors suffer from contact resistance (must have many parallel contacts
to reduce the contact resistance)
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -43
Solenoid Inductors
Example:
Upper Metal
nt
,,
,,,,,,,,,,
e
Curr
l
i
o
C
Coil
Cur
Contact
Vias
rent
Magnetic Flux
Lower Metal
SiO2
Silicon
Fig. 6-11
Comments:
• Magnetic flux is small due to planar structure
• Capacitive coupling to substrate is still present
• Potentially best with a ferromagnetic core
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -44
OTHER CONSIDERATIONS OF CMOS TECHNOLOGY
Lateral Bipolar Junction Transistor
P-Well Process
NPN LateralVDD
n+
Base
Emitter
Collector
p+
n+
n+
p-well
n-substrate
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -45
Lateral Bipolar Junction Transistor - Continued
Field-aided LateralßF ≈ 50 to 100 depending on the process
Keep channel
from forming
VDD
n+
Base
Emitter VGate Collector
n+
p+
n+
p-well
n-substrate
• Good geometry matching
• Low 1/f noise (if channel doesn’t form)
• Acts like a phototransistor with good responsitivity
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -46
Geometry of the Lateral PNP BJT
Minimum Size layout of a single
emitter dot lateral PNP BJT:
n-well
p-diffusion
contact
40 emitter dot LPNP transistor (total device area
is 0.006mm2 in a 1.2µm CMOS process):
p-substrate
diffusion
Base
n-well
contact
Lateral
Collector
Emitter
31.2
µm
71.4
µm
Base
Gate
V SS
Lateral
Collector
V SS
Emitter
84.0 µm
Gate
(poly)
33.0 µm
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -47
Performance of the Lateral PNP BJT
Schematic:
Emitter
Gate
Base
Lateral
Collector
Vertical
Collector
( V SS )
ßL vs ICL for the 40 emitter dot LPNP
BJT:
Lateral efficiency versus IE for the 40
emitter dot LPNP BJT:
VCE =
− 4.0 V
150
1.0
110
VCE =
− 0. 4V
90
70
50
1 nA
VCE =
− 4.0 V
0.8
Lateral Efficiency
Lateral ß
130
VCE =
− 0. 4V
0.6
0.4
0.2
10 nA
100 nA
1 µA
10 µA
Lateral Collector Current
ECE 6421 - Analog IC Design
100 µA
1 mA
0
1 nA
10 nA
100 nA
1 µA
10 µA
Emitter Current
100 µA
1 mA
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -48
Performance of the Lateral PNP BJT - Continued
Typical Performance for the 40 emitter dot LPNP BJT:
Transistor area
0.006 mm2
Lateral ß
90
Lateral efficiency
0.70
Base resistance
150
En @ 5 Hz
2.46 nV / Hz
En (midband)
1.92 nV / Hz
fc (En)
3.2 Hz
In @ 5 Hz
3.53 pA / Hz
In (midband)
0.61 pA / Hz
fc (In)
162 Hz
fT
85 MHz
Early voltage
16 V
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -49
High Voltage MOS Transistor
The well can be substituted for the drain giving a lower conductivity drain and therefore higher
breakdown voltage.
NMOS in n-well example:
Source
Oxide
Gate
Drain
Substrate
n+
p+
Polysilicon
n+
Source
Channel
n-well
p-substrate
Fig. 2.6-7A
Drain-substrate/channel can be as large as 20V or more.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -50
Latch-up in CMOS Technology
Latch-up Mechanisms
1. SCR regenerative switching action.
2. Secondary breakdown.
3. Sustaining voltage breakdown.
Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
,,
,,
,,
,,
,,
,,
,,,,,,,,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
|,, ,,
{
|,,,,
{
VDD
D
G
S
S
D
G
A
n+
p+
p-well
p+
RN-
n+
VSS
B
p+
n+
RP-
n- substrate
Fig. 2.6-8
Equivalent circuit of the SCR formed from the parasitic BJTs:
VDD
VDD
+
RNA
Vin ≈VSS
B
A
-
Vout
B
RP-
VSS
VSS
ECE 6421 - Analog IC Design
Fig. 2.6-9
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -51
Preventing Latch-Up in a P-Well Technology
1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This
will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can occur.
3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
p-channel transistor
n+ guard bars
VDD
FOX
n-channel transistor
p+ guard bars
VSS
FOX
FOX
FOX
FOX
p-well
FOX
FOX
n- substrate
Figure 2.6-10
For more information see R. Troutman, “CMOS Latchup”, Kluwer Academic Publishers.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -52
Electrostatic Discharge Protection (ESD)
Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit
VDD
p+ to n-well
diode
To internal gates
n+ to p-substrate
diode
p+ resistor
Bonding
Pad
VSS
Implementation in CMOS technology
Metal
FOX
n+
FOX
p+
FOX
n-well
p-substrate
Fig. 2.6-11
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -53
Temperature Characteristics of Transistors
Fractional Temperature Coefficient
1 ∂x
Typically in ppm/°C
TCF = x· ∂T
MOS Transistor
V T = V(T0 ) + α(T-T 0 ) + ···, where α ≈ -2.3mV/°C (200°K to 400°K)
µ = KµT-1.5
BJT Transistor
Reverse Current, IS:
1 ∂I S 3 1 VG0
·
= +
IS ∂T T T kT/q
Empirically, IS doubles approximately every 5°C increase
Forward Voltage, vD:
V G0 - v D 3kT/q
∂vD
=
- T ≈ -2mV/°C at vD = 0.6V
∂Τ
T
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -54
Noise in Transistors
Shot Noise
i2 = 2qID∆f (amperes2)
where
q = charge of an electron
ID = dc value of iD
∆f = bandwidth in Hz
i2
2
Noise current spectral density =
∆f (amperes /Hz)
Thermal Noise
Resistor:
v2 = 4kTR∆f (volts2)
MOSFET:
iD2 =
8kTgm∆f
(ignoring bottom gate)
3
where
k = Boltzmann’s constant
R = resistor or equivalent resistor in which the thermal noise is occurring.
gm = transconductance of the MOSFET
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -55
Noise in Transistors - Continued
Flicker (1/f) Noise
 Ia 
iD2 = Kf b ∆f
f 
where
Kf = constant (10-28 Farad·amperes)
a = constant (0.5 to 2)
b = constant (≈1)
Noise power
spectral density
1/f
log(f)
ECE 6421 - Analog IC Design
Fig. 2.6-12
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -56
Design Rules
Design rules are geometrical constraints which guarantee the proper operation of a circuit implemented by
a given CMOS process.
These rules are necessary to avoid problems such as device misalignment, metal fracturing, lack of
continuity, etc.
Design rules are expressed in terms of minimum dimensions such as minimum values of:
• Widths
• Separations
• Extensions
• Overlaps
• Design rules typically use a minimum feature dimension called “lambda”. Lambda is usually equal to
the minimum channel length.
• Minimum resolution of the design rules is typically half lambda.
• In most processes, lambda can be scaled or reduced as the process matures.
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -57
DIODES
BJT Diode
Different configurations
Diode
PC08A
PC08B
Condition
IC = 0
IE = 0
Series
Resistance
rbb’
rbb’+rcc’
VF @10mA
960mV
Breakdown
Voltage
Storage Time
PC08C
PC08E
PC08F
V CB = 0
V EB = 0
VCE = 0
rbb’+rcc’
rbb’/β
rbb’/β + rcc'
rbb’
950mV
950mV
850mV
940mV
920mV
BVEBO
BVCBO
BVCBO
BVEBO
BVCBO
BVEBO
≈70ns
≈130ns
≈80ns
≈6ns
≈90ns
≈150ns
ECE 6421 - Analog IC Design
IE =0
no emitter
PC08D
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -58
MOS Diode
PC09
iD = β(vD-VT)2
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
Page 1 -59
Comparison of the BJT and MOS diodes
Assume the Is = 1fA, βo = 99 and VD = 0.65V for the BJT diodes and β = 300µA/V2 and VT = 0.5V for
the MOS diode. Find the dc current, the static resistance, and the dynamic resistance of the BJT diode in
the first and fourth columns and the MOS diode.
IC=0 diode:
IC 1fA
1fA
ID = β = 99 exp(0.65/0.026) = 99 (7.2x10+10) = 0.727µA ,
ο
1
1 ∂iD Isexp(0.65/0.026) ID
= ∂v =
=
=
V t 35.7kΩ
V tβ ο
rd
D
0.65V
Rstatic = 0.727µA = 893kΩ
r d = 35.7kΩ
VCB=0 diode:
IC 1+βo
ID = IE = IC+IB = α = β Isexp(0.65/0.026) = 72.7µA ,
o
0.65V
Rstatic = 72.7µA = 8.93kΩ
Vt
rd = I = 357Ω
D
MOS diode:
ID = 300µA/V2(0.65-0.5)2 = 6.75µA,
ECE 6421 - Analog IC Design
0.65V
1
1
Rstatic = 6.75µA = 100kΩ , r d ≈ g =
= 11.1kΩ
m
2·300·6.75
 P.E. Allen and J.A. Connelly 2000
IC Passive Components (1/13/00)
•
•
•
•
•
Page 1 -60
SUMMARY
Showed passive components that were compatible with silicon IC technology
Capacitors are inherently the most accurate passive components
Inductors are possible at frequencies in excess of 100Mhz
Modifications to the standard active device include:
- Lateral PNP transistor for a BJT technology
- Lateral BJT with the base the well in CMOS technology
- Substrate BJTs
- High voltage transistors
- Latch up
- ESD protection in CMOS technology
Diodes include BJT and CMOS (BJT diodes are more ideal)
ECE 6421 - Analog IC Design
 P.E. Allen and J.A. Connelly 2000