TRANSMISION LINE II
SHORT LINES
A short line is defined as a line which the effect of capacitive current can be neglected. Figure 1
shows single line representation of short line model, where R and XL are the resistance and
inductive reactance of the loop circuit respectively.
R
XL
IS
IR
Line Impedance
VS
VR
Figure 1
IS represents the sending end current which will be equal in magnitude to the load current IR. VR
represents the receiving end voltage and VS represents the sending end voltage.
The phasor diagram (Figure 2) is constructed by drawing a reference phasor to represent the load
current IR. If the load is operating at a lagging power factor the phasor representing the receiving
end voltage VR is drawn to a suitable scale leading the current phasor by an angle θR (the cosine
of which represents the load power factor).
By scribing arcs representing the sending end voltage Vs, and the line voltage drop VD (drawn to
the same scale as the receiving end voltage) the phasor diagram can be completed. The voltage
drop due to the line resistance is drawn “in phase” (i.e. parallel to) with the current IR.
The voltage drop due to the line reactance is drawn leading the current IR by 900, and hence the
effective values of line resistance and reactance can be estimated for a particular value of load
current.
arc VS
arc Vd
Vd
VS
IRR
VR
θR
θS
IR=IS
Figure 2
IRXL
Having determined the line parameters for a particular load current, calculation of the voltage
drops may be carried out to confirm the experimental results.
Using the results obtained the line regulation can be determined, this is defined as the percentage
rise in voltage at the receiving end when full load is throw off, the sending end voltage remaining
at a constant value, it is therefore given by :
Line Regulation =
VS − VR
x100
VR
Transmission efficiency may also be determined from :
Efficiency =
Power Out
Power In
VR I R cosθ R
VSIScosθ S
=
MEDIUM / LONG LINES
For certain lengths of line the capacitive charging current cannot be neglected and its effect must
be taken into consideration. Two methods have been evolved to determine the characteristics of
such lines.
a)
THE NOMINAL T REPRESENTATION
In this model the total line capacitance is placed (i.e. lumped) at the mid point of the line, and half
the total line resistance and inductive reactance placed at each end of the line (Figure 3).
IS
R/2
XL/2
XL/2
R/2
IR
IC
VS
VC
C
VR
Figure 3
The phasor diagram (Fig. 4) is constructed using load current IR as the referenced phasor. If the
load is operating at a lagging power factor the phasor representing the receiving end voltage
VR is drawn leading the current phasor by an angle θR (the cosine of which represents the load
power factor).
The phasor representing the voltage drop at the receiving end of the line due to line resistance (IR
R/2) is drawn in phase (i.e. parallel to) with the current IR.
The phasor representing the voltage drop at the receiving end of the line due to line inductive
reactance (IR X/s) is drawn leading the current IR by 900. By completing the figure formed by the
three voltage phasors the voltage across the line capacitance (VC) can be determined.
The line charging current IC due to line capacitance is calculated as follows:
IC = 2 π f C VC
IC is drawn at an angle of 900 to the phasor representing the voltage VC. It is then transposed to
the end of the current phasor IR to enable the phasor representing the sending end current IS to be
drawn.
The phasor representing the voltage drop at the sending end of the line due to line resistance
(IS.R/2) is drawn in phase with the current IS and due to line inductive resistance (IS X/2) is drawn
leading the current IS by 900.
By completing the figure formed by the three voltage phasors the sending end voltage VS can be
determined. The sending end power factor is given by the cosine of the angle θS.
arc VS
arc Vd2
Vd2
arc VC
IS (XL/2)
arc Vd1
VS
IS(R/2)
Vd1
VC
IR (XL/2)
IR(R/2)
VR
θS
IC
θR
IS
IR
Figure 4
b)
THE NORMINAL π REPRESENTATION
In this model the total line resistance and inductive reactance is placed (i.e. lumped) at the mid
point of the line, and half the total line capacitance placed at each end of the line (Figure 5).
R
XL
IL
IS
IR
IC2
IC1
VS
C/2
C/2
Figure 5
VR
The phasor diagram (Fig. 6) is constructed using load current IR as reference phasor. If the load is
operating at a lagging power factor the phasor representing the receiving end voltage VR is drawn
leading the current phasor by an angle ∅R (the cosine of which represents the load power factor).
The capacitor current at the receiving end of the line ICI is calculated as follows:
ICT = 2 π f CI VR
The phasor representing this current is drawn leading the receiving end voltage by 900. By
completing the figure formed by the current phasors, the current through the line resistance and
reactance can be determined, and hence the voltage drops due to the line resistance (ILR) and line
reactance (ILX).
The phasor representing the voltage drop due to the line resistance is drawn in phase (i.e. parallel
to) with the current IR. The phasor also representing the voltage drop due to the line inductive
reactance is drawn leading the current I by 900.
By completing the figure formed by these voltage phasors the voltage at the sending end of the
line Vs can be determined. The capacitor current at the sending end of the line IC2 can be
calculated as:
IC2 = 2 π f C2 Vs
The phasor representing this current is drawn leading the sending end voltage Vs by 900.
By completing the figure formed by the current phasors I, IC2 the sending end current I, may be
determined. The sending end power factor is given by the cosine of the angle θS.
arc VS
arc Vd
Vd
VS
ILR
VR
θS
IC2
IC1
θR
IS
IL
IC2
IC1
IR
Figure 6
ILXL