ECE 257 Linear Integrated Analog Circuits Switched
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ECE 257 Linear Integrated Analog Circuits Switched-Capacitor Circuits Shaahin J. Ashtiani Switched-Capacitor Circuits © 2007 S. J. Ashtiani 1 Switched Capacitor Circuits • Basics Operation • Functional Operation Switched-Capacitor Integrator Discrete-Time Signal Processing Switched Capacitor Filters Sample and Hold Circuits Gain Stages • Non-Ideal effects and Practical Solutions Analysis of Sampling Switches Charge injection and Clock Feed-through Bottom-Plate Sampling Effect of op-amp non-idealities Noise Correlated double-sampling Switched-Capacitor Circuits © 2007 S. J. Ashtiani 2 Why SC Circuits? • SC Circuits Discrete-time systems • Accurate realization of filters and gains Accuracy related to matching of capacitors No need to resistors Performance Independent of absolute values of C • Highly linear Independent of shape of waveforms Only settling accuracy is important Switched-Capacitor Circuits © 2007 S. J. Ashtiani 3 Basic Operation: SC Resistor • Iavg= C(V1-V2)/T • Req=T/C=1/fC • Low-frequency approximation Switched-Capacitor Circuits © 2007 S. J. Ashtiani 4 Basic Switched-Capacitor Integrator • Phase Φ1: C1 is charged up tp Vin (Q=C1Vin) • Phase Φ2: C1 charge (Q=C1Vin) is transferred into C2 • Charge transfer equation: C2Vo(nT − T / 2) = C 2Vo(nT − T ) − C1Vi (nT − T ) C2Vo(n) = C 2Vo(n − 1) − C1Vi( n − 1) Switched-Capacitor Circuits Vo(n) C1 z −1 H ( z) = =− Vi(n) C 2 1 − z −1 © 2007 S. J. Ashtiani 5 Sensitivity to Parasitic Capacitance • Basic SC equal resistor is sensitive to parasitics C1 + C p1 z −1 Vo(n) = − Vi (n) C 2 1 − z −1 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 6 Parasitic-Insensitive Integrator • Non-inverting integrator • Delayed Vo(n) C1 z −1 = H ( z) = Vi(n) C 2 1 − z −1 Switched-Capacitor Circuits C2Vo(n) = C2Vo(n − 1) + C1Vi (n − 1) © 2007 S. J. Ashtiani 7 Parasitic-Insensitive Integrator: Operation • Cp2: Always connected to ground • CP1: Connected to ground in Φ2 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 8 Parasitic-Insensitive Integrator: Delay Free • Inverting integrator • Delay Free H ( z) = Vo(n) C1 1 =− Vi(n) C 2 1 − z −1 Switched-Capacitor Circuits C2Vo(n) = C2Vo( n − 1) − C1Vi (n) © 2007 S. J. Ashtiani 9 Switched Capacitor Filters • H(s) to H(z) 2 1 − z −1 Bilinear Transform: Accurate s = − T 1 + z −1 Impulse invariant: Simple but not accurate Switched-Capacitor Circuits h[n] = Thc (nT ) © 2007 S. J. Ashtiani 10 Implementing H(z) by SC Circuits 1 1 C1 − C1 V1 C 2 z −1 ( C 3 1 − z −1 1 ) 1 1 C A 1 − z −1 CA C2 V2 Vo 1 V2 C3 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 11 Example: First-Order Filter − C3 − C2 ( C1 1 − z −1 Switched-Capacitor Circuits ) 1 1 C A 1 − z −1 © 2007 S. J. Ashtiani 12 First-Order Filter − C3 − C2 ( C1 1 − z −1 • DC Gain: 1 1 C A 1 − z −1 ) H (1) = − C2 C3 • Pole: zp = CA C A + C3 • Zero: zz = C1 C1 + C2 Switched-Capacitor Circuits ⎛ C1 + C 2 ⎞ C ⎜⎜ ⎟⎟ z + 1 CA ⎠ CA ⎝ H ( z) = − ⎛ C3 ⎞ ⎜⎜1 + ⎟⎟ z − 1 ⎝ CA ⎠ © 2007 S. J. Ashtiani 13 Design Example • First order filter: -3dB @ 10kHz, 0 @ 50kHz, fs=100kHz, DC Gain=1 • Zero at 50kHz: zz=-1, (Negative capacitor) • Using bilinear transform: zp=10kHz, s=2/T(z-1)/(z+1) Î zp=.53327 • H(z): H ( z) = K ( z + 1) z − 0.53327 H(1)=1 Î K=0.23337 • Assume CA=10pf Î C1=4.376pF C2=-8.752pF C3=8.752pF • Implementing C2: Cross-couple it in a fully differential design Switched-Capacitor Circuits © 2007 S. J. Ashtiani 14 Switch Sharing • Removing redundant switched Switched-Capacitor Circuits © 2007 S. J. Ashtiani 15 Biquad Filter: Low-Q k 2 s 2 + k1s + k 0 H (s) = ⎛ ω0 ⎞ 2 s + ⎜⎜ ⎟⎟ s + ω02 ⎝Q⎠ • Biquad: General second-order system • Any filter can be realized by cascading biquads and firstorders • Low-Q and High-Q implementation Switched-Capacitor Circuits © 2007 S. J. Ashtiani 16 Low-Q Biquad Filter: CT Implementation Switched-Capacitor Circuits © 2007 S. J. Ashtiani 17 Low-Q Biquad Filter: SC Implementation From Analog Integrated Circuit Design (Johns & Martin) Switched-Capacitor Circuits © 2007 S. J. Ashtiani 18 Low-Q Biquad Filter: z domain flow-graph a2 z 2 + a1 z + a0 H ( z) = b2 z 2 + b1 z + 1 • • • • • K3=a0 K2=a2-a0 K1K5=a0+a1+a2 K6=b2-1 K4K5=b1+b2+1 • One degree of freedom for K1,K4 and K5 • Optimum choice for dynamic range: K 4 = K 5 = b1 + b2 + 1 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 19 CT to SW Conversion • Impulse invariance • Rewrite H ( z) = − (K (1++KK)z)z ++(K(KKK− −KK− −2K2)z)z++1 K to 2 2 3 1 5 2 3 2 6 4 5 • for z-1/2 and z1/2 we have: H(jω) is: 3 H ( z) = − ( 6 ( ωT 2 H ( z) = − 2 ωT K 4 K 5 + jK 6 sin(ωT ) + (4 + 2 K 6 )sin ( ) 2 ( ) ( K 4 K 5 + K 6 z1/ 2 − z −1/ 2 z1/ 2 + z1/ 2 − z −1/ 2 ⎛ ωT ⎞ ⎛ ωT ⎞ z1/ 2 = cos⎜ ⎟ + j sin ⎜ ⎟ ⎝ 2 ⎠ ⎝ 2 ⎠ K1 K 5 + jK 2 sin(ωT ) + (4 K 3 + 2 K 2 )sin 2 ( ) K1K 5 + K 2 z1/ 2 − z −1/ 2 z1/ 2 + K 3 z1/ 2 − z −1/ 2 ) ) 2 2 ⎛ ωT ⎞ ⎛ ωT ⎞ z −1/ 2 = cos⎜ ⎟ − j sin⎜ ⎟ ⎝ 2 ⎠ ⎝ 2 ⎠ ) K1K 5 + jK 2 (ωT ) + (K 3 + K 2 / 2 )(ωT ) 2 H ( z) = − K 4 K 5 + jK 6 (ωT ) + (1 + K 6 / 2 )(ωT ) 2 For ωT<<1 K4=K5=ω0T, K6=ω0T/Q • For high Q, large capacitor ratio required Switched-Capacitor Circuits © 2007 S. J. Ashtiani 20 Biquad Filter: High-Q • Biquad HQ K 3 z 2 + (K1 K 5 + K 2 K 5 − 2 K 3 )z + K 3 − K 2 K 5 H ( z) = − z 2 + (K 4 K 5 + K 5 K 6 − 2 )z + (1 − K 5 K 6 ) Switched-Capacitor Circuits © 2007 S. J. Ashtiani 21 Sample and Hold Circuits: Flip-Around 1 1 C Vo Vi 1 • Fast: OTA out does not change: Relaxed SR • Feedback factor =1 • Common-Mode Issue: Input signal CM should be equal to OTA CM Switched-Capacitor Circuits © 2007 S. J. Ashtiani 22 Flip-Around S&H: Fully Differential Φ2 C Φ1 Φ1 Vi+ Vo+ ViΦ1 C Switched-Capacitor Circuits VCMI Φ1 Φ1 Vo- Φ2 © 2007 S. J. Ashtiani 23 Sample and Hold Circuits: Two-Capacitor C 1 1 C Vo Vi 1 1 • OTA Settles: Slower • Insensitive to CM difference Switched-Capacitor Circuits © 2007 S. J. Ashtiani 24 Gain Stage I C2 1 1 C1 Vo Vi 1 1 • Same as S&H: G=-C1/C2 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 25 Gain Stage II • G=1+C1/C2 Switched-Capacitor Circuits © 2007 S. J. Ashtiani 26 Practical Issues and Non-Idealities • • • • • • • MOS Sampling Speed Linearity Switch bootstrapping Charge Injection Jitter Noise Switched-Capacitor Circuits © 2007 S. J. Ashtiani 27 MOS T&H: Simulation Switched-Capacitor Circuits © 2007 S. J. Ashtiani 28 MOS S&H: Tracking Speed & Distorsion • Simple RC model: • τ= 1 RC R≅ t ⎛ − Vo = Vi⎜1 − e τ ⎜ ⎝ ⎞ ⎟ ⎟ ⎠ 1 μcox • R is non-linear! W (VDD − VT − Vi ) L ⎞⎞ t ⎛ Vi ⎛ ⎟ − ⎜⎜ 1− ⎜ 2τ ⎝ VDD −VT ⎟⎠ ⎟ Vo = Vi⎜1 − e ⎟ ⎟ ⎜ ⎠ ⎝ • Tracked signal has harmonic distortion! Switched-Capacitor Circuits © 2007 S. J. Ashtiani 29 MOS S&H: Tracking Distortion 0 -20 Fully Diff Single -40 Vo (dB) -60 -80 -100 -120 -140 -160 0.0 5.0M 10.0M 15.0M 20.0M 25.0M Frequency (Hz) • W=10, L=0.18, Cin=1pF fs=50M, fin=1.56M ,Vin=.5V, Switched-Capacitor Circuits © 2007 S. J. Ashtiani 30 Improving Tracking Speed: T-GATE Resistance (ohm) 160 140 120 100 80 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Input Voltage (V) • Not a good choice for low-voltage technologies Switched-Capacitor Circuits © 2007 S. J. Ashtiani 31 Improving Tracking Speed: Bootstrapping • Improving R by increasing VGS • No terminal-to-terminal voltage exceeds VDD • Overdrive Independent of Vi Switched-Capacitor Circuits © 2007 S. J. Ashtiani 32 Improving Tracking Speed: Bootstrapping Switched-Capacitor Circuits © 2007 S. J. Ashtiani 33 Charge Injection and Clock Feed-through • Error in sampled voltage due to charge injection and clock feed-through • Clock feed-through Independent of Vi ΔVo = • Charge injection Depends on Vi Body effect ΔVo = β c gd c gd + C L VDD WLcox (VDD − Vi − VT ) CL • Charge injection causes harmonic distortion Switched-Capacitor Circuits © 2007 S. J. Ashtiani 34 Canceling Charge Injection • Dummy transistor Dummy transistor: half size 1 1 Vi Vo CL • Tgate as switch NMOS and PMOS have same size Switched-Capacitor Circuits © 2007 S. J. Ashtiani 35 Canceling Charge Injection: Fully Differential Switched-Capacitor Circuits © 2007 S. J. Ashtiani 36 Bottom-Plate Sampling • Q2 turns off first Î Q2 induces Constant charge in C1 • Q1 turns off later ÎQ1 does not add charge in C1 • Induced error is independent of Vin Switched-Capacitor Circuits © 2007 S. J. Ashtiani 37 SC Circuits with Bottom-Plate Sampling Switched-Capacitor Circuits © 2007 S. J. Ashtiani 38 Clock Jitter • Jitter (Δt): Uncertainty in rising and falling of clock signal Δt in the range of 1-100ps Δt Î Δv in sampling Switched-Capacitor Circuits © 2007 S. J. Ashtiani 39 Correlated Double Sampling • Canceling opamp offset and 1/f noise • Store offset in C2’ during sampling phase Switched-Capacitor Circuits © 2007 S. J. Ashtiani 40 Effect of Op-Amp • Limited Gain • Limited Settling Linear settling Nonlinear settling • Non-Linearity Variable gain Slewing Switched • Noise Switched-Capacitor Circuits © 2007 S. J. Ashtiani 41 Limited Gain of op-amp 1 C2 C1 Vo( n) C1 z −1 (1 − λ ) H ( z) = = Vi (n) C 2 1 − (1 − ε ) z −1 Vin Vo 1 A 1− ε = 1 1 C1 1+ A C2 Gain = • • λ= 1 ⎛ C1 ⎞ ⎜1 + ⎟ A ⎜⎝ C 2 ⎟⎠ C1 ⎛ 1 C1 + C2 ⎞ ⎜⎜1 + ⎟⎟ C2 ⎝ A C2 ⎠ SC Integrator: Convert to low-pass filter Sample and hold: Gain error Switched-Capacitor Circuits © 2007 S. J. Ashtiani 42 Linear & Nonlinear Settling T − Vo(n) C1 ⎛⎜ H ( z) = = 1− e τ Vi(n) C 2 ⎜⎝ ⎞ z −1 ⎟ ⎟ 1 − z −1 ⎠ • Linear Settling: Caused gain error • Nonlinear Settling: Input-dependent response Î harmonic distortion High-Slew-Rate op-amp required! Switched-Capacitor Circuits © 2007 S. J. Ashtiani 43 Linear Settling: Feedback Factor τ= 1 C1 + C2 + C P 2πfT C2 • Larger gain Î Larger C1/C2 Î Slower settling • Large input parasitic CP Î Slow settling Switched-Capacitor Circuits © 2007 S. J. Ashtiani 44 Op-Amp Noise 1 C2 C1 C2 C1 Vin Vi Vo 1 Vo CP Vn(t) Vn(t) • Noise: • KT/C Noise • Op-Amp noise Switched-Capacitor Circuits © 2007 S. J. Ashtiani 45