Politecnico di Torino
Master Degree in Electronic Engineering
Analog and Telecommunication Electronics course
Prof. Del Corso Dante
Miniproject:
“ Switched Capacitor: working principles
and real IC-device application ”
Student Name: Paolo Vinella
Student ID: s206827
1
paolo.vinella@studenti.polito.it
Contents
1. Switched Capacitor basics ......................................................................................................... 3
1.1 Realizing a resistor inside integrated circuits ............................................................................. 3
1.2 The need of replacing traditional resistors with Switched Capacitor ........................................ 4
1.3 Switched Capacitor basic element .............................................................................................. 4
1.4 Switched Capacitor working principle: a resistor-like device ..................................................... 5
1.5 Switches: which device? .............................................................................................................. 6
2. Switched capacitors in basic Filters........................................................................................ 7
2.1 Passive I order Low Pass RC cell ............................................................................................... 7
2.2 Active Integrator (I order Low Pass cell) .................................................................................. 8
2.3 Active Integrator Stray Insensitive .......................................................................................... 12
3. Commercial Active Filter: TI MF10 .......................................................................... 14
3.1 Introduction and key parameters ............................................................................................. 14
3.2 Main circuital building block: State Variable Filter ................................................................ 15
3.3 Basic circuit description............................................................................................................ 16
3.4 Design hints common summary................................................................................................ 19
3.5 Modes of operations: design example with MODE#3.............................................................. 20
3.6 Recall on BP, LP, HP responses and parameters .................................................................... 22
3.7 Offset contribution.................................................................................................................... 24
3.8 Design of Fourth Order Chebyshev LP filter: using the entire MF10 ..................................... 25
4. Traditional vs Switched Capacitor Filter: which is better? ............................................ 27
5. Final remarks on Switched Capacitor Filters ..................................................................... 29
References ........................................................................................................................................ 30
2
paolo.vinella@studenti.polito.it
1. Switched Capacitor basics
1.1 Realizing a resistor inside integrated circuits
Resistors are one of the basic building blocks for any analog or digital integrated circuit. They play
an essential role (as voltage dividers, current regulators,…) and cannot be avoided during design.
Inside integrated circuits realized employing silicon (but not only), a resistor can be realized with a
doped semiconductor area: we refer to Diffused Integrated Resistor, which exploit the
microscopic Ohm’s Law. In fact, an uniformly doped area connected with other devices through
ohmic metallic contacts, can be seen as a resistor.
Consider an n-doped volume with doping concentration ND, with physical dimensions L x W x t:
t
ρ = f ( μn , ND )
W
L
Recalling the definition of resistivity:
1
1
ρ= =
σ q μn ND
The sample can be seen as a resistor whose resistance is given, as well known, by the relation:
R=ρ
ρL
L
=
Wt tW
Defining the layer resistance R□, which is given by manufacturing, as:
R□ =
ρ
t
We can express then the equivalent associated resistance R of the device as:
R = R□
L
W
From the manufacturing standpoint, this is realized considering n squares each of which characterized
by R□, putting them in series:
3
paolo.vinella@studenti.polito.it
1.2 The need of replacing traditional resistors with Switched Capacitor
Nowadays, within integrated circuits, where physical layout, space and lithography constrains allow
more and more restrictive, this approach is very space (surface) consuming.
Realizing integrated circuits, the area occupied by a capacitor is far smaller than the one required
by a traditional resistor.
In order to make resistor integration still possible and try to overcome this limitation, another
approach, completely different, can be used: the Switched Capacitor technique. It is based on the
use of a capacitor driven alternatively by a couple (or more) switches between power supply sources.
In a MOSFET-oriented IC, realizing a capacitor is not a big deal, since the same technique used to
realize the MOS gate area can be used.
1.3 Switched Capacitor basic element
The Switched Capacitor is based on two metal plates (realized with polysilicon, a strongly doped
silicon sample) separated by a thin oxide layer.
Although the structure is a “pure” capacitor, however we must take into account the presence of
nonlinearities:
•
C1 is the ideal desired capacitance;
•
CP1 and CP2 are the two parasitic terms introduced by the structure, between which
especially the second one, associated to the bottom oxide plate which separates the structure
from the substrate, can be quite large: even up to the 20-30% in respect to C1!
4
paolo.vinella@studenti.polito.it
1.4 Switched Capacitor working principle: a resistor-like device
Switched capacitor is a technique commonly used to realize filters (but not only) within integrated
circuits, which allows to emulate the behavior of a resistor whose resistance is function of
the clock frequency used to drive the device.
Consider this basic series circuit:
R
I
V2
V1
Assuming V1 > V2, we can write:
V1 - V2
R
I=
Let us now consider a similar system but composed by a capacitor of value C and two switches
in counter phase S1 and S2, connecting alternatively the capacitor to either V1 or V2:
S1
S2
I
V2
C
V1
We can easily derive that:
S1 CLOSED
S2 OPENED
S1 OPENED
� ⟶ Q 1 = C ∙ V1
S2 CLOSED
� ⟶ Q 2 = C ∙ V2
The variation of charge is thus:
∆Q = Q 1 - Q 2 = C ∙ (V1 - V2 )
We can see ∆Q as the variation of the quantity of charge transferred from V1 to V2. The
associated current I is the quantity of charge transferred / second, thus we can divide by the time
T which represents the cycle duration:
I=
C (V1 - V2 )
∆Q
=
= C (V1 - V2 ) fCLK
T
T
Comparing this result with the formula:
I=
V1 - V2
R
We find the equivalent resistance of the system:
REQ =
REQ
1
C fCLK
1
I12
2
5
paolo.vinella@studenti.polito.it
Example: C=5pF ; fCLK=100kHz ⟶ REQ= 2MΩ : very high value with very low capacitor (with
traditional approach, instead, huge amount of silicon area would be required!).
The formal definition for Switched Capacitor working principle can be expressed as:
“ A capacitor, connected alternatively between two low-impedance points (two voltage sources)
driven by two switches, behaves like a resistor put in between these two points”.
The system works with two switches: for this reason, we talk about sampled system. In order to
make the system behave “as” an ideal resistor, keeping an high confidence for the ideality of the
equivalent component, we have to use the device with signals at frequency fS << fCLK .
In order to keep everything work as it should, the switches S1 and S2 are driven by two square waves
Φ1 and Φ2 (digital signals) not overlapped:
S1 ⟶ Φ1
S2 ⟶ Φ2
1.5 Switches: which device?
In order to realize the driving switches, the basic idea is the use of a single nMOS or pMOS:
Φ
Φ
Φ
We can do even better, employing a transmission gate, based on an nMOS in parallel with a
pMOS, which ensures low ON resistance (basically when the switch is closed, it behaves “almost” like
a short circuit, with a negligible voltage drop across it). Driving voltage is again a square wave Φ:
Φ
Φ
It is possible to show that the ON conductance of the device, when it is turned “ON” (ohmic region
for both nMOS and pMOS) is very low, and equal to:
Wp
Wn
= Kp = μp COX
GON = K � VAL - Vtn + Vtp � , having defined K ≐ Kn = μn COX
Ln
Lp
The switch also ensures low VDS dependence (better linearity). MOSFET are good switches: off
resistance near GΩ range; on resistance several tenth of Ω (depending on transistor sizing).
6
paolo.vinella@studenti.polito.it
2. Switched capacitors in basic Filters
The presence of switched capacitors to replace the resistor(s) within filters, both passive and active
(based on OPAMPs) enables the implementation of filters as fully integrated circuits. In fact:
•
The capacitor that replaces the resistor, together with its switches, offers a more compact
•
structure (less occupation area);
Typically, in filters what counts is the ratio between values rather than absolute ones (for
example: C1/C2), allowing to work with small value of capacitances. In fact, we work with
•
a single type of component, and only a good matching (desired ratio) is required.
Error on an absolute value of a parameter can reach up to 30% (tolerance), while error of
ratio of values of capacitances can be reduced even to 0.1%!
•
In general, remove resistors means “remove” dissipated power!
In all the following implementations, for the sake of schematic simplicity, we will consider as switch
an nMOS structure; however, each switch can be replaced by a transmission gate for better RON.
2.1 Passive I order Low Pass RC cell
Let us replace the usual resistor R present in a simple low-pass passive I order filter cell with a
switched capacitor system, from the transfer function standpoint nothing changes, recalling that
.
now we have to introduce however a clock signal and that R = 1�C f
CLK
S1
vi
R= 1�C ∙ f
1 CLK
S2
C1
C2
vo
vi
Φ
C2
In first order approximation, the filter works as usual; the transfer function can be written as:
1
1
H(s) =
=
C2
1 + sRC2
1+s
C1 ∙fCLK
Which complies with a LP profile. The cutoff frequency will be given by the relation:
1
1 C1
=
∙f
fC =
2πRC2
2π C2 CLK
Two important results:
7
paolo.vinella@studenti.polito.it
vo
•
•
Cut-off frequency dependent on the RATIO among two capacitance values;
Cut-off frequency is tunable by varying the frequency fCLK of the signal Φ.
The module and phase of the transfer function H(s) can be described as usual for a low pass filter:
∠H(j2ΰf)
|H(j2ΰf)|dB
0
90°
-20dB/dec
0°
f
fC
fC
0.1fC
10fC
f
2.2 Active Integrator (I order Low Pass cell)
A second straightforward implementation of switching capacitor technique is an SC active integrator,
which can be also seen as a low pass active cell of the first order (that is, filtering plus gain).
Again, the resistor present at the non-inverting input of the operational amplifier can be replaced by
the well-known switching capacitor system:
C2
C2
R1
–
–
vi
+
vi
vo
Φ1 C1
Φ2
+
vo
The transfer function is given by:
H(s) = -
Zc
⟶ H(s) = -ZC2 C1∙fCLK
𝑅𝑅1
⟹
H(s)= -
1 C1
∙f
s C2 CLK
Once again, we find the same peculiarities of the low-pass passive filter:
•
A ratio between two capacitances rather than a set of values per-se (R, C);
•
Something that is frequency dependent. In fact, the transfer function can be seen as the
one of a pole in the origin shifted up by the constant value
frequency:
fC =
1 C1
∙f
2π C2 CLK
C1
C2
∙ fCLK, then we get a pole at
8
paolo.vinella@studenti.polito.it
Qualitatively, the transfer function can be then represented as follows:
∠H(j2ΰf)
|H(j2ΰf)|dB
C1
∙f
C2 CLK
-90°
-20dB/dec
fC
f
f
REMARK: As the transfer function representation allows to see, the problem of this circuit is that
for low frequencies the circuit can easily saturate: in fact, the feedback capacitor becomes an open
circuit and the loop is open, leading to OPAMP saturation at the output. In order to reduce the gain
at low frequencies, a resistor R2 can be put in parallel to the feedback capacitor C that causes:
•
•
for high frequencies: behavior as the usual integrator;
for low frequencies (quasi-DC): behavior as an inverting op-emp.
In fact, in the transfer function the pole in the origin is transformed into a pole not in the origin.
This circuit gives us the chance to go deeper in the circuit analysis in order to see better:
•
•
•
the presence of the switches;
the required characteristics of the driving digital voltages of the switches themselves;
the non-idealities of this circuit and their influences.
First, Φ1 and Φ2 are the two digital binary signals driving the switches and form what is called a
two-phases non-overlapping clock: basically we must guarantee that they never assume the
value HI simultaneously to fully complain with the switching capacitor working principle (correctness
in the charge transfer):
Φ1
t
Φ2
t
The charge that plays the game is Q=C1 ∙ vi , which is then transferred at the output of the circuit:
1. Φ1 active, Φ2 off  charge stored in C1;
2. Φ1 off, Φ2 active  charge moved away from C1 to C2.
9
paolo.vinella@studenti.polito.it
INTEGRATOR-LIKE BEHAVIOR: WHY?
Why this circuit can be considered an integrator? We can give the same answer in different ways:
1. Analyzing the “traditional” circuit (that is, the one with the “real” resistor) the transfer
function is:
1
H(s)= sR1 C2
However, we know that dividing by s means integrating in the time domain. In fact, if we
analyze back the simplest integrator reasoning on currents, voltages and charges, we can write:
C2
I
R1 I
–
+
vi
vo
Starting from the definition of current, together with the capacitor voltage-charge relationship,
and applying the concept to our circuit configuration where we have a virtual ground thanks
to the presence of the operation amplifier, we can easily derive that:
I(t)=
dQ(t)
dt
Qc (t)=C2 vc (t)
�⎯⎯⎯⎯⎯⎯⎯⎯⎯�
I(t)=C2
dvc
dt
vc =-vo
�⎯⎯⎯�
I(t)=-C2
dvo
dt
The current I(t) which flows across the capacitor is the same current provided by the input
branch of the OPAMP circuit (I- negligible), then:
vi (t)
dvo
= - C2
R1
dt
⟶
vo (t)
�
vo (0)
⇒
t
dvo = - �
0
vi (t)
dt
R1 C2
vo (t) = vo (0) -
⇒
vo (t) - vo (0)= -
t
1
� vi (t)dt
R1 C2 0
t
1
� vi (t)dt ⇒
R1 C2 0
Then, we can conclude that the output voltage at a given time instant t, is proportional to
the integral of the input voltage until that time t.
2. Starting instead from the equivalent switching capacitor circuit (replacing the resistor with
its discrete-time equivalent), we can reason in terms of transferred charge from the input to
the output. In fact, every clock cycle:
• Φ1 active, C1 absorbs a charge Q=C1vi
• then, Φ2 active: the same charge is moved away from C1 to C2. Assuming
vi=Vi=const, during Φ2 we can write that the output changes by C1Vi/C2 each clock
cycle:
Q
C1
Vo = = V
C2
C2 i
10
paolo.vinella@studenti.polito.it
Approximating the staircase waveform by a ramp, we note that the circuit behaves as an
integrator:
Vi
C1
VO
C2
C2
S2
S1
Vi
VO
C1
t
The final value of Vo after k clock cycles TCK can be written as:
Vo (kTCK) = Vo [(k-1)TCK ] - Vi [(k-1)TCK ]∙
C1
C2
Again, as stated at the beginning of this report, we can see it as a sampled system.
Neglecting the nMOS switches’ parasitic capacitances, both C1 and C2, since realized within the
same integrated circuit, exhibit parasitic capacitive effects between each of their two terminals and
ground:
CP21
CP22
C2
–
vi
Φ1 C1
+
Φ2
vo
CP11
CP12
The presence of parasitic capacitors to charge and discharge will then clearly influence the ideal
behavior of the device. However:
•
•
•
CP12 is between GND and GND: no effect!
CP21 is between virtual GND of the OPAMP and GND: again, no effect!
CP22 is between vO and GND: since it is in parallel to (driven by) vO, no effect on C2 charge!
•
CP11 is in parallel with C1 => the “real” C1 is then C1+CP11: problematic!
We can do better, let us see how in the next paragraph.
11
paolo.vinella@studenti.polito.it
2.3 Active Integrator Stray Insensitive
In order to avoid the influence of parasitic components, the idea is: let us put C1, the capacitor
between input voltage and inverting input of the OPAMP, in series instead of parallel like done
before.
4-SWITCH CELL
In practice, this is done using a 4-switch cell, which makes us of four nMOS. In order to create
again the commutation needed for switching capacitor principle, for each switch we use two dual
nMOS that connect each terminal of the capacitor C1 either to the voltage or to ground. We still
use the two digital voltages Φ1 and Φ2:
C
vi
Φ1
Φ1
Φ2
IO
Φ2
The cell requires output to ground. By doing that we can easily see that we can re-create an
equivalent resistor again, since:
•
•
Φ1 active, Φ2 off  C will charge to Q=viC
Φ2 active, Φ1 off  C will be discharged to ground, and since the ground is present also at
the output, the current here will be taken from vi contribution! In other words:
o
Charge Q taken from the input voltage fCLK/sec times: thus we can write
o
IO=QfCLK
The equivalent resistance R=V/IO is, in our case, given by:
Req =
vi
vi
=
QfCLK
vi CfCLK
⟹
R=
1
CfCLK
We have obtained the same result, in terms of equivalent resistance of this circuit, already derived
for the previous switching capacitor system seen before!
REMARK: we can easily obtain an INVERTING 4-SWITCH CELL by exchanging the position
of Φ1 and Φ2 in the output branch: now IO=-QfCLK (current with opposite sign).
The system still works as switched capacitor needed by the inverting integrator. After all, recalling
that C in the integrator previously seen is connected either between vi and GND or between GND
and (virtual) GND of the OPAMP we obtain the same result:
12
paolo.vinella@studenti.polito.it
•
•
Φ1 active, Φ2 off  C connected between vi and (virtual) GND;
Φ1 off, Φ2 active  C connected between GND and GND.
Then, the 4-switch cell is plugged in the usual active integrator overall circuit, resulting into:
C2
C1
–
vi
Φ1
+
Φ1
Φ2
vo
Φ2
Observing the charge transfer we can observe this slight variation due to the new layout:
1. Φ1 active, Φ2 off  charge in C1 is coming from the input: Q=C1vi ;
2. Φ1 off, Φ2 active  charge on C1 must become zero, flowing towards ground: it is then
moved away from C1 to C2.
Finally, we can get rid of the influence of parasitic capacitances: let us look at the associated real
circuits with the parasitic part (again, highlighted in red color):
CP21
CP11
CP22
C2
CP12
C1
–
vi
Φ1
Φ1
Φ2
+
vo
Φ2
Regarding C2, its parasitic terms are not influencing anything like before:
•
•
CP21 is between virtual GND of the OPAMP and GND: no effect!
CP22 is between vO and GND: since it is in parallel to (driven by) vO, no effect on C2 charge!
Concerning C1, now no influence at all of the parasitic parts. In fact:
•
•
CP11 charge is moved to GND, not to C1 or C2! It is either in parallel to vi during Φ1 or
between two grounds during Φ2.
CP12 is connected to 0V points (either virtual or physical ground): no charge stored!
REMARK: using the inverting 4-switch cell we can realize a non-inverting active integrator!
13
paolo.vinella@studenti.polito.it
3. Commercial Active Filter: TI MF10
3.1 Introduction and key parameters
The TI MF10, namely the Texas Instrument MF10-N Universal Monolithic Dual Switched
Capacitor Filter, is characterized by the following features:
•
It consists of 2 independent general purpose CMOS active filter building blocks.
•
Each block, together with an external clock and 3 to 4 resistors, can produce various 2nd
•
order functions at the same time.
Each building block has 3 output pins:
o
One of the outputs can be configured to perform either an allpass, highpass or a
notch function;
o
The remaining 2 output pins perform lowpass and bandpass functions.
•
The center frequency has some peculiarities:
o For the lowpass and bandpass 2nd order functions, can be either directly dependent
on the clock frequency, or can depend on both clock frequency and external resistor
ratios;
o For the notch and allpass functions, it is directly dependent on the clock frequency;
o For the highpass, it depends on both resistor ratio and clock.
•
Up to 4th order functions can be performed by cascading the two 2nd order building
blocks of the MF10-N.
•
Higher than 4th order functions can be obtained by cascading MF10-N packages.
•
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and
Chebyshev) can be formed.
Features
•
•
•
•
•
•
•
•
Easy to Use
Clock to Center Frequency Ratio Accuracy ±0.6%
Filter Cutoff Frequency Stability Directly Dependent on External Clock Quality
Low Sensitivity to External Component Variation
Separate Highpass (or Notch or Allpass), Bandpass, Lowpass Outputs
fO × Q Range up to 200 kHz
Operation up to 30 kHz
20-pin 0.3″Wide PDIP Package or 20-pin Surface Mount (SOIC) Wide-Body Package
14
paolo.vinella@studenti.polito.it
Parametrics
3.2 Main circuital building block: State Variable Filter
In precision filters, it is most desirable to have an independent “handle” for each of three basic filter
parameters: resonant frequency (f0), Q or quality factor, and the passband gain (H0). As a general
rule, the degree of tunability increases with the number of amplifiers used.
The state variable active filter, based on three OPAMPs, is the most popular for 2nd order designs.
Let us take the occasion to mention its basic working principle. The device offers simultaneously
three outputs: HP, LP and BP. The basic idea is to consider the transfer function HHP(s) and
integrate it (that is, multiply it by 1/s in the Laplace domain) in order to obtain a function of the
kind HBP(s) and then repeat once again the procedure to obtain an HLP(s).
The building block and the associated transfer functions general expressions are the following:
15
paolo.vinella@studenti.polito.it
VA
s2
=−
Vi
A2 s 2 + A1 s + A0
VHP
𝐁𝐁𝟐𝟐 𝐬𝐬 𝟐𝟐
= 𝐇𝐇𝐇𝐇𝐇𝐇 (𝐬𝐬) = −
𝟐𝟐
Vi
𝐀𝐀𝟐𝟐 𝐬𝐬 + 𝐀𝐀𝟏𝟏 𝐬𝐬 + 𝐀𝐀𝟎𝟎
VBP
𝐁𝐁𝟏𝟏 𝐬𝐬
= 𝐇𝐇𝐁𝐁𝐁𝐁 (𝐬𝐬) = −
Vi
𝐀𝐀𝟐𝟐 𝐬𝐬 𝟐𝟐 + 𝐀𝐀𝟏𝟏 𝐬𝐬 + 𝐀𝐀 𝟎𝟎
VLP
𝐁𝐁𝟎𝟎
= 𝐇𝐇𝐋𝐋𝐋𝐋 (𝐬𝐬) = −
𝟐𝟐
Vi
𝐀𝐀𝟐𝟐 𝐬𝐬 + 𝐀𝐀 𝟏𝟏 𝐬𝐬 + 𝐀𝐀𝟎𝟎
The implementation of this block diagrams makes use of OPAMPs as adder or integrator.
A major shortcoming of this type of filter is that resonant frequency accuracy is only as good as the
capacitors used. In high volume production, to minimize filter tuning procedures, costly, low-tolerance,
lowdrift capacitors are required. Furthermore, these filters use a fair number of components; 3
OPAMPs, 7 resistors and 2 capacitors for each 2nd order section.
3.3 Basic circuit description
To offer designers an attractive alternative to these types of active filters, a device would have to:
1.
2.
3.
4.
5.
eliminate critical capacitors entirely
minimize overall parts count
provide easy tunability of filter parameters
allow for the design of all five filter responses
simplify design equations.
These are the design objectives behind the development of the MF10. Recent advances in sampledata techniques permit the construction of an op amp integrator on a monolithic substrate without
the need for any external capacitors thanks to switched capacitor approach.
The integrator is a key factor in filter designs for establishing the overall filter time constant and,
therefore, its resonant frequency. The MF10 contains, in one 20-pin DIP package, all of the necessary
active and reactive components to construct two complete 2nd order state variable type active filters.
The only external requirements are for resistors to establish the desired filter parameters.
16
paolo.vinella@studenti.polito.it
Digital and Analog
positive power supplies
(can be tied together)
Used in AllPass (input to S1 then
switch 1 points to LP out (that is,
no filtering: simple short!)
Notch/AllPass/HighPass output
BP output
LP output
Input “Vi”
Clock input to
drive upper filter
INTEGRATORS
(driven by CK)
Defines
fCLK/f0 ratio
connects one of the inputs of
each filter's second summer
to either GND or LP output
Defines supply
for MF10
Digital and Analog
negative power supplies
(can be tied together)
To keep the device as universal as possible, the outputs of each section of each filter are brought out.
This allows designs for all five filtering functions: lowpass, bandpass, highpass, allpass, and
bandreject or notch filters. With two independent 2nd order sections in one package, cascading to
achieve 4th order responses can easily be accomplished. Additionally, any of the classical filter
response types such as Butterworth, Chebyshev, Bessel and Cauer can be implemented.
3-INPUT SUMMING STAGE
Between the output of the summing op amp and the input of the first integrator there is a unique
3-input summing stage where two of the inputs are subtracted from the third. One of the (−)
inputs is brought out to serve as the signal input for some filter configurations. The other (−) input
is connected through an internal switch to either the lowpass output or analog ground depending
upon the desired filter implementation. The direction of this input connection is common to both
halves of the MF10 and is controlled by the voltage level on the SA/B input terminal: when tied to
VD+ [the (+) supply], the switch connects the lowpass output, and when tied to VD- [the (−) supply],
the connection to ground is made.
In some applications one half of the MF10 may require that both of the (−) inputs to this summer
be connected to ground, while the other side requires one to be connected to the lowpass output and
17
paolo.vinella@studenti.polito.it
the other to ground. For this, the SA/B control should be tied to the (−) supply and the connection
to the lowpass output should be made externally to the S1A (S1B) pin.
CLOCK
A clock with close to 50% duty cycle is required to control the resonant frequency of the filter.
Either TTL or CMOS logic compatible clocks can be accommodated, whether the MF10 is powered
from split supplies or a single supply, by simply grounding the level shift (L Sh) control pin.
Filter center frequency accuracy and stability are only as good as the clock provided. Standard
crystal oscillators, combined with digital counters, can provide very stable clocks for specific
filter frequencies. A relatively new device from Texas Instruments COPS™ family of microcontrollers
and peripherals, the COP452 programmable frequency generator/counter, finds a unique use with
the MF10. This low cost device can generate two independent 50% duty cycle clock
frequencies. Each clock output is programmed via a 16-bit serial data word (N). This allows over
64,000
different
clock
frequencies
for
the
MF10
from
a
single
crystal
(“PROGRAMMABLE DUAL CLOCK GENERATOR”):
CLOCK/CENTRAL FREQUENCY RATIO AND OUTPUT EFFECTS
The resonant frequency of each filter is directly controlled by its clock. A tri-level control pin sets
the ratio of the clock frequency to the center frequency (the 50/100/CL pin) for both halves. When
this pin is tied to V+ the center frequency will be 1/50 of the clock frequency. When tied to midsupply potential (that is, ground, when biased from split supplies) provides 100 to 1 clock to center
frequency operation. When this pin is tied to V− a power saving supply current limiter shuts down
operation and rolls back the supply current by 70%.
The MF10 is intended for use with center frequencies up to 20 kHz, and is guaranteed to operate
with clocks up to 1 MHz. This means that for center frequencies greater than 10 kHz, the 50 to 1
clock control should be used.
The effect of using 100 to 1 or 50 to 1 clock to center frequency ratio manifests itself in
the number of “stair-steps” apparent in the output waveform. The MF10 closely
approximates the time and frequency domain response of continuous filters (RC active filters, for
example) but does so using sampling techniques. The clock to center frequency control determines
the number of samples taken (1 per clock cycle) in one cycle of the center frequency. Therefore, as
shown below, 100 to 1 clocking provides a smoother looking output as it has twice as many samples
per cycle.
18
paolo.vinella@studenti.polito.it
For most audio applications, the audible effects of these step edges and the clock frequency
component in the output are negligible as they are beyond 20 kHz. To obtain a cleaner output
waveform, a simple passive RC lowpass can be added to the output to serve as a smoothing filter
without affecting the MF10 filtering action.
Several of the modes of operation (discussed in a later section) allow altering of the clock to center
frequency ratio by an external resistor ratio. This can be used to obtain center frequencies of
values other than 1/50 or 1/100 of the clock frequency. In multiple stage tuned filters, the
center frequency of each stage can be set independently with resistors to allow the overall filter to
be controlled by just one clock frequency.
(ANTI)ALIASING
All of the rules of sampling theory apply when using the MF10. The sampling rate, or clock
frequency, should be at least twice the maximum input frequency to produce the best
equivalent to a continuous time filter. High frequency components in the input signal that approach
the clock frequency will generate aliasing signals which appear at the output of the lower frequency
filter and are indistinguishable from valid passband signals. Bandlimiting the input signal to
attenuate these potential aliasing frequencies is the best preventative measure. In most
applications, aliasing will not be a problem as the clock frequency is much higher than the passband
of interest. In the event that a much higher clock frequency is required, the modes of operation which
utilize external resistor ratios to increase the clock to center frequency ratio can extend the clock
frequency to greater than 100 times the center frequency. By using a higher clock frequency, the
aliasing frequencies are correspondingly higher. The limiting factor, with regard to increasing the
clock to center frequency ratio, has to do with increased DC offsets at the various outputs.
3.4 Design hints common summary
The following is a general summary of design hints common to all modes of operation:
1. The maximum supply voltage for the MF10 is ±7V or just +14V for single supply operation.
The minimum supply to properly bias the part is 8V.
2. The maximum swing at any of the outputs is typically within 1V of either supply rail.
3. The internal op amps can source 3 mA and sink 1.5 mA. This is an important criterion when
selecting a minimum resistor value.
19
paolo.vinella@studenti.polito.it
4. The maximum clock frequency is typically 1.5 MHz.
5. To insure the proper filter response, the fo×Q product of each stage must be realizable by the
MF10. For center frequencies less than 5 kHz, the fo×Q product can be as high as 300 kHz
(Q must be less than or equal to 150). A 3 kHz bandpass filter, for example, could have a Q
as high as 100 with just one section. For center frequencies less than 20 kHz, the allowable
fo×Q product is limited to 200 kHz. A 10 kHz bandpass design using a single section should
have a Q no larger than 20.
6. Center frequency matching from part to part for a given clock frequency is typically ±0.2%.
Center frequency drift with temperature (excluding any clock frequency drift) is typically
±10 ppm/°C with 50:1 switching and ±100 ppm/°C for 100:1.
7. Q accuracy from part to part is typically ±2% with a temperature coefficient of ±500 ppm/°C.
8. The expressions for circuit dynamics given with each of the modes are important. They
determine the voltage swing at each output as a function of the circuit Q. A high Q bandpass
design can generate a significant peak in the response at the lowpass output at the center
frequency.
9. Both sides of the MF10 are independent, except for supply voltages, analog ground, clock to
center frequency ratio setting and internal switch setting for the three input summing stage.
In the following descriptions of the filter configurations, f0 is the filter center frequency, H0 is the
passband gain and Q is the quality factor of the complex pole pair and is equal to f0/BW where BW
is the −3 dB bandwidth measured at the bandpass output.
3.5 Modes of operations: design example with MODE#3
There are six basic configurations (modes of operation) for the 2nd order sections in the MF10 to
realize a wide variety of filter responses. In all cases, no external capacitors are required. Design is a
simple matter of establishing a few resistor ratios to set the desired passband gain and Q and
generating a clock for the proper resonant frequency. Each 2nd order section can be treated in a
modular fashion, with regard to individual center frequency, Q and gain, when cascading either the
two sections within a package or several packages for very high order filters.
Mode
BP
LP
1
*
*
1a
HOBP1 = −Q
HOBP2 = +1
HOLP + 1
2
*
*
3
*
*
*
3a
*
*
*
4
*
*
5
*
*
6a
6b
*
HOLP1 = +1
HOLP2 = -R3/R2
HP
N
No. of
Resistors
Adjustable fCK/f0
3
No
2
No
3
Yes (above fCK/50 or
4
Yes
7
Yes
*
3
No
*
4
AP
*
*
*
*
Notes
May need input buffer. Poor
dynamics for high Q.
fCK/100)
Universal State-Variable Filter.
Best general-purpose mode
As above, but also includes
resistor-tuneable notch
Gives Allpass response with
HOAP =−1 and HOLP = −2
Gives flatter allpass response
than above if R1=R2 = 0.02R4
3
Single pole
2
Single pole
20
paolo.vinella@studenti.polito.it
Mode 3 is the one that we will take as design example, since it represents a good starting point for
the realization of a generic filtering, allowing to obtain as output simultaneously a low-pass, a
band-pass and an high-pass. The IC also allows to tune independently gain, quality factor
and cut-off/central frequency.
This configuration is the classical state variable filter implemented with only 4 external resistors.
This is the most versatile mode of operation, since the clock to center frequency ratio can be
externally tuned either above or below the 100 to 1 or 50 to 1 values. The circuit is suitable for
multiple stage Chebyshev filters controlled by a single clock:
…which looks pretty similar to the equivalent “textbook” State Variable Filter (switched-capacitor
filter utilizes non-inverting integrators):
The design equations for this filter configuration are:
f0 =
fCLK R2
�
100 R4
or
f0 =
fCLK R2
�
50 R4
H0 HP =HP gain �f→
;
R2 R3
Q=�
∙
R4 R2
fCLK
R2
�= R1
2
H0 BP =BP gain(f=f0 )= H0 LP =LP gain (f→0)= -
R3
R2
R4
R1
21
paolo.vinella@studenti.polito.it
3.6 Recall on BP, LP, HP responses and parameters
The equations just mentioned uniquely define the behavior of the filter (for example, BLOCK A).
Clearly, for the second block we can implement another kind of configuration.
In this paragraph, we review the main parameters of filters in order to further remark the relation
with the design equations above.
II ORDER BP RESPONSE
II ORDER LP RESPONSE
(a)
II ORDER HP RESPONSE
22
paolo.vinella@studenti.polito.it
II ORDER NOTCH RESPONSE
II ORDER ALLPASS RESPONSE
FILTERS RESPONSE AS FUNCTION OF Q
Bandpass
Low Pass
Notch
High-Pass
All-Pass
23
paolo.vinella@studenti.polito.it
3.7 Offset contribution
The MF10-N's switched capacitor integrators have a higher equivalent input offset voltage
than would be found in a typical continuous-time active filter integrator. This is the
equivalent circuit of the MF10-N from which the output DC offsets can be calculated:
Typical values for these offsets with SA/B tied to V+ are:
VOS1 = opamp offset = ±5 mV
VOS2
= −150 mV @ 50:1
−300 mV @ 100:1
VOS3
= −70 mV @ 50:1
−140 mV @ 100:1
When SA/B is tied to V−, Vos2 will approximately halve. The DC offset at the BP output is equal to
the input offset of the lowpass integrator (VOS3). The offsets at the other outputs depend on the
mode of operation and the resistor ratios; for example, for the MODE#3 previously considered:
For most applications, the outputs are AC coupled and DC offsets are not bothersome
unless large signals are applied to the filter input. However, larger offset voltages will cause clipping
to occur at lower AC signal levels, and clipping at any of the outputs will cause gain nonlinearities
and will change f0 and Q.
When operating in Mode 3, offsets can become excessively large if R2 and R4 are used to make
fCLK/f0 significantly higher than the nominal value, especially if Q is also high: the offset voltage
at the lowpass output can reach in worst case about +1V. Where necessary, the offset voltage
can be adjusted by using the circuit below. This allows adjustment of VOS1 (“ TRIMMING”):
24
paolo.vinella@studenti.polito.it
3.8 Design of Fourth Order Chebyshev LP filter: using the entire MF10
Suppose to realize:
•
•
•
•
•
Fourth-order Chebyshev low-pass filter
1 dB ripple
unity gain at DC
cut-off frequency fc=1000 Hz
fCLK=100 kHz
As the system order is four, it is realizable using both second-order sections of an MF10-N.
Many filter design texts include tables that list the characteristics (f0 and Q) of each of the secondorder filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined
above, such a table yields the following characteristics:
f0_A = 529 Hz ; QA = 0.785
f0_B = 993 Hz ; QB = 3.559
For unity gain at DC, we also specify:
H0_A = 1 ;
H0_B = 1
The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and
a 100 kHz clock signal is available. However, be CAREFUL: the required center frequencies for the
two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100.
It will be necessary to adjust externally fCLK/f0 .
Mode 3 can be used to produce a low-pass filter with resistor-adjustable center frequency.
In most filter designs involving multiple second-order stages, it is best to place the stages with
lower Q values ahead of stages with higher Q, especially when the higher Q is greater than
0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a
stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency
and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower
Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a convenient value for the input resistance:
R1A = 20kΩ. The absolute value of the passband gain HOLP_A needs to be made equal to 1:
H0 LP_A = -
R4A
R1A
→
R4A = R1A = 20kΩ
If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency
ratio, we find R2A by:
f0_A =
fCLK R2
�
→ R2A = 5.6kΩ
100 R4
The condition on QA allows to determine R3A:
25
paolo.vinella@studenti.polito.it
R2 R3
QA =�
∙
R4 R2
→ R3A = 8.3kΩ
The resistors for the second section are found in a similar fashion:
R1B = 20kΩ ; R4B = R1B = 20kΩ ; R2B = 19.7kΩ ; R3B = 70.6kΩ
Choosing a 5V Power Supply, 0V–5V TTL, the circuit schematic is then:
CASCADING
done by connecting
LPA output to input
INVB through input
resistance R1B of
block B
Output taken
from LPB pin
Input fed to
block A
Same CLK for
both filter blocks!
26
paolo.vinella@studenti.polito.it
4. Traditional vs Switched Capacitor Filter: which is better?
Clearly, the answer to this question depends first of all on the parameter we consider:
Parameter
Switched Capacitor Filter
Traditional Filter
To achieve high accuracy, requires
ACCURACY
COST
Better accuracy: providing
accurate clock, typical centerfrequency accuracy is about 0.2%
(worst case: 0.4-1.5%).
For complex designs, very
inexpensive and take little PCB
space
the use
of either very accurate resistors,
capacitors, and sometimes inductors,
or trimming of component values
to reduce errors: costly!
For easy design, a traditional RC
one-pole filter fast to build and
inexpensive, for growing complexity
and accuracy cost increases
SC Filter use integrators as building
blocks, and to keep small capacitors
and enabling still for high time
constant, large input resistor is
NOISE
required which produce higher
thermal noise: typically, at the
output: 100µV-300µVrms over 20kHz
BW.
Generate very little noise (just the
thermal noise of resistors)
Also, some clock feed through is
present at the output (order of
10mVpp): use an RC network
OFFSET
VOLTAGE
FREQUENCY
RANGE
Quite high: from few to 100mV,
sometimes even over 1V. Not
suggested for DC precision
applications.
Offset coming from OPAMP and the
DC gain of the various filter stages,
can be optimized up to less than
1mV.
Typically from 0.1Hz to 100kHz
To work at low frequencies, it will
require large and expensive reactive
components.
27
paolo.vinella@studenti.polito.it
TUNABILITY
COMPONENT
COUNT /
PCB AREA
ALIASING
DESIGN
EFFORT
Easy, just change the clock
frequency, enabling variations up to
5 to 6 decades without external
circuitry.
Very difficult to vary center
frequency without varying the value
of several components.
A total winner: a single dedicated
monolithic filter use no external
components other than clock, even
for multiploe transfer functions.
Even resistor-programmable ones
take less space.
They need a capacitor or inductor
per pole, for active approaches at
least one OPAMP, two resistors and
two capacitors per second-order
filter.
They are sampled-data devices:
susceptible to aliasing when the
input signal contains frequencies
higher than one-half the clock
frequency. May consider add an RC
network at filter input.
They are not sampled systems.
Frequency limitations due to
OPAMP.
Nowadays, software tools (like WEBENCH Active Filter Designer) allow the
designer to put less manual efforts while sizing a filter.
28
paolo.vinella@studenti.polito.it
5. Final remarks on Switched Capacitor Filters
Switched-capacitor filter has become widely available in monolithic form during the last few years.
The switched-capacitor approach overcomes some of the problems inherent in standard active filters,
while adding some interesting new capabilities.
Switched-capacitor filters need no external capacitors or inductors, and their cutoff frequencies are
set to a typical accuracy of ±0.2% by an external clock frequency. This allows consistent, repeatable
filter designs using inexpensive crystal-controlled oscillators, or filters whose cutoff frequencies are
variable over a wide range simply by changing the clock frequency.
In addition, switched-capacitor filters can have low sensitivity to temperature changes.
Switched-capacitor filters are clocked, sampled-data systems; the input signal is sampled at a high
rate and is processed on a discrete-time, rather than continuous, basis. This is a fundamental
difference between switched-capacitor filters and conventional active and passive filters, which are
also referred to as “continuous time” filters.
The operation of switched-capacitor filters is based on the ability of on-chip capacitors and MOS
switches to simulate resistors. The values of these on-chip capacitors can be closely matched to other
capacitors on the IC, resulting in integrated filters whose cutoff frequencies are proportional to, and
determined only by, the external clock frequency.
Now, these integrated filters are nearly always based on state-variable active filter topologies, so they
are also active filters, but normal terminology reserves the name “active filter” for filters built using
non-switched, or continuous, active filter techniques.
The primary weakness of switched-capacitor filters is that they have more noise at their outputs both random noise and clock feed through - than standard active filter circuits.
National Semiconductor builds several different types of switched-capacitor filters. The LMF100 and
the MF10 can be used to synthesize any of the filter types, simply by appropriate choice of a few
external resistors.
The values and placement of these resistors determine the basic shape of the amplitude and phase
response, with the center or cutoff frequency set by the external clock.
The filter block of these IC with external resistors provides low-pass, high-pass, and bandpass outputs.
Note that this circuit is similar in form to the universal (traditional) state-variable filter, except that
the switched-capacitor filter utilizes non-inverting integrators, while the conventional active filter
uses inverting integrators.
Changing the switched-capacitor filter's clock frequency changes the value of the integrator resistors,
thereby proportionately changing the filter's center frequency. The LMF100 and MF10 each contain
two universal filter blocks, capable of realizing all of the filter types.
29
paolo.vinella@studenti.polito.it
References
•
Slides “Swiched Capacitor Filters” of academic course “Analog and Telecommunication
Electronics” taught by Prof. Del Corso Dante, Politecnico di Torino, Academic Year 20132014
- Course information:
https://didattica.polito.it/pls/portal30/sviluppo.guide.visualizza?p_cod_ins=01NVD
OQ&p_a_acc=2014&p_lang=EN
-
Course dedicated page:
http://areeweb.polito.it/didattica/corsiddc/01NVD/
-
Slides on Switched Capacitor:
http://areeweb.polito.it/didattica/corsiddc/01NVD/Lessons/ATLCEE26.pdf
•
Personal lecture notes of academic course “Applied Electronics” taught by Prof. Sansoè
Claudio, Politecnico di Torino, Academic Year 2011-2012
- Course information:
https://didattica.polito.it/pls/portal30/sviluppo.guide.visualizza?p_cod_ins=04ATIN
X&p_a_acc=2012
•
Slides “Switched-Capacitor Circuits” by David Johns and Ken Martin, University of Toronto
- Slides webpage:
http://www.eecg.toronto.edu/~johns/ece1371/slides/10_switched_capacitor.pdf
•
Texas Instrument website at http://www.ti.com/product/mf10-n
•
Slides “Circuiti per l’Elaborazione del Segnale: Capacità Commutate” of academic course
“Microelectronics” taught by Prof. Barbaro Massimo, Università di Cagliari, Dep. Of Electric
and Electronic Engineering
- Slides webpage:
http://www.diee.unica.it/eolab2/MICROEL/09/06ue_switcap.pdf
•
VLSILAB.POLITO.IT material by Delaurenti Marco, section “Filtri a capacità commutate”
- Webpage:
http://www.vlsilab.polito.it/thesis/jox/node122.html
30
paolo.vinella@studenti.polito.it