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Optical Front-End System Reference Design
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Optical Front-End Design With Demonstrated
System Performance
High-Speed Amplifier Signal Path With Bandwidth
Greater Than 120 MHz
High-Speed 14-Bit ADC With JESD204B Interface
Ultrafast Laser-Diode Driver and Laser Diode to
Generate Tx Signal
Avalanche Photodiode (APD) Front-End With
Onboard High-Voltage Supply
High-Speed Transimpedance Amplifier for I-to-V
Conversion
A Fully Differential Amplifier (FDA) to Drive the
ADC
Flexibility to Easily Change Components in the
Optical, Amplifier, or Data-Converter Signal-Path
ASK Our E2E Experts
Featured Applications
•
•
•
•
•
•
•
•
Laser
driver
OTDR
Optical Amplifiers
CAT-Scanner Front Ends
Photodiode Monitoring
Machine Vison
Distance Measurement
Missle Guidance
3D Scanning
Optical
attenuator
Pulse trigger
TSWJ1456
controller board
Trigger and
data capture
10- to 60-V
supply
THS4541
OPA857
+
-
ADC34Jx
VOCM
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
TINA-TI is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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1
Key System Specifications
1
2
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Key System Specifications
Parameter
Specification
Supply voltage
5-V external supply
Analog bandwidth
120 MHz
ADC sampling rate
160 MSPS
Maximum system gain
100 kΩ
Programmable transimpedance gain
5 kΩ/20 kΩ
Maximum signal swing
1 VPP
Noise performance
≥ 60-dB SNR
Averaged noise performance
< 10-µVRMS
Optical Front-End System Reference Design
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System Description
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2
System Description
Figure 1 is a detailed block diagram of the evaluation system and subblocks. The system is an interface of
the following four different PCBs.
• Laser-diode driver + laser-diode board
• Amplifier signal-chain board
• ADC34J45, analog-to-digital converter (ADC) board
• TSW14J56 digital-capture board
A high-speed laser driver pulses the laser diode that transmits an optical pulse through the fiber. The
optical attenuator controls the strength of the optical pulse incident on the photo-diode without changing
the operating point of the laser diode or its driver. A high-speed photodiode placed in close proximity to
the transimpedance amplifier converts the optical energy into an output current. The transimpedance
amplifier converts the current into a pseudo-differential output voltage. The subsequent fully differential
amplifier (FDA) stage converts the signal to a fully differential signal and level-shifts the output commonmode to match the ADC. The FDA drives the ADC through a doubly terminated 50-Ω resistor.
iC-HB 155-MHz laser
driver board
Optical attenuator
and optical fiber
IBIAS
Amplifier signal
chain board
10- to 60-V
Supply
Clocking + FPGA + memory
Gain = 5 V/V
50
50
VREF2
VREF2
-
ADC34J45
50
50
Controller + ADC3K
board
5K
to 20 K
+
Trigger and
data capture
+
Optical pulse trigger
ISIG
VREF1
OPA857
THS4541
Figure 1. Block Diagram of System for Evaluation
The TSW1456 digital-capture board generates triggers to pulse the laser diode while simultaneously
sending a signal to the ADC to convert data. The firmware allows multiple triggers with a programmable
repetition rate. The firmware can also control the time-delay between the trigger that fires the laser and the
trigger to the ADC that converts data. The ADC results are buffered into memory and the average result is
computed on the PC. In test and measurement systems such as optical time-domain reflectometry
(OTDR), this averaging feature can lower the noise floor of the entire system, which improves SNR. The
system block diagram in Figure 1 is a loop-back system to enable evaluation of the electrical signal chain
in a controlled environment.
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3
System Description
2.1
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OPA857 Transimpedance Amplifier
The OPA857 is a high-bandwidth, programmable gain, integrated-transimpedance amplifier (TIA).
Standard operational amplifiers have a gain-bandwidth relationship, where bandwidth decreases as gain is
increased. In the case of the OPA857, switching the transimpedance gain also changes the internal
compensation of the amplifier. The closed-loop bandwidth does not follow convention and optimizes the
bandwidth of amplifiers.
The OPA857 also has a pseudo-differential output that makes it easier to interface to the subsequent FDA
stage. The pseudo-differential output also reduces the common-mode noise of the TIA stage. The
OPA857 close to the photodiode on the amplifier signal-chain board minimizes parasitic capacitance. The
board is powered off a 5-V DC supply, which is plugged into the AC mains. A TPS79901 adjustable-linear
regulator converts the 5-V input into a 3.3-V output that drives the OPA857. The output common-mode of
the OPA857 is VCC × 5/9 = 1.83 V. The photodiode is biased and only sources an output current, which is
important because the OPA857 output is optimized to swing less than its common-mode voltage. For
more information, see Figure 2.
6.7k
20k
3.3 V
IN
25
+
25
OUTP
OUTN
VCM = (5/9)* VCC
Figure 2. OPA857 Transimpedance Amplifier
2.2
THS4541 Differential-Amplifier Stage
The THS4541 is a high-bandwidth, low-noise FDA used to provide additional gain to the output of the TIA
stage. The THS4541 also converts the pseudo-differential output of the OPA857 into a fully differential
signal to drive the next ADC stage. The THS4541 level-shifts the output common-mode of the OPA857 to
match the specified input common-mode of the ADC. An onboard resistor divider connected between the
FDA power supply and GND sets the output common-mode of the THS4541. The FDA stage is powered
by 3.3 V from its TPS79901 linear regulator. The THS4541 is configured in a gain of 5 V/V, which results
in an estimated closed-loop bandwidth of 170 MHz.
Increasing the closed-loop gain increases the phase margin of the amplifier and reduces the overshoot to
a pulsed input. A smooth-settling transient response reduces blind-spots and other test artifacts in
applications like OTDR systems. Increasing the RG value improves the response of the OPA857 because
the bandwidth of the OPA857 decreases as the output loading is reduced. The gain resistor (RG) forms the
output load of the OPA857. A large value of RF drives up the value of RG, which reduces the output load
on the OPA857.
4
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A large RF may reduce the phase-margin of the amplifier. The feedback resistance with the input
capacitance of the amplifier creates a zero in the noise-gain response of the amplifier. This zero can
reduce the phase-margin. Add an appropriately sized feedback capacitance (CF) in parallel with RF to
compensate for the zero in the noise-gain response. The combination of RF and CF creates a pole in the
response. The pole in the response helps shape the final closed-loop response of the amplifier.
The FDA and ADC are on separate PCBs connected through SMA connectors. The placement of the FDA
and ADC creates some physical separation between the two devices and a suboptimal layout. To reduce
the effects of reflections, each output of the THS4541 is doubly terminated with 50-Ω resistors. Because
the THS4541 is doubly terminated with 50-Ω resistors, the 6-dB output attenuation reduces the overall
amplifier gain to 2.5 V/V. In a dedicated single-board system, the THS4541 and ADC34J45 can be placed
close to each other to remove the requirement for the output termination.
Another effect to consider is the output swing of the THS4541. In standard CW applications, each output
of the FDA swings symmetrically about its output common-mode with equal magnitude and opposite
phase. In the case of a transimpedance application, the photo-diode can either source or sink current
results in a unipolar output swing from the transimpedance amplifier stage. When the output signal is
applied to the FDA stage, each output swings either higher or lower than its common-mode using only half
the available swing of the amplifier. The ADC also uses only half its available signal swing. For more
information, see Figure 3.
2k
3.3 V
374
From OPA857
TIA stage
+
0.95 V
50
To ADC34J45
Evaluation module
50
374
2k
Figure 3. THS4541 FDA Block Diagram
2.3
ADC34J45 High-Speed ADC
The ADC34J45 is a highly linear, low-power, 14-bit ADC that can sample at up to 160 Msps. To
accommodate many different applications, this family of devices comes in configurations that include dual
or quad channels, 12 bits or 14 bits, and sample rates from 50 to 160 Msps. The JESD204B data interface
allows a simple, flexible SERDES interface to many FPGAs and processors. This device also supports
JESD204B subclasses 0, 1, and 2. The support for these subclasses provides various options for
synchronizing the multiple devices in phased-array applications.
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5
System Description
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With an input range of 2 Vpp, SNR of 72 dBFS, and SFDR greater than 86 dBc, TI designed the
ADC34J45 family for demanding high-frequency signals with a large dynamic range. A 3-dB input
bandwidth of 450-MHz enables this device to subsample systems with frequencies up to three times
greater than the maximum sample rate. In this application, a 14-bit ADC channel digitizes a repetitive,
synchronous optical pulse. For more information, see Figure 4 and Figure 5.
INAP,
INAM
12-Bit
ADC
Digital
Encoder and
JESD204B
INBP,
INBM
12-Bit
ADC
Digital
Encoder and
JESD204B
CLKP,
CLKM
Divide
by 1,2,4
OVRA
DBP,
DBM
OVRB
PLL
SYNCP,
SYNCM
SYSREFP,
SYSREFM
INCP,
INCM
12-Bit
ADC
Digital
Encoder and
JESD204B
INDP,
INDM
12-Bit
ADC
Digital
Encoder and
JESD204B
DCP,
DCM
OVRC
DDP,
DDM
OVRD
SDOUT
SDATA
SCLK
SEN
Configuration Registers
RESET
Common
Mode
PDN
VCM
DAP,
DAM
Figure 4. ADC34Jxx Functional Block Diagram
6
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System Description
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Figure 5. ADC34J45EVM Top View
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7
System Description
2.4
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TSW14J56 Digital-Capture Board
The TSW14J56 is an FPGA-based digital-capture card for ADCs that uses the JESD204B digital interface.
The TSW14J56 provides up to 10 lanes running at 12.5 Gbps to support the fastest converters that use a
JESD204B interface. The board has 2 Gsamples of memory in which to store samples from the ADC. The
USB3.0 interface on this capture platform enables fast data transfers from the sample memory.
HSDC Pro software controls the TSW14J56. This software lets you capture data from the ADC and
process it in the time domain or frequency domain using a fast Fourier transform (FFT). The TSW14J56
captures more than 10,000 triggered ADC34Jxx conversions. These successive conversions are then
extracted for averaging and further analysis. See Figure 6 and Figure 7 for more information.
Figure 6. TSW14J56 Digital Capture Card
8
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System Description
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Figure 7. HSDC Pro Software GUI
2.5
2.5.1
Optical Components
Laser Driver and Laser Diode
The laser-diode driver and laser diode are on a separate PCB with a 5-V supply. The laser driver is an iCHB, 155-MHz triple-laser switch from iC-Haus. See Laser-Diode Driver, iC-HB datasheet for the data
sheet for the laser driver. The laser diode is a 1550-nm DFB LDM5S515-015. In a pulsed high-speed
application, toggling a laser on and off causes suboptimal performance. Rather than turning the laser off,
configure the laser just less than its turnon threshold when it is inactive to ensure a smoother and quicker
turnon. This configuration minimizes the effects of parasitic capacitances that require charging and
discharging during transient operation.
Figure 6 shows a simplified schematic of the laser setup. See Figure 15 for the complete PCB schematic.
Consider each channel of the laser-diode driver a voltage-controlled current source (VCCS) with an
enable and disable switch. The three parallel channels are as follows:
• The bias channel sets the laser at its threshold condition.
• Channel 1 drives the signal current that toggles the laser on or off.
• Channel 2 is unused in this application.
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System Description
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Using the onboard resistor divider and potentiometer subcircuit connected between the 5-V supply and
ground, set the bias voltage to control the VCCS. Set the bias supply to 1.15 V and the signal supply on
channel 1 to 1.65 V. Use the jumper to statically control the bias channel state, while the trigger generated
by the TSW14J56 controls the signal channel. The adjustable linear regulator (U3) is configured to drive
an output voltage of 1.8 V on the VDIG line. This voltage drives the primary side of the SN74LVC1T45
logic-level translator to shift the 0- to 1.8-V logic level from the trigger signal of the TSW14J56 to a 0- to 5V digital signal required to drive the iC-HB chip. For more information, see Figure 8.
Trigger from
TSW14J56
VDD
EN1
3.01 k
CI1
1.50 k
Signal
drive
VDD
ENB
3.74 k
CIB
806
Bias drive
Figure 8. Laser Diode Block Diagram
2.5.2
Photodiode
TI used a low-voltage InGaAs photodiode (NR-7500) and high-voltage avalanche photodiode (NR8300) to
evaluate the system. TI used an LT3995-integrated APD supply to bias the photodiodes. The LT3995 can
supply a bias voltage from 10 to 60 V. This range covers the operating range of both photodiodes during
evaluation.
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Simulations
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3
Simulations
3.1
Noise Simulation
Figure 9 shows the schematic that simplifies the noise of the amplifier signal chain. A current source in the
circuit represents the photodiode.
Figure 9. TINA Schematic For Noise Simulation
Figure 10 shows the output noise of the amplifier system measured at the Vd_Out node. The total
simulated output noise for the 5-kΩ and 20-kΩ transimpedance-gain setting is 303 µVRMS and 888 µVRMS,
respectively, assuming a 135-MHz brick-wall filter. The 900-fF capacitance is an estimate of the sum of
the diode capacitance, PCB parasitic capacitance, and diode package parasitic capacitance.
Output Noise (nV / —Hz)
100
10
5-k: TIA Gain
20-k: TIA Gain
1
100k
1M
10M
Frequency (Hz)
100M
D001
Figure 10. Simulated Output Noise of the Amplifier Chain
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Simulations
3.2
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THS4541 Loop-Gain and Phase Margin Simulation
To get a pulse-response with minimal overshoot and ringing on the rising and falling edges of the pulse,
the phase-margin of the FDA circuit must be greater than 70°. To simulate the loop-gain of the THS4541,
use the circuit in Figure 11. The voltage-controlled voltage source (VCVS1) converts the single-ended
source signal into a full-differential output that subsequently drives the inputs of the amplifiers.
To measure loop-gain, break the loop of the amplifier at its summing-junctions. The differential input signal
drives the inputs of the amplifier forward through C1 and C2, and the L1 and L2 inductors isolate the
feedback signal from the amplifiers input pins and the source. This method is similar to the loop-gain
analysis in single-ended operational amplifiers. C3 and C4 show the approximate parasitic capacitance in
the amplifiers feedback path. C_diff models the input common-mode and differential capacitance of the
amplifier because the actual input capacitance of the amplifier has been isolated from the feedback
network due to the inductors.
Figure 11. THS4541 Loop-Gain Analysis TINA Schematic
12
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Simulations
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The simulated loop-gain magnitude and phase plotted in Figure 12 predict a phase-margin of
approximately 79°. Control-loop theory estimates the pulse-overshoot for 79° of phase-margin to less than
0.001%. The simulated closed-loop bandwidth of the FDA circuit is 150 MHz.
45
100
0
80
-45
60
-90
40
-135
20
-180
0
-225
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
Loop Gain Magnitude (dB)
Loop Gain Phase (q)
Loop Gain Phase (q)
Loop Gain Magnitude (dB)
-20
1G
D002
Figure 12. Simulated Loop Gain of THS4541
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13
PCB Schematic and Layout
4
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PCB Schematic and Layout
Figure 13 and Figure 15 show the PCB layout and schematic for the laser-driver board. Section 9.1
contains the bill of materials (BOM). Minimize trace lengths to reduce parasitic trace resistance and
capacitance. Match the trace lengths wherever possible. To create low-impedance paths from the ICs to
their respective power supplies, place bypass capacitors close to the supply pins of the amplifiers, laser
driver, and APD supply.
Bias-control
potentiometer
Signal-enable
jumper
Bias-enable
Trigger in
from
TSW14J56
Signal-control
potentiometer
Figure 13. Laser-Driver Circuit PCB
14
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PCB Schematic and Layout
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Figure 14 and Figure 16 show the PCB layout and schematic for the signal-driver board. The amplifier
signal chain occupies 38.7 mm2 of PCB area. This area includes the two amplifiers and the surrounding
resistors and capacitors. Both the OPA857 and THS4541 are available in a 3-mm × 3-mm VQFN
package. The area consumed by the amplifiers is 18 mm2.
TIA gain control
switch
20% APD
output current
Figure 14. Signal-Chain Circuit PCB
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PCB Schematic and Layout
4.1
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Circuit Schematic
Figure 15 and Figure 16 show the circuit schematics.
VDD
F1
U3
VDD
C2
47µF
1206SFF200F/63-2
3
2
C3
22µF
1
60 ohm
C4
10µF
C5
1µF
C6
0.1µF
IN
3
R11
1.00KW
VDIG
5
OUT
EN
R12
4
FB
4.99KW
C12
1000pF
C13
2.2µF
C14
0.1µF
GND
C7
0.1µF
Q1
CSD18532Q5B
R13
10.0KW
2
RAPC722X
VDIG
TPS79901DDCT
L1
1
2
+5V
5V
1,2,3
4
D1
1
4
7,8
5,6,
+5
LTST-C 150KGKT
Green
3
U2
TPS2400DBVR
GATE
VIN
VDD
C19
0.1µF
R27
VDD
NC
1.00KW
R3
1.00KW
DNI
DNI
3
2
1
NC
GND
VDD
R26
NC23
C9
1µF
VDD
R4
0W
0W
NC22
VDD
NC20
R5
VDD
4.02KW
1
2
3
4
LD Cathode
1
LD_Anode
LD_Cathode
PD_Cathode
PD_Anode
19
GND
AGNDB
5
4
3
2
6
VDD
LDK1
EPB
AGND1
ENB
5
4
3
2
20
CI2
NER
22
21
TTL
23
EN2
LDKB
5
DNI
CIB
R6
DNI
3.74KW
U1
iC-HB
IMON
LDK2
3
J1
1
SYN2
AGND2
2
LD Cathode
4
Monitor Diode
24
25
C22
0.1µF
1
R24
DNI
CIB
18
GND
VR2
2
17
C21
0.1µF
16
15
VDD
JP3
VDD VDD
1
2
3
14
13
C10
1µF
J6
1
DNI
3299Y-1-501LF
GND
R7
SH-JP3_2-3
806W
R10
NC13
CW
R25
DNI
BIAS IN
1
C1
0.1µF
DNI
LD1
EP2
C11
100pF
DNI
DNI
PwrPad
4.02KW
VDD
IMON
J5
R8
5
4
3
2
GND
3
1
5
4
MBRB2515LT4G
CI1
SYNB
VTTL
SYN1
GND
EN1
EP1
1.00KW
12
11
10
8
9
7
VDD
R9
VDIG
R1
49.9W
VDD
3.01KW
NC8
VDD
NC11
VDD
CI1
R22
VDD
VDD VDIG
SH-JP1_2-3
1
R14
J2
SIGNAL EN
1
0W
VCCA
2
GND
3
A
VCCB
R23
C8
1µF
6
DIR
5
B
4
2
3
4
5
R15
SN74LVC1T45DBVR
CW
J4
1
3299Y-1-501LF
DNI
R2
GND
VDIG
VDD
49.9W
C17
0.1µF
DNI
GND
GND
GND
SIGNAL IN
VR1
2
1.50KW
R17
1.00KW
DNI
C20
0.1µF
R16
R18
DNI
0W
U5
DNI
VDD
DNI
1
VCCA
2
GND
3
A
VDIG VDD
VCCB
6
DIR
5
B
4
DNI
SYNC
J3
R19
1.00KW
C18
0.1µF
SN74LVC1T45DBVR
1
R21
DNI
5
4
3
2
U4
VDIG
1
2
3
3
JP1
5
4
3
2
C16
0.1µF
1
C15
0.1µF
GND
GND
GND
R20
0W
Figure 15. TIDA-00725 Laser-Driver Circuit Schematic
16
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Getting Started–System Setup
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Vout
L1
1286AS-H-1R5M
APD Power Supply
DNI
R29
2
4
1
4
GND
B1
R3
R8
200KW
100KW
1
*ILIM
ILIM
5
VIN
GATE
GND
1.0µF
8
VOUT
C18
0.22µF
R14
TPS63050YFF
DNI
487KW
10% APD
R9
2
0W
LOS_MON
R15
15
FB
15.0KW
U5
LT3905EUD#PBF
3
1
C3
VAMP_5P0
DNI
SS
C4
1000pF
DNI
C16
C7
0.1µF
4
MBRB2515LT4G
C1
10µF
DNI
PG
PFM/PWM
D3
C6
10µF
1.05MW
DNI
ILIM1
C2
+5
LTST-C 150KGKT
Green
VAMP_5P0
C5
22µF
R2
D2
FB
U2
ILIM0
11
B2
B3
1,2,3
7,8
5,6,
D1
VOUT
EN
R1
1.00KW
5V
VIN
A3
C3
10µF
L2
SD3110-100-R
VAMP_5P0
12
C2
47µF
Q1
CSD18532Q5B
Vout
D1
CTRL
1206SFF200F/63-2
3
2
RAPC722X
FLT1
VAMP5.0
NFM41PC204F1H3L
C1
L2
VIN
A2
EN/UVLO
5VIN
7
F1
1
10
+5V
L1
SW
A1
0W
U1
TPS2400DBVR
3
ILIM_MON
ILIM_MON
6
MONIN
5% APD
fSEL
DAP
17
13
9
GND
16
LOS
20.0KW
LOS_ADJ
MON
R11
5
NC
NC
GND
2
49.9KW
3
1
R10
14
MON
20% APD
APD
4
VAMP_5P0
+VAPD
R12
fSEL
0
LOS
VAMP_5P0
3
2 MHz
1
1 MHz
2
R13
C17
0.1µF
100KW
100V
CL-SB-12B-01T
VAMP_5P0
OPA857 Transimpedance Amplifier Stage
1
2
5KW
2
13
15
GND
CTRL
3
GND
12
VCC
11
GND
Vin1_N
R20
2.00KW
4
13
15
OUT-
11
VOCM
9
IN-
3
OPA857
GND
VCC
R22
49.9W
OUT+
142-0801-801
1
10
VOCM
5
4
3
2
5
CL-SB-12B-01T
10
1
U6
1
U7
THS4541IRGT OUT+
FB+
49.9W
C22
0.1µF
DNI
5
4
3
2
PD
IN+
5
4
3
2
10.0KW
PP
12
FB-
VS+
2
1
3
R21
8
Gain Control
V3p3_1
20KW
2
VS+
C11
0.1µF
1
VS+
C10
2.2µF
2.00KW
7
C9
1000pF
R5
R19
VS+
17.4KW
Vin1_P
TESTSD
R4
GND
14
4
17
TESTIN
FB
EN
16
5
VIN
OUT
DNI
3
C8
0.1µF
14
10.0KW
V3p3_1
6
V3p3_1
TPS79901DDCT
IN
OUT142-0801-801
R23
0W
U3
1
V3p3_2
VS-
V3p3_1
VS-
TO5-3pin
VS-
EP
17
PD_Anode
PD_Cathode
NC
GND
R30
VS-
100V
VAMP_5P0
1
2
3
C19
0.01µF
16
PD1 DNI
+VAPD
LDO for Amplifier Supplies
THS4541 FDA Stage
9
OUT+
GND
VCC
GND
GND
OUT-
4
VAMP_5P0
V3p3_1
C20
1000pF
C24
0.1µF
C21
0.1µF
C25
1000pF
V3p3_2
V3p3_2
U4
TPS79901DDCT
1
IN
3
EN
5
FB
4
R6
17.4KW
C13
1000pF
C14
2.2µF
0W
R18
374W
C15
0.1µF
2.00KW
1%
1%
C23
0.1µF
374W
R17
R24
4.99KW
Vin1_N
Vin1_P
1.00KW
1%
DNI
R7
R27
464W
8
7
R25
R16
R26
V3p3_2
V3p3_2
GND
2
C12
0.1µF
OUT
6
5
R28
10.0KW
Figure 16. TIDA-00725 Signal-Chain Circuit Schematic
5
Getting Started–System Setup
To prevent damage to the sensitive optical components and ensure the software is operating in the correct
mode, connect the 5-V supplies to the boards in the following order:
1. TSW14J56 and ADC3k
2. Laser driver
3. Amplifier signal chain
5.1
Laser-Driver Board Setup
1. Ensure jumpers JP1 and JP3 are grounded (JP2 is unused in this application).
2. Use the VR2 potentiometer to set the voltage on CIB (pin 17) to 1.15 V ±25 mV.
NOTE: This adjustment drives approximately 10 mA of current into the LDM5S515-015 laser diode.
This current puts the laser diode at its lasing threshold.
3. Use the VR1 potentiometer to set the voltage on CI1 (pin 12) to 1.65 V ±25 mV.
NOTE: This adjustment drives approximately 40 mA of signal current into the laser diode.
4. Adjust the threshold and signal-bias voltages if using another laser diode.
5. Connect a short cable between J7 (TRIG OUT A) on the TSW controller board and J2 (SIGNAL EN)
on the laser-driver board to trigger the lazer diode.
6. Use a short cable to minimize the delay between the ADC trigger initiating a conversion and the optical
pulse generated by the laser.
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Getting Started–System Setup
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7. Connect JP3 to VDD to set the laser at its threshold.
5.2
Signal-Chain Board Setup
Photodiode Protection: The APD power supply self-limits its output voltage if the voltage on the ILIM_MON
pin exceeds 1.248 V. For this design, the maximum current through the photodiode is limited to 500 µA by
tying a 100-kΩ resistor from ILIM_MON to GND. See the LT3905 data sheet
(http://cds.linear.com/docs/en/datasheet/3905fa.pdf) for more details on this function.
1. Measure the output voltage on the IMON pin using a multi-meter to monitor the amount of input current
into the OPA857 transimpedance stage.
NOTE: The IMON pin sources a current proportional to 20% of the photo-diode current for external
current monitoring. Tie a 20-kΩ resistor from IMON to GND to set the gain of the circuit. Use
Equation 1 to calculate the photodiode current.
VIMON
20kW
(1)
2. Use the fSEL switch to select the frequency of the internal clock of the APD power supply (TI
performed this evaluation with f = 1 MHz; system performance was independent of the selected
frequency).
3. Use the GAIN switch to set the transimpedance gain to 5 kΩ or 20 kΩ.
4. Connect the OUT– and OUT+ SMA connectors on the signal-chain board to the SMA connectors on
the appropriate ADC3k channel.
IAPD = 5 ´
NOTE: TI designed the connector spacing to be equal on the two boards to eliminate the need for
cables thereby minimizing parasitics.
5.3
TSW14J56 + ADC3K Board and Software Setup
The ADC3k EVM accepts a single-ended signal that is converted to a differential signal using the onboard
transformers. See Table 1 for a list of BOM changes required to modify the EVM to accept the differential
output from the signal-chain board. The following changes are described for channel 2 of an ADC34J45
EVM.
HSDC Pro software (available at http://www.ti.com/tool/dataconverterpro-sw?keyMatch=hsdc pro
software&tisearch=Search-EN-Everything) controls the system. The firmware to perform averaging and
hardware-generated triggering is proprietary and unavailable for general use. For additional firmware
information, contact the applications team at http://e2e.ti.com/support/amplifiers/high_speed_amplifiers/.
Table 1. BOM Modifications Required on ADC34J45 and Channel 2 to Accept Differential Input
Signals
18
Reference Designator
Default State
Modified State
J4
DNI
Install
R21
DNI
Install 0-Ω resistor
R24
0Ω
DNI
T3, T4
ADT1-1WT installed
Replace the transformers with a 0-Ω shunt
across the terminals.
C11, C19
0.1 µF
Replace the capacitors with a 0-Ω shunt.
R16, R17
49.9 Ω
Replace the resistors with a 0-Ω shunt.
R19, R26
29.9 Ω
Replace the resistors with a 49.9-Ω shunt.
R20, R27
49.9 Ω
DNI
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5.4
Setting Optical Power and Adjusting the Optical Attenuator
1. Keep the optical power output from the laser diode constant during evaluation in compliance with the
settings in Section 5.1.
2. Turn the knob on the variable optical attenuator (VOA) clockwise for maximum attenuation.
NOTE: This adjustment ensures there is minimal optical power incident on the APD.
See Variable Fiber Optical Inline Attenuator for details on the optical attenuator.
3. Connect a multimeter to the IMON test point on the amplifier board.
4. Set jumper JP1 on the laser-diode board to VDD.
NOTE: The laser diode stays on.
5.
6.
7.
8.
9.
6
Perform a DC measurement of the APD output current.
Turn the knob on the VOA counterclockwise to reduce its attenuation.
Observe the voltage reading on the multimeter.
Use Equation 1 to calculate the APD output current.
Remove JP1 to return control of the laser-diode driver to the trigger signal from the TSW digitalcapture card.
Verification and Measured Performance
Figure 17 shows the bench setup to evaluate the performance of the system in the lab.
Figure 17. Laboratory Bench Setup of Optical Loop-Back System
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Verification and Measured Performance
6.1
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Output Noise of Amplifier Stage
TI measured and compared the noise of the amplifier signal chain with the simulated measurements in
Figure 10. TI found the total output noise of the system to be 365 µVRMS and 840 µVRMS for the 5-kΩ
and 20-kΩ transimpedance-gain settings, respectively. These findings correlate to the simulated values.
The calculations assume a 135-MHz brick-wall filter. For more information, see Figure 18.
Output Noise (nV / —Hz)
100
10
5-k: TIA Gain
20-k: TIA Gain
1
100k
1M
10M
Frequency (Hz)
100M
D003
Figure 18. Measured Output Noise of Amplifier Signal Chain
20
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6.2
System Output Noise
The total output noise of the system and its components was measured using the ADC34J45. Table 2
shows the results. The signal-chain noise correlates with the spectrum analyzer measurements. Because
the photodiode is a significant contributor to the total noise of the system, TI also measured with an
unilluminated photodiode.
Table 2. Output Noise of the System and Components
System Setup
Output Noise (µVRMS)
ADC34J45
260
OPA857 (G = 5 kΩ) + THS4541 + ADC34J45
460
OPA857 (G = 20 kΩ) + THS4541 + ADC34J45
1050
NR7500 + OPA857 (G = 5 kΩ) + THS4541 + ADC34J45
525
NR7500 + OPA857 (G = 20 kΩ) + THS4541 + ADC34J45
1300
TI measured the output noise of the system including the photodiode after averaging. Table 3 shows the
results.
Table 3. System Noise vs Number of Averages
Number of Averages
Noise: 5-kΩ Gain (µVRMS)
Noise: 20-kΩ Gain (µVRMS)
10
165
405
100
51
127
1000
16.7
41
10000
6
14
100000
4
7.9
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Verification and Measured Performance
6.3
6.3.1
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Pulse Response Measurements
Pulse Response vs Output Voltage
TI measured the output pulse response as a function of the output voltage swing for both transimpedancegain settings. Figure 19 plots the response with the output voltage plotted on a log-scale to accentuate the
settling performance. Figure 20 compares the settling responses for the different output voltages on a
linear scale. The curves have been offset from each other by 50 µV to make comparisons easy.
1
125 mV
250 mV
500 mV
950 mV
Output Voltage (V)
100m
10m
1m
100P
10P
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
Time (Ps)
2.5
2.75
3
3.25
3.5
3.75
4
D004
Figure 19. Pulse Response vs Output Voltage, 20-kΩ Transimpedance Gain
400P
125 mV
250 mV
500 mV
1V
350P
Output Voltage (V)
300P
250P
200P
150P
100P
50P
0
-50P
0
1
2
3
4
5
Time (Ps)
6
7
8
9
10
D005
Figure 20. Long-Term Settling Response vs Output Voltage, 20-kΩ Transimpedance Gain
Figure 21 and Figure 22 show the response for the 5-kΩ transimpedance-gain setting.
22
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1
125 mV
250 mV
500 mV
950 mV
Output Voltage (V)
100m
10m
1m
100P
10P
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
Time (Ps)
2.5
2.75
3
3.25
3.5
3.75
4
D006
Figure 21. Pulse Response vs Output Voltage, 5-kΩ Transimpedance Gain
400P
125 mV
250 mV
500 mV
1V
350P
Output Voltage (V)
300P
250P
200P
150P
100P
50P
0P
-50P
0
1
2
3
4
5
Time (Ps)
6
7
8
9
10
D007
Figure 22. Long-Term Settling Response vs Output Voltage, 5-kΩ Transimpedance Gain
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6.3.2
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Pulse Response vs Output Pulse Width
1
1
100m
100m
Output Voltage (V)
Output Voltage (V)
Figures 23 through 28 show the pulse response as a function of the pulse width for the two
transimpedance-gain settings. TI adjusted the optical attenuator to drive an output voltage of 0.5 V.
10m
1m
100P
10m
1m
100P
10P
10P
0
0.2
0.4
0.6
Time (Ps)
0.8
1
0
0.2
1
1
100m
100m
10m
1m
100P
1
D009
10m
1m
100P
10P
10P
0
0.5
1
1.5
2
2.5
Time (Ps)
3
3.5
4
0
0.5
1
1.5
D010
Figure 25. 250-ns Pulse Width, 20-kΩ Gain
1
1
100m
100m
10m
1m
100P
2
2.5
Time (Ps)
3
3.5
4
D011
Figure 26. 250-ns Pulse Width, 5-kΩ Gain
Output Voltage (V)
Output Voltage (V)
0.8
Figure 24. 25-ns Pulse Width, 5-kΩ Gain
Output Voltage (V)
Output Voltage (V)
Figure 23. 25-ns Pulse Width, 20-kΩ Gain
10m
1m
100P
10P
10P
0
1
2
3
4
5
6
Time (Ps)
7
8
9
10
0
1
D012
Figure 27. 2.5-µs Pulse Width, 20-kΩ Gain
24
0.4
0.6
Time (Ps)
D008
2
3
4
5
6
Time (Ps)
7
8
9
10
D013
Figure 28. 2.5-µs Pulse Width, 5-kΩ Gain
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6.3.3
Overloaded Pulse Response
TI also evaluated the system response for an overdriven output signal from the TIA in both gain
configurations. TI adjusted the optical attenuator to vary the output current from the photodiode with the
bias settings to the laser driver unchanged from the previous measurements and to set the pulse width to
250 ns for the tests. See Figure 29 and Figure 30 for more information.
1
I IN = 50 PA, 1x Overload
I IN = 100 PA, 2x Overload
I IN = 200 PA, 4x Overload
Output Voltage (V)
100m
10m
1m
100P
10P
0
4
8
12
16
20
Time (Ps)
24
28
32
36
40
D014
Figure 29. TIA Gain = 20 kΩ, Overloaded Response
1
I IN = 200 PA, 1x Overload
I IN = 400 PA, 2x Overload
Output Voltage (V)
100m
10m
1m
100P
10P
0
4
8
12
16
20
Time (Ps)
24
28
32
36
40
D015
Figure 30. TIA Gain = 5 kΩ, Overloaded Response
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Verification and Measured Performance
6.3.4
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Pulse Response vs Output Termination
The output of the THS4541 was doubly terminated at the ADC inputs through a 50-Ω resistor. This
configuration creates a 6-dB loss in signal output resulting in an effective FDA gain of 2.5 V/V. TI
configured the circuit to prevent signal reflections because of the distance between the THS4541 output,
and the input of the ADC. When the THS4541 and ADC3K share the same PCB, you can eliminate this
termination. TI also measured the pulse response of the circuit without the 50-Ω termination at the ADC
input and compared the results with the earlier measurements. TI set the pulse width to 250 ns and
configured the OPA857 in a gain of 20 kΩ. Figure 31 shows that the unterminated output does not affect
the settling performance of the system.
1
V OUT = 500 mV, No Termination
V OUT = 250 mV, 50 : Termination
V OUT = 500 mV, 50 : Termination
Output Voltage (V)
100m
10m
1m
100P
10P
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
Time (µs)
2.5
2.75
3
3.25
3.5
3.75
4
D016
Figure 31. Effect of Output Termination on Settling Performance
26
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6.4
OTDR System Test
Using the principle of Rayleigh scattering, TI used optical time-domain reflectometry (OTDR) to test and
characterize optical cables. In a true OTDR system, light from the transmitter (usually a high-power laser)
is injected into the optical fiber under test. The backscattered light from the test fiber is collected using a
photo detector that converts the optical signal into a current output, which is processed using a low-noise,
high-speed signal chain. See Optical Time-Domain Reflectometer Wiki and Guide to Fiber Optics and
Premises Cabling for more information on OTDR.
Figure 32 shows a block diagram of a test OTDR system. A 3-port, fiber-optic circulator (for example, see
http://www.thorlabs.com/thorproduct.cfm?partnumber=6015-3-FC) is required for the measurement.
1. Couple the output from the laser into port 1 of the circulator.
2. Connect the optical fiber being tested to port 2.
3. Connect port 3 to the photodiode.
4. Allow light from port 1 to enter port 2 with minimal insertion loss while the light from port 1 to port
undergoes large attenuation.
5. Allow the back-scattered light from port 2 to enter port 3 with minimal insertion loss but is greatly
attenuated at port-1.
6. Attenuate light entering port 3 at port 1 and port 2.
For the tests in this section, the transimpedance gain was 20 kΩ. Based on the results in Section 6.3.4, TI
did not terminate the THS4541 with a 50-Ω resistor at the input of the ADC3K. This overall system gain
was 20 kΩ × 5 V/V = 100 kΩ.
1 km Optical Fiber
Fiber
Connector
iC-HB 155-MHz Laser
Driver Board
Circulator
ISIG
Optical Pulse Trigger
1 km Optical Fiber
IBIAS
Amplifier Signal Chain
Board
10- to 60-V
Supply
Clocking + FPGA + memory
Gain = 5 V/V
20 kŸ
Trigger &
Data Capture
VREF2
VREF2
VREF1
-
1 NŸ
+
ADC34J45
50 Ÿ
Controller + ADC3K
Board
+
50 Ÿ
1 NŸ
OPA857
THS4541
Figure 32. OTDR Block Diagram
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Verification and Measured Performance
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TI conducted several OTDR tests by varying the optical pulse-width with the results in figure 33.
Increasing the pulse-width increases the amount of backscattered light incident on the photodiode. There
are three distinct regions in the output response.
• At t = 0.3 µsec, a discontinuity occurs in the backscatter due to Fresnel reflections occurring at the
opto-coupler between the laser diode and the first section of 1-km fiber. Based on the speed of light in
fiber (200,000 km/sec), the light takes 10 µsec to travel 1 km and return to the source.
• At t = 10.3 µsec, a second discontinuity occurs in the backscatter due to Fresnel reflections occurring
at the opto-coupler between the two 1-km fibers.
• At t = 20.3 µsec, a large reflection occurs when the light encounters the unterminated end of the
second fiber.
1
2.5 Ps Pulse
1.0 Ps Pulse
250 ns Pulse
Output Voltage (V)
100m
10m
1m
100P
10P
0
2.5
5
7.5
10
12.5
Time (Ps)
15
17.5
20
22.5
25
D017
Figure 33. OTDR System Test vs Optical Pulse Width
28
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With the pulse-width set at 2.5 µsec, TI retested the OTDR system. TI bent the second fiber at the
coupling between the two fibers. The increased optical attenuation at the fiber bend exists in the droop in
backscattered power at 10 µsec and in the reduced reflected power at the unterminated fiber end. See
Figure 34 for more information.
1
Output Voltage (V)
100m
10m
1m
100P
10P
0
2.5
5
7.5
10
12.5
Time (Ps)
15
17.5
20
22.5
25
D018
Figure 34. OTDR Response With Bend in Optical Fiber
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System Enhancements
7
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System Enhancements
In this section, TI proposes two different methods of improving the system SNR performance.
7.1
THS4541 Level-Shift Circuit
Depending on the direction of reverse-bias, a photodiode can either source or sink current. The output of
the OPA857 swings in a negative direction from its common-mode reference voltage. When this signal is
applied to the THS4541, each of its differential outputs swings either higher or lower than its output
common-mode (VOCM). Due to this unipolar swing limitation, only half the input range of the ADC is used,
which reduces the dynamic range of the system by 6 dB. To overcome this limitation, configure the FDA
as shown in Figure 35.
2 NŸ
VID
3.3 V
374 Ÿ
25 Ÿ
OPA857
RD
VCM = 1.83 V
25 Ÿ
0.95 V
374 Ÿ
V,'¶
+
VOUT1
-
VOUT2
R'¶
2 NŸ
Figure 35. THS4541 Level-Shift Circuit
The ADC3K has a specified maximum differential-input swing of 2 VPP on a 0.95-V common-mode input.
This implies that each differential input to the ADC input can swing from 0.45 V to 1.45 V. To level-shift
the output of the THS4541 to take advantage of the full dynamic range of the ADC, apply a differential DC
input signal (VI_DIFF = VID – VID’) to produce a 1-VPP differential output.
Calculate the input common-mode of the THS4541 from the OPA857 output as follows:
1.83 - VICM
V - 0.95
= ICM
400 W
2 kW
Þ VICM = 1.68 V
Calculate the gain of the level-shift circuit as follows:
VO _ DIFF
R
=- F
VI _ DIFF
RD
30
Optical Front-End System Reference Design
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(2)
(3)
(4)
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To reduce the noise-gain contribution from the level-shift circuit, keep its gain to a minimum. If a level-shift
circuit gain of 0 dB is assumed, set RD = RD’ = 2 kΩ, VID = (1.68 V + 0.5 V), and VID’ = (1.68 V – 0.5 V).
Figure 36 shows the simulated output for a 100-mV differential input to the THS4541 circuit. From
simulations, the increased noise due to the level-shift circuit is less than 6%.
2
1.8
1.6
Voltage (V)
1.4
VINPUT
VOUT2
VOUT1
1.2
1
0.8
0.6
0.4
0
25
50
75
100
125
150
175
Time (ns)
200
225
250
275
300
D019
Figure 36. Simulated Output Pulse of Level-Shift Circuit
7.2
Anti-Aliasing Filter
To reduce the total system noise, place a third-order, passive Bessel filter between the THS4541 and
ADC3K. Figure 37 shows one such implementation of the filter.
3rd Order, 80-MHz
Bessel Filter
3.3 V
+
VOCM
40 Ÿ
300 nH
43 pF
-
40 Ÿ
5.2 pF 200 Ÿ
300 nH
To ADC
Inputs
Figure 37. Anti-Alias Filter
The simulated system noise was reduced by 50% when using this anti-alias filter. The final shunt capacitor
filter (5.2 pF) must be tuned based on the differential input capacitance of the ADC. The filter introduces a
3-dB insertion loss to the overall system gain.
8
Conclusion
This reference design describes a complete end-to-end optical front-end system and its performance.
Various techniques to optimize the SNR performance of the signal chain are also discussed. This
reference design provides a flexible platform, letting you change critical system components such as the
amplifier chain, ADC, and the optical components.
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Design Files
9
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Design Files
To download the design files, see the files at TIDA-00725.
9.1
Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-00725.
10
References
1. Optical Time-Domain Reflectometer Wiki, https://en.wikipedia.org/wiki/Optical_timedomain_reflectometer
2. Guide to Fiber Optics and Premises Cabling, http://www.thefoa.org/tech/ref/testing/OTDR/OTDR.html
3. Laser-Diode Driver, iC-HB data sheet (https://www.ichaus.de/upload/pdf/HB_datasheet_A4en.pdf)
4. Laser Diode, LDM5S515 data sheet (https://www.oequest.com/getDatasheet/id/21653255cfdc2f98b43.pdf)
5. Variable Fiber Optical Inline Attenuator, http://www.fiberstore.com/fc-apc-to-fc-apc-variable-fiber-opticvoa-in-line-attenuator-0-60db-p-13556.html
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Optical Front-End System Reference Design
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About the Author
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About the Author
SAMIR CHERIAN is an applications engineer with TI in the high-speed amplifier division in Tucson, AZ.
He validates the performance and specifications of high-speed amplifiers and provides customer support
through TI online forums, application notes, and reference designs.
KEN CHAN is an applications engineer with TI in the high-speed data converter product line based in
Dallas, TX. He supports data converter devices, systems, and solution in high-speed signal chains
covering communications and industrial applications.
TIDUAZ1 – November 2015
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Optical Front-End System Reference Design
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