A new modular voltage source inverter topology
A. Lesnicar, R. Marquardt
INSTITUTE OF POWER ELECTRONICS AND CONTROL
Universität der Bundeswehr München
Werner-Heisenberg-Weg 39
85577 München, Germany
Phone: +49-(0)89-60043938 / Fax+49-(0)89-60043944
e-mail: anton.lesnicar@unibw-muenchen.de
http://et6-server.et.unibw-muenchen.de
Keywords
Multilevel converter, Transmission of electrical energy, HVDC, Power conditioning, Emerging
topologies
Abstract
This paper introduces a new modular multilevel converter (M2LC) topology suitable for very high
voltage applications, especially network interties in power transmission. The fundamental concept, the
applied control scheme and simulation results of a 36MW–network intertie are presented. With
reference to the expenditure of components, a comparison between the new modular multilevel
converter and a conventional converter topology is given. A suitable structure of the converter control
is proposed.
1
Introduction
The deregulation of international energy markets and the trend to decentralized power generation are
increasing the demand for advanced power electronic systems. For this application field, multilevel
converters with a high number of voltage levels are the most suitable types, because of the need for
multiple series connection of semiconductors and low voltage distortion on the line side [1-3]. Besides
these points, a lot of other important aspects have to be taken into account for these applications. Main
technical and economical aspects for the development of multilevel converters are:
Modular realization:
- scalable to different power- and voltage levels
- insensitive to variable semiconductor parameters
Multilevel waveform:
- expandable to any number of voltage steps
- low total harmonic distortion
- dynamic voltage sharing of the power devices
High availability:
- use of approved semiconductor devices
- redundant operation
Failure management:
- fail safe operation on device failures
- avoidance of mechanical destruction (high magnetic forces caused
by surge currents)
Investment and life cycle cost: - modular construction
- standard components
2
2.1
Concept of the new Modular MultiLevel Converter M2LC
Principle of M2LC
In order to fulfil the above mentioned requirements, a converter system solely composed of an
arbitrary number of identical “submodules” was a prerequisite. For the sake of stringent modular and
scalable realization, additional “central” components have to be avoided. The DC-link capacitor of
conventional voltage source inverters presents an example of such a component – independent of its
realization out of a number of series connected capacitors or not. The same applies to the associated
high voltage, low inductance DC-bus bars.
The new concept consists of submodules which are two terminal devices composed of switches and a
local DC-storage capacitor C0 (Fig. 1, 2). No additional external connection or energy transmission to
the submodules is needed, for full 4-quadrant operation of the converter system. The interface is
composed solely of two electrical terminals and one bi-directional fibre-optic cable. By this means, the
voltage of each submodule is transmitted and can be freely controlled by software. The individual
voltages of the submodules may even be chosen unequal. This can be used to increase the number of
resulting voltage steps (e.g. together with PWM-operation).
Unlike the conventional VSI, a common central capacitive storage is abundant. This advantage eases
the protection of the converter against mechanical destruction in case of a short circuit or insulation
failures, significantly. In addition, a defective submodule can be replaced by a redundant submodule in
the arm without the need for mechanical switches. This results in an increased safety and availability.
Fig. 1 illustrates an inverter leg consisting of n submodules in each arm. In a first step, the submodules
can be considered as controlled voltage sources. In this given structure, it can be shown that the
submodules must be able to carry a DC-component ( ia ≠ 0 ) of the current ia, but do not have to supply
real power in steady state operation. Concerning control, a realization with 2-level voltage sources
leads to the simplest realization (Fig. 2). A realization with 3-level voltage sources leads to a
generalized concept for “matrix type” converters [8]. Regardless of the sign of the current ia,i, the
terminal voltage Vx,i of each submodule can be impressed.
By switching a number of the n submodules in the upper and lower arm, the voltage VN is adjusted. In
a similar manner, the voltage Vd can be adjusted, independently.
P
i a .1
SM
Vd
SM
i a .2
SM
SM
V x 1 .1
Vd
2
V x 1 .n
iN
V x 2 .1
N
VN
Only the sum of the voltages Vd(t) and VN(t) is
restricted depending on the number n of
submodules per arm:
Vd ( t ) + 2 ⋅ VN ( t ) ≤ 2 ⋅ n ⋅ VC (1)
When - for example -
Vd = n ⋅ VC
Vd
2
V x 2 .n
N
Fig. 1: Inverter leg consisting of 2n submodules
is chosen, the amplitude of the output voltage
will be restricted to:
V̂N ≤ n ⋅ VC
(2)
P
q·Id
iT1
iC
iC
iT1
T1
+
VC
Vd
iFD1
D1
T1
+
iN
- Cd
D1
ia
- C
0
D2
T2
iT2
VX
iFD2
Fig. 2: Structure of a submodule (SM)
(Two terminal device)
D2
T2
iT2
N
2.2
iFD1
iFD2
Fig. 3: Structure of a conventional leg
(Three terminal device)
Concept of controlled voltage balancing
In order to keep the capacitors on the same voltage level and to ensure equal stress for the power
devices the following algorithm is applied for each arm:
The voltages of the capacitors are periodically measured with a typical sampling-rate in the
millisecond-range. According to their voltage, the capacitors are sorted by software. In case of positive
current in the arm the required number of submodules, determined by output state controller, with the
lowest voltages are switched on. When the current in the corresponding arm is negative, the demanded
number of submodules with the highest voltages are selected. Instead of measuring the current in the
arm, the information about the sign may be derived from the voltage difference of two subsequent
voltage samples. By this method, continuous balancing of the capacitor voltages is achieved.
Inherently, this concept supports an optimized utilisation of the stored energy and evenly distributed
power losses for the installed electrical devices. Additionally, the power losses can be kept low by
switching the submodules solely, when a change of the output state is requested.
3
Control scheme
With regard to the modular and scalable topology of the M2LC, the applied control scheme should be
easily expandable to any number of levels. With this in mind, the space-vector PWM is a suitable
control scheme. In general, all concepts based on the space-vector PWM theory are compatible with
the following concept:
The first task is the transformation of the three phase voltages into the two-dimensional space by using
the equation (3).
1

−
1

 v Re  2 
2
  = ⋅
3
v
3

 Im 
0 +
2

1  v 
1

2 ⋅v 
 
3  2
−
 v
2   3
−
(3)
The second step is to find the three active switching vectors adjacent to the setpoint vector vref. The
three active switching points next to the setpoint vector have to be located to minimize the harmonics.
Finally, the correspondent dwelling times have to be calculated [3]-[6].
As an example Fig. 4 shows a 5-level space-vector diagram, assuming that the capacitor-voltages of
the submodules are equal and scaled to the value 1. (From this it follows that the normalized terminalvoltages VX of the submodules have either the value 0 or 1.)
2.89
Im
1
2.31
2
1.73
3
1.15
4
0.58
5
0.00
Re
−0.58
−1.15
−1.73
−2.31
−2.89
−3.33 −2.67 −2.00 −1.33 −0.67 −0.00
0.67
2.00
1.33
2.67
3.33
Fig. 4: Space-vector diagram of a 5-level converter with the corresponding
number of possible different DC-link voltages
The M2LC offers the degree of freedom to control the DC-link voltage directly, using the different
switching states. The proposed control scheme adopts the fundamental principles of the
abovementioned general concept of space-vector theory. In addition to the two dimensions, the DCvoltage Vd can be taken into account. This results in a three-dimensional space consisting of
tetrahedrons.
5.0
1.33
4.0
1.00
3.0
0.67
2.0
1.0
0.33
0.0
0.0
-1.0
-0.33
-2.0
-0.67
-3.0
-4.0
-5.0
0
-1.00
3.33m
6.67m
10.00m
time[ms]
13.33m
16.67m
20.00m
Fig. 6: Line-to-line voltages
(5-level topology, normalized to VC)
-1.33
0
3.33m
6.67m
10.00m
time[ms]
13.33m
16.67m
20.00m
Fig. 7: Example of common-mode voltage
(corresponding to Fig. 6)
For synthesizing the setpoint vector by using the most convenient switching states, a suitable
algorithm shall be roughly described: In the same way, like in the planar representation, the phase
voltages have to be transformed. The third dimension is given by the DC-voltage axis. The next
surrounding switching-state vectors to the setpoint vector have to be located. Compared to the planar
graph now 4 points have to be determined, which encase the setpoint vector by a tetrahedron.
Analogue to the conventional duty cycle computation the four dwelling times of the correspondent
switching-state vector can be calculated.
Simulation results of the three-phase voltages using the proposed space-vector PWM are shown in
Fig. 6.
4
Simulation results
A network intertie model has been built and tested to verify the concept. For this task, the program
SIMPLORER was used. A prototype of a 2 MW converter system is under construction. In the model,
5 inverter legs are connected to a common DC-link (one three-phase inverter and one single phase
inverter). Each arm is composed of 22 identical submodules (Fig. 8). No additional, central, capacitive
energy storage at the DC-link is installed.
ia.11
ia.13
ia.12
SM
SM
ia.14
P
N0
SM
SM
ia.15
SM
U[kV]
n=22
SM
SM
V 12
SM
SM
SM
40.0
V 23
30.0
V 45
controlled Vd
20.0
d
VV
d
V 31
Vd
50.0
V45
10.0
0
- 10.0
SM
SM
SM
SM
SM
- 20.0
- 30.0
SM
SM
SM
SM
SM
- 40.0
NN
0
0
Fig. 8: Model of network intertie
P[MW ]
80.0
70.0
10.0
20.0
30.0
50.0
40.0
time[ms]
80.0
I[kA]
U[kV]
3.5
60.0
50.0
40.0
30.0
20.0
10.0
7.0
VC.1 - VC.22
3.0
6.0
2.5
5.0
2.0
4.0
VC
1.5
0
-10.0
1.0
P in
-30.0
70.0
Fig. 9a: Output voltage and DC-link voltage
P out
-20.0
60.0
3.0
2.0
ia.14
1.0
0.5
-40.0
0
0
-50.0
0
10.0
20.0
30.0
40.0
time [ms]
50.0
60.0
70.0
Fig. 9b: Input and output power versus time
80.0
-0.5
-1.0
0
10.0
20.0
30.0
40.0
time [ms]
50.0
60.0
70.0
80.0
Fig. 9c: Current and submodule voltages in an arm
Parameters: Transmitted real power Pd = 36 MW; C0 = 2.0 mF;
single-phase-system: V1,rms =25.0 kV, f1 = 25 Hz; three-phase-system: V3,rms =23.0 kV, f3 =
60 Hz)
The curves shown in Fig. 9a, 9b and 9c are under steady state conditions. The single phase and the
three phase voltages are synthesized by 21 levels (+1 redundant submodule). As mentioned above, the
DC-voltage Vd has been controlled by appropriate control of the switching states, too. Fig. 9a shows
the controlled DC-link voltage. By this means, the expected, severe voltage pulsation caused by the
single phase supply could be remarkably suppressed. The remaining low ripple content of the 2nd
harmonic on the DC-link voltage has no effect on the input and output power characteristic (Fig 9b).
Fig. 9c illustrates the good voltage balancing of the submodule voltages in an arm and the associated
current in the arm.
The voltage ripple of the submodules has been chosen high, in order to demonstrate the capabilities of
the system. Another characteristic of the M2LC-converter is the very low di/dt of the (internal) arm
currents. The possible control of the converter, however, has not yet been fully optimized - as may be
seen from the low amplitude oscillations in the arm current.
5
Expenditure of installed components
Because the structure of M2LC is quite different from conventional converters, a comparison with
respect to the expenditure of the installed components is not a simple task. At least, the following
major points should be taken into account:
1.
2.
3.
4.
5.
Sum of the installed, stored energy of the converter (i.e. capacitors)
Sum of the power losses of the silicon devices
Required, total silicon area of the converter
Number of switches, gate drivers and snubbers
Mechanical construction requirements including low inductance bus bars at high voltage and
high surge current
6. Protection hardware
The comparison must be based on an equal power and voltage level. In order to be precise, the
technical requirements of a certain application must be considered. On the other hand, an analytical
investigation can contribute to better basic understanding of the main points. In the following, this
investigation will be given – focused on the important points 1 to 3. With respect to the remaining
points, a brief comment shall be given: Point 4 is a clear disadvantage of the M2LC – concept, because
the number of switches is doubled compared to a conventional converter. The number of switches,
however, is less important than the total required silicon area (point 3) when using modern MOS-gated
and snubberless devices. The points 5 and 6 are clear advantages of the new system, because the
absence of heavy high voltage bus bars and additional protection hardware enables a modular, simple
and robust mechanical construction of the whole converter. The absence of passive filters and the
resulting superior control characteristics are important advantages, too [8].
5.1
Capacitive energy storage requirement
An analytical expression of the required, total stored energy (point 1) can be given under the following
conditions:
a) Sine wave output voltages (VN) and line currents (iN)
b) Smooth DC-link voltage (Vd)
c) Equally divided real power flow of the converter legs
These conditions are not necessary for operation of the converter, but they are fulfilled with good
approximation, in general. Condition b) leads to a very simple expression of the real power flow
Pd = Vd ⋅ I d
(5)
where I d denotes the average current in the DC-link (Fig. 8). Condition c) gives the DC-component
of the converter arm current.
ia = q ⋅ I d
(6)
where q denotes a constant share of I d , depending on the number of converter legs sharing the real
power flow. For the single phase converter section – which shall be discussed here – this value is
q = 0.5 . Defining a normalized current ratio:
m=
iˆN
Id
(7)
of peak line current to DC-current, it becomes possible to express the pulsation of energy ( ∆WSM ) per
submodule, directly:
∆WSM
m ⋅ Pd
=
2 ⋅ n ⋅ωN
1 

1 − 2 
 m 
3
2
(8)
In this equation, ω N denotes the angular frequency of the line current (a more detailed explanation of
these equations is given in [2]).
It shall be noticed, that the current ratio (m) – because of basic laws of physics – is restricted to values
m ≥ 2 , for all possible output voltages (VN) and arbitrary power factor.
The necessary capacitance of each submodule follows from equation (8), when the ripple factor of the
submodule voltage (0 < ε < 0.5) is introduced:
m ⋅ Pd
1 

C0 =
1 − 2 
2
4 ⋅ ε ⋅ (U C ) ⋅ n ⋅ ω N  m 
3
2
(9)
The comparison of stored energy of a conventional converter (with central DC-link capacitors)
depends on the particular application. If there are requirements concerning operation with short line
interruptions or operation on single phase lines, the M2LC compares very well - see [2] and [8] for
examples.
When none of these requirements exist, a conventional 3-phase/3-phase – converter system could be
equipped with negligible DC-link capacitance – depending only on pulse frequency, theoretically. In
these applications the M2LC would not compare well, because it needs a considerably higher
minimum of installed energy for operation. For the present application (Fig. 8 and 9) it turned out, that
the M2LC – converter could operate with about the same amount of capacitive stored energy, than a
conventional voltage source converter of the same power rating – but it is saving the installed
magnetic energy of the additional passive filters.
5.2
Required silicon area and power losses
The required total silicon area of the converter gives a good approximation of the cost, especially
when used only for comparison at the same semiconductor voltage level and the same cooling system.
The required total silicon area can be assumed to be proportional to the total semiconductor power
losses,, if the cooling system is the limiting factor. This assumption is reasonable for high power
converters and will be made here, in order to enable an analytical comparison. In a next step, the load
dependent peak junction temperature and peak current for any semiconductor chip would have to be
considered. This, however, can be done for a special application, only. It will be seen from the
following analysis, that this is not necessary for a basic comparison.
Concerning semiconductor losses, the switching losses shall be discussed first: The conventional leg
with direct series connection (Fig. 3) needs a high switching frequency, in order to assure a reasonable
quality of the line currents spectrum. Multi level waveforms enable better quality at reduced switching
frequencies, which is well known. With respect to this point, the M2LC-converter is similar to a multilevel-diode-clamped converter. In addition, it gives the control freedom, to ensure ideal sharing of the
switching losses of all the submodules in each arm. Owing to these reasons, the following comparison
will focus on the on state losses.
The on state losses of an IGBT (or free wheeling diode) can be expressed in the form (see Fig. 3)
PF = iT ⋅ U F
*
(10)
*
where iT represents the IGBT average current (arithmetic mean value) and U F represents an
“equivalent on state voltage”, which has to be determined form the current wave form of the load
*
current. Even if iT (t ) is completely unknown, it can be proven that U F must be in the range:
*
U F ( iN ) ≤ U F ≤ U F (iˆN )
(11)
Using this approach, a general comparison of on state losses PF becomes possible, when the
semiconductor average current iT , the average of the absolute value of the load current iN and the
peak value of the load current iˆN is known. The arithmetic mean values of the semi-conductor currents
( iT , iFD ) can be expressed in general equations, based on Kirchhoff’s law (see Table 1). When the on
state voltages of IGBT and diodes are similar, a comprehensive result for the on state losses (
∑P
can be given, finally. (16)
Table I: On state power dissipation of the semiconductor devices (for comparison)
submodule (two terminal device)
=>
i T1 = i FD1 =
iT 2 =
1 IN
⋅
4 2
1 IN 1
⋅
+ q ⋅ Id
4 2 2
iFD 2 =
1 IN 1
⋅
− q ⋅ Id
4 2 2
(12.a)
(14.a)
F
=
IN
*
⋅ U F ⋅ 2n
2
1
1
⋅ IN + ⋅ q ⋅ Id
4
2
i FD1 = i FD 2 =
(12.b)
(16.a)
1
1
⋅ I N − ⋅ q ⋅ I d (14.b)
4
2
Maximum peak current in any semiconductor
iˆT ≤ iˆN
(15.a)
Power dissipation with 2n submodules per leg:
∑P
i T1 = i T 2 =
(13)
Maximum peak current in any semiconductor:
1
1
iˆT ≤ ⋅ iˆN + iˆN
2
4
conventional leg (three terminal device)
(15.b)
Power dissipation with 2n switches per leg:
∑P
F
*
= I N ⋅U F ⋅ n
(16.b)
F
)
As may be noticed form Table I, the submodules of the M2LC-converter are carrying half of the ACcurrent (iN) amplitude, only. The peak current (îT) is lower, too (see (10.a) for the worst case m=2).
Owing to these reasons, the resulting total on state losses (
PF ) would be lower than for the
∑
conventional leg. This is not true, however, when the total silicon area of both converters is made
equal. When the silicon area per IGBT (and diode) is reduced in accordance with the reduced average
current ( iT ) in the M2LC, the total on state losses (
PF ) of both converters become very similar.
∑
This result has been proven (with a reasonable accuracy of approximately ±10%) by several detailed
computations for actual applications.
6
Structure of M2LC-control
The following control structure for M2LC is chosen (Fig. 10), consisting of three different fundamental
units.
Supervisory
Computer
Converter
Cubicle
Central Control Unit (CCU)
Submodule
T1,T2
Vc1
duplex opticalfibre cable
Interface
cable
Interface
flat
ribbon
•
•
•
Submodule
T1,T2
Vc1
Arm-Circuit
Current
Measurement
A
Fig. 10: Structure of M2LC – control
The supervisory unit manages the feedback and general control of the entire system. According to the
setpoint values, the feedback control supplies data to the central control unit in real-time mode. A
digital signal processor DSP (or FPGA) is well suited to solve these tasks. The presented concept of
voltage balancing is implemented in the modulator. The output state controller - which has to
determine the optimized output states and the operating sequence for the next PWM-period - is
integrated, too. The PWM-generator calculates the dwelling-times for the appendant switching states.
The converter cubicles are equipped with a number of identical submodules, which are connected to
the central control unit solely by duplex optical-fibre cable. Each submodule receives the
correspondent switching commands, opto-electronically and sends its capacitor-voltage back to the
central control unit, periodically. The power supply voltage for data transfer and the drive circuits of
the IGBTs is supplied from the local capacitor of the submodule [7]. The system for current
measurement is connected fibre-optically, too. This structure leads to clear and safe separation of the
low voltage and the high voltage part of the system.
7
Conclusion
This paper introduced the topology of the new modular multilevel converter M2LC and its relevant
characteristics. The modular concept allows the application for a wide power range. The proposed
control scheme is well suited for a different number of voltage levels. It is shown that the control
scheme allows to control phase-voltages and the DC-voltage at the same time, independently.
Simulations have demonstrated a good performance of the M2LC-concept. The start under deenergized condition can be safely realized. The structure of M2LC-control enables good separation of
the low voltage units and the high voltage units of the converter cubicles. Presently, a prototype of a 2
MW – converter system is being built. This modular system will enable further experimental
investigations.
8
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für