DC/DC converter PCB layout, Part 3
Timothy Hegarty - June 29, 2015
One important innovation in the field of DC/DC power converters is the realization of higher and
higher density designs. In the push for smaller-footprint solutions, designers are now focusing on
usable power density to extract the most power per unit area or volume from the converter circuit.
Since the power converter is a critical and ubiquitous piece of the overall solution, a thoughtful
printed circuit board (PCB) layout represents an opportunity to improve density while providing
additional system-level advantages, too. One example is electromagnetic interference (EMI), which
is an increasingly vexing issue during product design and qualification. A compact, optimized power
stage layout improves EMI in terms of both emissions and immunity.
In this three-part series [1], I discussed PCB layout considerations for fast-switching DC/DC
converters using a step-by-step approach. Steps 1 and 2 from part 1 examined the PCB layer stackup
and identified the high-di/dt current loops and high-dv/dt voltage nodes of the converter. Steps 3 and
4 in part 2 offered a review of power stage and control IC component placement for optimal
switching as well as thermal and EMI performance. In this final installment, I cover steps 5 and 6:
the routing of critical traces for the gate drives, current sense and feedback network; and a review
of power and ground (GND) plane design of the multilayer PCB substrate as well as ground
separation techniques. For a complete summary of DC/DC converter PCB layout guidelines, see
Table 1.
Step 5: Route the MOSFET gate drives, current sense, feedback and other critical traces
Step 5: Route the MOSFET gate drives, current sense, feedback and other critical traces
Understanding gate-loop and common-source parasitic inductances
MOSFET switching behavior and the consequences for waveform ringing, switching loss, device
stress and EMI are closely associated with the parasitic inductances of the switching loop and gate
circuit arising from device package and PCB layout connections [2,3]. From Figure 1, we need to
recognize the role of two parasitic inductances arising from the gate drive circuit layout.
Figure 1: SyncFET parasitic turn-on leads to undesirable shoot-through in phase-leg
configurations. This is related to displacement current from switch-node voltage dv/dt (a),
and negatively induced source voltage from body diode reverse-recovery-current di/dt (b).
LG is the self-inductance of the gate loop, including lumped contributions from the MOSFET package
and PCB trace routing, and LS is the common-source or mutual inductance shared by the drain and
gate current paths [4,5]. As shown in Figure 1, common-source inductance LS1 of the control
MOSFET (CtrlFET) increases switching loss because the di/dt of the main loop produces a negative
feedback voltage that impedes the rise and fall times of the gate-source voltage. During body diode
reverse recovery, common-source inductance LS2 contributes to spurious turn-on of the synchronous
MOSFET (SyncFET).
Minimizing gate-circuit parasitic inductances
Previously I discussed the top- and bottom-layer layouts for the 4-switch buck-boost converter [5] in
parts 1 and 2. Figures 2, 3 show the inner-layer artwork for this PCB.
The gate driver traces running from the control IC to the four MOSFETs, which are located on layers
3 and 4, are kept as short and direct as possible to reduce gate inductance. A Kelvin connection
connects the gate drive return traces directly to their respective MOSFET source terminals,
minimizing common-source inductance. The return currents for the low-side MOSFET gate drives
flow on the GND plane back to the PGND pin of the IC. To minimize gate loop area, gate and source
traces are routed side-by-side as differential pairs using 20-mil trace widths.
Figure 2: Artwork for layer 2 (a) and layer 3 (b).
Figure 3: Artwork for layer 4 (a) and layer 5 (b).
Gate loop parasitic inductance also increases the time required to refresh the boot capacitor. This is
particularly important for high duty cycle operating conditions when the SyncFET has a short
conduction time. Figure 1 highlights the boot capacitor refresh current path in green.
Routing current and voltage sense traces
Figure 3a shows the traces for current sense routed as a tightly coupled differential pair from the
shunt resistor to the IC current sense inputs. Kelvin sensing at the shunt is essential for accuracy.
Keepout boundaries ensure that vias associated with the sense return trace are isolated from GND
planes, and current sense filter components are located as close as possible to the IC.
Figure 3b shows the VOUT sense location at the point where the most accurate regulation is
achieved, typically on the lowest layer in the stackup before current flows to the load. VIN and VOUT
sense traces are low impedance to GND, but are still susceptible to the high di/dt loops of the
converter.
Step 6: Power and GND plane design; single-point grounding
Step 6: Power and GND plane design; single-point grounding
For a high-density layout, designers need to be particularly mindful to use as few vias as possible for
signal routing, particularly within high current conduction paths. This avoids a “Swiss cheese
effect,” where all layers in the PCB stackup are perforated by a large number of vias, increasing DC
resistance and compromising thermal and EMI performance. As mentioned in [6], many PC board
problems are traced back to discontinuous signal return paths, which lead to common-mode currents
and radiated emissions. If the return path is not interrupted by a gap or slot in the GND plane, highfrequency signals conduct along the trace to the load and then return immediately under that trace
due to mutual coupling.
Given that all capacitors decouple effectively only up to their frequency of self-resonance, it is
difficult to realize a wide spectral distribution of decoupling from VIN and VOUT to PGND. The
multilayer PCB is leveraged as a low equivalent series inductance (ESL) capacitor by stacking VIN
and VOUT planes above or below PGND planes. In the buck-boost converter example layout, VIN and
VOUT copper polygons are located on the top and bottom layers to provide low-resistance conduction
paths to the power terminals (part 2). Then, the inner layers of the PCB are filled with as much
copper at GND potential as possible, as shown in Figures 2, 3. AGND and PGND are commonly
denoted by two different ground symbols in the schematic. Only one connection point between
AGND and PGND is required, usually at the IC’s exposed thermal pad (DAP).
PCB layout guidelines
Step 1: Choose the PCB structure and stackup specification
1.1
1.2
1.3
1.4
1.5
1.6
A multilayer PCB structure is vastly superior to a single- or double-sided PCB
to reduce conduction loss, lower thermal impedance, mitigate EMI, and
minimize noise and interaction between traces and components.
Understand the stackup construction in terms of board thickness, copper
weight, and arrangement of core and prepreg (pre-impregnated
fibreglass/resin composite) layers [7].
Using a four-layer or six-layer PCB stackup permits a tightly coupled, solid
GND plane on layer 2. An example of a four-layer stackup is POWER-GN-SIGNAL-POWER/SIGNAL.
Improve the coupling to and effectiveness of a GND plane on the bottom side
of a two-layer design by specifying a low-height PCB. Otherwise, double-sided
designs are essentially relegated to two single-sided assemblies.
Use GND plane(s) to shield sensitive small-signal traces from power stage
switching noise.
Recognize that best practices for PCB design closely align with high density
and small solution size.
Step 2: Identify high di/dt current loops and high dv/dt voltage nodes
2.1
2.2
2.3
Minimize the area of high current, high di/dt power loops and gate-drive
loops, as these create H-fields that can magnetically couple to nearby lowimpedance circuits.
Minimize the area of high-voltage AC nodes with large dv/dt transitions – for
example, switch, boot and high-side gate drive – as these represent E-fields
that can capacitively couple to nearby high-impedance circuits.
Avoid slots, gaps and segments in the GND plane that increase the return
current path length, leading to common-mode noise currents and radiated
emissions.
Step 3: Power stage layout
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Component selection and floorplanning of the MOSFETs, decoupling
capacitors and shunt resistor should target the absolute smallest area and
circumference of “hot” loops.
Reduce power loop parasitic inductance, including partial inductances from
the MOSFET packages, decoupling capacitor, shunt resistor and PCB
interconnections, as it leads to voltage overshoot, ground bounce, ringing,
EMI and power loss [3].
With a power loop configured for horizontal current flow, add a GND plane on
the layer immediately underneath to act as a shield layer for H-field selfcancellation and reduced parasitic inductance.
Connect multiple decoupling capacitors in parallel to reduce equivalent series
resistance (ESR) and ESL.
Undesirable SyncFET spurious turn-on is strongly related to high switch-node
dv/dt as well as gate loop and common-source parasitic inductances (Figure
1). Take steps to mitigate this by decreasing gate pull-down impedance and
using tightly coupled gate and source (return) traces.
Place a resistor in series with the boot capacitor for an asymmetric gate-drive
design [6]. This attenuates voltage and current slew rates of the turn-on
transition without affecting turn-off switching loss.
Locate switch-node snubber networks and antiparallel Schottky diodes for
dead-time conduction extremely close to the SyncFET.
3.8
3.9
3.10
3.11
For optimal thermal field contours in convective environments, avoid airflow
shadowing of low-profile power MOSFETs by taller components, such as the
filter inductor and electrolytic capacitors.
Switch-node copper land area is a trade-off between managing dv/dt-related
noise and providing acceptable heat-sinking for the low-side MOSFET(s).
Large planes with high AC voltage become transmit and receive antenna
structures for radiated EMI.
Remove GND plane copper directly underneath the inductor to minimize
capacitive coupling to GND, especially if a large number of turns are needed
to obtain the inductance.
Separate the inductor terminals’ copper pours to avoid increasing the
inductor’s equivalent parallel capacitance (EPC), decreasing its self-resonant
frequency (SRF).
Step 4: Control IC placement and control section layout
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Consult device data sheets for specific layout recommendations and layout
examples.
Keep the IC close to the MOSFETs for reduced gate drive trace lengths. One
option with a two-sided layout is to locate the IC on the opposite side of the
PCB relative to the MOSFETs.
Connect the IC’s exposed thermal pad to the GND plane(s) underneath using
multiple thermal vias for heat-sinking.
Locate the VIN, VCC and boot capacitors close to the IC.
Connect the VCC capacitor’s negative terminal to PGND, as it behaves as the
return for the low-side gate drive.
Keep the FB trace short by locating the feedback resistors adjacent to the IC.
With low-IQ converters that demand high-resistance feedback components, be
mindful that the FB node is particularly susceptible to noise pickup.
Use short traces for other critical analog nodes such as error amplifier output
(COMP), frequency set (RT) and slope compensation (SLOPE) inputs.
Use a dedicated GND plane moat for small-signal component return currents.
Connect this plane to the IC’s analog GND pin (AGND).
Connect PGND and AGND at the IC for single-point grounding.
Step 5: Routing of critical traces – gate drive, current sense, voltage sense
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Make the gate driver trace runs from the controller to the MOSFETs as short
and direct as possible to minimize gate loop parasitic inductance. Use at least
20-mil trace widths.
Reduce common source inductance (the mutual effect between the gate loop
and switching loop) by tying the gate drive return directly to the source
terminal of the MOSFET.
Route the gate drive traces orthogonal to the power stage to avoid mutual
coupling.
Place the gate and source traces parallel to each other on one layer or
vertically aligned on adjacent layers to reduce inductance and high dv/dt
noise.
Place the low-side gate drive trace close to a PGND plane such that the return
current is mutually coupled in a path underneath the trace.
For very high duty cycle operation, minimize the parasitic inductance in the
boot capacitor refresh current path through the low-side MOSFET.
Route the current-sense traces as a tightly coupled differential pair. Locate
current-sense filter components close to the IC.
5.8
5.9
Use keep-outs to ensure that vias for ground-referenced sense return are
isolated from GND planes.
Sense VOUT at the point where accurate regulation is required (usually at the
point of load). Keep VIN and VOUT sense nets away from high di/dt loops.
Step 6: Power and GND plane design
6.1
6.2
6.3
6.4
6.5
Keep the copper planes solid and continuous by minimizing the number of vias
used for signal routing.
Use many vias in parallel close to the decoupling capacitors’ terminals to
connect to power and GND planes. Place positive and negative via pairs close
to each other for flux cancellation.
Fill in both top and bottom layers of the PCB with as much copper at GND
potential (ground fill) as possible.
Beware of hidden antenna structures where the conduction path dimension
approaches one-quarter wavelength (or a multiple) at the frequency of
interest.
Finally, review the PCB layout and flush out any design-rule violations [8].
Table 1: Summary of PCB layout guidelines for DC/DC converters.
Summary and References
Summary
It’s fair to say that PCB layout defines the performance that a switching power converter ultimately
achieves. In totality, this series of articles offered a step-by-step approach to PCB design. The prime
benefactor may well be the designer or their trustworthy technician, who avoids countless hours of
debugging time for EMI, noise, signal integrity and other issues related to a poor layout.
References
1. T. Hegarty. “DC/DC power converter PCB layout,” Part 1 and Part 2.
2. J. Wang and H. Shu-Hung. “Impact of parasitic elements on the spurious triggering pulse in
synchronous buck converter.” IEEE Trans. on Power Electronics, December 2010, pp. 6672-6685.
3. “Layout tips for EMI reduction in DC/DC converters.” Texas Instruments Application Report
SNVA638A, April 2013.
4. K. Wang et al. “An optimized layout with low parasitic inductance for GaN HEMTs based DC/DC
converter.” APEC 2015, pp. 948-951.
5. Texas Instruments LM5175EVM-HD 400-kHz high-density buck-boost converter evaluation
module.
6. K. Wyatt and R.J. Lost. “EMC pocket guide.” Scitech Publishing, 2013.
7. Multi-circuit boards, Design Aid: Layer buildup.
8. C. Glaser. “How to do a PCB layout review.” Texas Instruments Fully Charged blog, May 20,
2015.