studies on high-speed digital-to-analog conversion
STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG
CONVERSION
DISSERTATION
Presented in Partial Fulfillment of the Requirements for the Degree
Doctor of Philosophy in the Graduate School of The Ohio State University
By
Sidharth Balasubramanian, B.E., M.S.
Graduate Program in Electrical and Computer Engineering
The Ohio State University
2013
Dissertation Committee:
Dr. Waleed Khalil, Advisor
Dr. Patrick Roblin
Dr. John L. Volakis
c Copyright by
Sidharth Balasubramanian
2013
Abstract
Despite the tremendous advancement in innovations in digitizing and processing signals over the last century, real world signals are inevitably analog in nature. Several approaches have been researched and deployed in order to facilitate the maneuver between the digital and analog domains. Specifically, digital-to-analog converters (DACs) are the lynchpin in systems that realize this art of moving from the digital to the analog world.
Several real-world imperfections and limitations have impeded the efficacy of DACs in terms of accuracy, speed and power. Howbeit, a myriad of efforts has been made in the recent past towards improving the performance of DACs. Furthermore, the fundamental conception of DACs poses several challenges at the architectural, circuit and technological levels. These challenges mandate a solid understanding in order to enable DAC designers to move up and down the device-circuit-architecture ladder with dexterity.
A closer look at the genetic conception of DACs also reveals interesting answers behind some of the well-known questions, such as: How is the spectral performance related to the resolution? Why does distortion in DACs degrade at high frequencies? In order to effectively address these questions, the science behind digital to analog conversion needs to be revisited from a fresh perspective - what is called as a genetic bit-by-bit engineering approach. Such a radical study leads to fascinating ways to conceive DACs that perform well above their expected limit.
This dissertation aims to provide a neoteric and holistic view of the fundamental conception, limitations and challenges in how digital data transcends into the analog ii
world. The quantitative study of this process leads to several transformational benefits; of most importance is the ability to engineer D/A converters to provide high resolution performance with low-resolution data, thereby creating the doors to a brand new field of compressive transmission.
iii
To my Parents and Teachers iv
Acknowledgments
I am indebted to several people who made my journey as a graduate student possible. I would like to thank my parents who gave me various opportunities to pursue my interests in academia and music. Without their love, support and encouragement, nothing would have been possible.
OSU was one among my chosen destinations to pursue graduate studies, and the
University Fellowship awarded in 2008 was the primary reason for my decision to come here. I would like to thank all the anonymous reviewers who took the time to review my application and recommended me for the fellowship.
I wish to begin expressing my sincere gratitude to my advisor, Dr. W. Khalil, for having shown utmost concern towards my progress. Much of my learning and growing up as an individual in the last few years has been tremendously influenced by him. His tireless quest for perfecting ideas on paper and slides, continues to motivate me to search for perfection. Dr. Khalil and I have brainstormed a number of times on various ideas;
True to its name, most of these sessions were storming indeed. I sincerely appreciate him for all the patience, confidence and trust he has in me.
My gratitude to Dr. John Volakis, for having graciously served on my candidacy, while being out of the country. I am also thankful to him for giving me the opportunity to work with him and his students on a beamforming project. This project was the primary reason for having known new friends apart from Dr. Khalil’s group.
Dr. Patrick Roblin for taking the time to serve on my defense committee.
v
Dr. Steven Bibyk and Dr. Lee Potter, for serving on my candidacy committee.
Dr. Mohammed Ismail, for being my MS advisor and giving me the opportunity to experience and serve in the role of a reviewer.
Dr. Oren Eliezer, Oren as I fondly call him, is the man who offered me my first internship. Oren and I have had several conversations on random topics from academia and corporate to family and friends. I still remember the day when we accidentally reinvented the Gram-Schmidt Orthogonatization procedure on his whiteboard. We have mutually enjoyed our brainstorming sessions and benefited from each others’ approach towards a problem.
My interactions with Dr. Marian Verhelst were also critical in the development of the universal model for time-interleaved DACs. I thank her for the valuable insights and all that time she took to revise my paper.
Dr. PVR at the Integrated Systems Laboratory, for graciously providing me with resources beyond the classroom, that aided me to mould myself to pursue research.
Molly, Cindy, Tricia, Stephanie, Sherry, and Lisa, for dynamically serving in their respective roles.
Kevin, for having been a great source of help in administering software packages and licenses.
Vipul at the AirForce Research Labs, for assisting me with my book chapter.
Dr. Wilson at the Army Research Labs.
To my colleagues at the Electroscience Laboratory, for serious discussions and lazy chats.
To my friends at OSU, for really making Columbus a ‘home away from home’.
vi
Vita
May 12, 1987 . . . . . . . . . . . . . . . . . . . . . . . . Born – Coimbatore, India
June 2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . B.E., College of Engineering, Guindy, India
December, 2009 . . . . . . . . . . . . . . . . . . . . . . M.S., The Ohio State University, Columbus, OH
October 2008 - September 2009 . . . . . . . Graduate Fellow
October 2009 - December 2009 . . . . . . . Graduate Teaching Assistant
January 2010 - June 2010 . . . . . . . . . . . . . Graduate Research Assistant
September 2010 - December 2010 . . . . . Xtendwave Inc., Richardson, TX
January 2011 - June 2013 . . . . . . . . . . . . . Graduate Research Assistant
September 2008 . . . . . . . . . . . . . . . . . . . . . . The Ohio State University Fellowship
August 2010 . . . . . . . . . . . . . . . . . . . . . . . . . TSMC Outstanding Student Research Award
February 2011 . . . . . . . . . . . . . . . . . . . . . . . . IEEE Solid State Circuits Society Travel Grant
February 2011 . . . . . . . . . . . . . . . . . . . . . . . . NSF-MIPR Fellowship
January 2013 . . . . . . . . . . . . . . . . . . . . . . . . . Outstanding Journal Article, ElectroScience Lab
January 2013 . . . . . . . . . . . . . . . . . . . . . . . . . Best Paper Award, Wireless Innovation Forum vii
Publications
BOOK CHAPTERS
S. Balasubramanian , V. J. Patel and W. Khalil, “Current and emerging trends in the design of digital-to-analog converters”, in Design, Modeling and Testing of Data Converters , Signals and Communication Technology, Carbone, Paolo; Kiaei, Sayfe; Xu, Fang
(Eds.), Springer-Verlag Berlin Heidelberg, 2014 doi: 10.1007/978-3-642-39655-7 3
JOURNALS
S. Balasubramanian and W. Khalil, “Architectural trends in current-steering digital-toanalog circuits”, Journal of Analog Integrated Circuits and Signal Processing , 2013 doi:
10.1007s10470-013-0082-2 Invited
E. A. Alwan, S. Balasubramanian , J. G. Atallah, M. R. Larue, W. Khalil, K. Sertel and
J. L. Volakis, “Coding-based ultra-wideband digital beamformer with significant hardware reduction”, Journal of Analog Integrated Circuits and Signal Processing , 2013 doi:
10.1007/s10470-013-0102-2 Invited
S. Balasubramanian , S. Boumaiza, H. Sarbishaei, T. Quach, P. Orlando, J. L. Volakis, G.
L. Creech, J. Wilson and W. Khalil, “Ultimate transmission”, IEEE Microwave Magazine ,
Feb 2012 Invited
S. Balasubramanian , G. L. Creech, J. Wilson, S. M. Yoder, J. J. McCue, M. Verhelst and W. Khalil, “Systematic analysis of interleaved digital-to-analog converters”, IEEE
Transactions on Circuits and Systems - II: Express Briefs , Dec 2011
S. Balasubramanian and W. Khalil, “Direct digital-to-RF digital-to-analogue converter using image replica and nonlinearity cancelling architecture”, IET Electronics Letters , July
2010 Top Five Papers of the Issue
CONFERENCE PROCEEDINGS
S. M. Yoder, S. Balasubramanian , V. J. Patel and W. Khalil, “Accuracy and speed limitations in DACs across CMOS process technologies”, IEEE Midwest Symposium on
Circuits and Systems , Aug 2013 viii
O. E. Eliezer, Y. Liang, D. Rajan, S. Balasubramanian and W. Khalil, “A new broadcast format and receiver architecture for radio controlled clocks”, IEEE Midwest Symposium on Circuits and Systems , Aug 2013 Student Paper Contest Finalist
E. A. Alwan, S. Balasubramanian , J. G. Atallah, M. R. Larue, W. Khalil, K. Sertel and J. L. Volakis, “Ultra-wideband digital beamformer with significant SWAP-C reduction”, Wireless Innovation Forum on Wireless Communications Technologies and Software
Defined Radio , Jan 2013 Best Paper Award
S. Balasubramanian and W. Khalil, “Architectural trends in GHz-speed digital-to-analog converter”, IEEE Nordic Microelectronics Event (NORCHIP) , Nov 2012
E. A. Alwan, S. Balasubramanian , J. G. Atallah, M. R. Larue, W. Khalil, K. Sertel and
J. L. Volakis, “Coding-based transceiver for phased array with significant hardware reduction”, IEEE International Conference on Wireless Information Technology and Systems ,
Nov 2012
W. Khalil, J. Wilson, B. Dupaix, S. Balasubramanian and G. L. Creech, “Towards
Millimeter-Wave DACs: Challenges and emerging trends”, IEEE Compound Semiconductor IC Symposium (CSICS) , Oct 2012
J. Lowe, M. Deutch, G. Nelson, D. Sutton, W. Yates, P. Hansen, O. Eliezer, T. Jung, S.
Morrison, Y. Liang, D. Rajan, S. Balasubramanian , A. Ramasami, and W. Khalil, “New improved system for WWVB broadcast”, 43 rd Annual Precise Time and Time Interval
(PTTI) Meeting , Nov 2011
S. Balasubramanian and M. Ismail, “Rail-to-rail Input Stages: A voltage-mode design technique and a figure of merit”, IEEE Northeast Workshop on Circuits and Systems
(NEWCAS) , 2010
S. Balasubramanian , “Optical modulators using planar split ring resonators”, IEEE
National Aerospace and Electronics Conference (NAECON) , 2009
REPORTS
S. M. Yoder, S. Balasubramanian , V. J. Patel and W. Khalil, “Rapid and Parameterizable DAC Compiler User Guide”, 2013.
[Online].
Available: http://esl.eng.
ohio-state.edu/~class/DACmodel.html
ix
PATENTS AND DISCLOSURES
Utility Patents
United States 20120169397
Mixed Signal Integrator Incorporating Extended Integration Duration
Inventors: S. Balasubramanian and O. E. Eliezer, Filed Nov. 2011
Provisional Patents
United States 61/705,930
Ultra-Wideband Digital Beamformer using On-site Coding Techniques
Inventors: S. Balasubramanian , E. A. Alwan, W. Khalil, K. Sertel and J. L. Volakis,
Filed Sep. 2012
United States 61/424,697
Low-Power, High-Performance Rail-to-Rail CMOS Operational Amplifiers
Inventors: S. Balasubramanian and M. Ismail, Filed Dec. 2010
Disclosures
OSU Tech ID 2012-186
An Apparatus for High-speed Low-latency Switching in Digital-to-analog Converters
Inventors: S. Balasubramanian and W. Khalil, Filed Mar. 2012
OSU Tech ID 10169
An ultra-wideband Digital-to-analog Converter using Image Replica and Nonlinearity Canceling Architecture
Inventors: S. Balasubramanian and W. Khalil, Filed Aug. 2010
Fields of Study
Major Field: Electrical and Computer Engineering
Studies in:
RF Circuits Dr. Waleed Khalil
Analog Circuits Dr. Mohammed Ismail
Antennas and Electromagnetics Dr. John L. Volakis x
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page ii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xviii
Chapters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
From a Single Band Transmitter ... . . . . . . . . . . . . . . . . . . . .
4
... to a Multiband Transmitter . . . . . . . . . . . . . . . . . . . . . . .
The Holy Grail: Ultimate Radio . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
6
8
2 Digital-to-Analog Conversion
. . . . . . . . . . . . . . . . . . . . . . . .
13
The Big Picture of Data Representation . . . . . . . . . . . . . . . . . .
13
What is Digital-to-Analog Translation? . . . . . . . . . . . . . . . . . .
16
Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Static Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Dynamic Metrics . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Influence of static metrics on the dynamic metrics - INL Induced
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Implementation of DACs . . . . . . . . . . . . . . . . . . . . . . . . . .
26
High-Speed DACs: The current-steering architecture . . . . . . . . . . .
28
State-of-the-art in DACs . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3 Fundamental Limitations in DACs
. . . . . . . . . . . . . . . . . . . . . .
31
Sampling and Hold Operation . . . . . . . . . . . . . . . . . . . . . . .
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Spurious limitations of a DAC . . . . . . . . . . . . . . . . . . . . . . .
40
Derivation of 9 dB/bit trend . . . . . . . . . . . . . . . . . . . .
46
Effect of sampling on the achieved SDR
. . . . . . . . . . . . .
47 xi
Two-tone analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
4 Practical Challenges in DACs
. . . . . . . . . . . . . . . . . . . . . . . .
53
The current-steering cell . . . . . . . . . . . . . . . . . . . . . . . . . .
55
. . . . . . . . . . . . . . . . . . . . . . .
55
Switching Speed . . . . . . . . . . . . . . . . . . . . . . . . . .
56
Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . .
60
Device Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Signal Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
The Segmentation Philosophy . . . . . . . . . . . . . . . . . . . . . . .
79
Segmentation driven by Area and static linearity metrics . . . . .
79
Segmentation driven by micro-level challenges
. . . . . . . . . .
83
Challenges at the Macro-level . . . . . . . . . . . . . . . . . . . . . . .
86
. . . . . . . . . . . . . . . . . . .
87
Analog and Digital IR Drop . . . . . . . . . . . . . . . . . . . .
91
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
A high-speed low-latency DAC cell
. . . . . . . . . . . . . . . . . . . .
98
Interleaved DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
Proposed Model . . . . . . . . . . . . . . . . . . . . . . . . . .
103
Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . .
104
Area and Power Overhead . . . . . . . . . . . . . . . . . . . . .
110
Return-to-Zero (RZ) DACs . . . . . . . . . . . . . . . . . . . .
110
Mismatch and Nonidealities . . . . . . . . . . . . . . . . . . . .
112
Bandwidth limitations . . . . . . . . . . . . . . . . . . . . . . .
115
Observations and Design Considerations
. . . . . . . . . . . . .
117
6 Architectural Trends in DACs - A Summary
. . . . . . . . . . . . . . . .
119
Addressing the Grand Challenges . . . . . . . . . . . . . . . . . . . . .
120
Intrinsic Accuracy DACs . . . . . . . . . . . . . . . . . . . . . .
121
R-2R DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
High-Frequency Synthesis by Replica filtering . . . . . . . . . . .
122
Return-to-zero (RZ) DACs . . . . . . . . . . . . . . . . . . . . .
124
Interpolation DACs . . . . . . . . . . . . . . . . . . . . . . . . .
127
RF DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
Interleaved DACs . . . . . . . . . . . . . . . . . . . . . . . . . .
131
Power DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
. . . . . . . . . . . . . . . . . . . . . . . . . .
134
Generic representation of a bit . . . . . . . . . . . . . . . . . . . . . . .
135
Non-linearity of a bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Sampling a bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
146 xii
DACs with intentional bit mismatches . . . . . . . . . . . . . . . . . . .
147
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170 xiii
List of Figures
Figure Page
Radio evolution over the spaces of programmability and functionality
. .
Multiband transmitter using a radio array . . . . . . . . . . . . . . . . .
SDR evolution: Past, present and future
. . . . . . . . . . . . . . . . .
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
The Quantizer Grid: Data representation . . . . . . . . . . . . . . . . .
15
A sinusoidal signal within the quantizer grid . . . . . . . . . . . . . . . .
17
Basic functions within a 3-bit digital-to-analog converter . . . . . . . . .
18
3-bit DAC Transfer Function: (a) Offset error (b) Gain error (c) DNL (d)
INL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Spectral plots for a 12-bit DAC . . . . . . . . . . . . . . . . . . . . . .
22
Static INL shaping and the resulting effects on power spectral density . .
26
A segmented current-steering DAC architecture . . . . . . . . . . . . . .
28
30
4
7
8
Fundamental limitations in an ideal DAC . . . . . . . . . . . . . . . . .
32
A mid-rise Quantizer (a) Transfer function (b) Quantization error . . . .
35
Density distributions for the input and output of the quantizer . . . . . .
36
Illustration of the process of obtaining the density distribution of W
38
Block diagram of the area sampling . . . . . . . . . . . . . . . . . . . .
39
Probability density distribution of quantization error (noise) . . . . . . .
39
Effect of resolution on the power of the fundamental . . . . . . . . . . .
43
Effect of resolution on the levels of the harmonics
. . . . . . . . . . . .
44
Effect of resolution on signal-to-distortion ratio (SDR) . . . . . . . . . .
45
3.10 Deviation in SDR for various resolutions . . . . . . . . . . . . . . . . . .
48
3.11 SDR as a function of frequency: Non-prime sampling . . . . . . . . . . .
49
3.12 SDR as a function of frequency: Prime sampling . . . . . . . . . . . . .
50 xiv
3.13 Signal-to-third-order-intermod level improves with resolution, by roughly
12 dB/bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
54
An array of switched current cells . . . . . . . . . . . . . . . . . . . . .
56
Switching and settling behaviors in a transistor . . . . . . . . . . . . . .
57
High-speed switching phenomena . . . . . . . . . . . . . . . . . . . . .
58
Dependence of the transistor switching time on current
. . . . . . . . .
59
T as a function of feature length
. . . . . . . . . . . .
60
A cascoded current source . . . . . . . . . . . . . . . . . . . . . . . . .
61
(a) Low-frequency (DC) output impedance ( Z
(0) ) (b) High-frequency output impedance ( Z
CS at 100 MHz) . . . . . . . . . . . . . . . . . . .
62
Impact of transistor size and current on impedance . . . . . . . . . . . .
64
4.10 Impedances in a current-steering cell
. . . . . . . . . . . . . . . . . . .
65
. . . . . . . . . . . . . . . . . . .
66
4.12 Cell-level cascoding offers no benefits at high frequencies . . . . . . . . .
67
4.13 (a) Glitch propagation from the source node (b) Modulation of the current source
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
4.14 Noise sources in a DAC . . . . . . . . . . . . . . . . . . . . . . . . . .
71
72
4.16 Output swing as a function of the LSB current for various DAC resolution
73
4.17 A modified DAC cell with leakers and neutralization switches
. . . . . .
75
4.18 The DAC design space: device noise, output impedance, signal swing and switching speed
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
T mismatch as a function of gate area
. .
78
4.20 Maximum permissible error in MSB current cell . . . . . . . . . . . . . .
80
4.21 Optimum segmentation based on area and static linearity specifications .
82
85
4.23 Macro-level challenges in a DAC . . . . . . . . . . . . . . . . . . . . . .
87
4.24 (a) A H-tree for clock feeds (b) Buffer requirements in a H-tree . . . . .
88
4.25 Issues caused in a buffer chain . . . . . . . . . . . . . . . . . . . . . . .
89
4.26 (a) Jitter accumulation in a buffer chain (b) Jitter limitations on SNR . .
90
92
94
4.29 The problem of digital supply bounce . . . . . . . . . . . . . . . . . . .
95
96
A modified DAC cell with leakers and neutralization switches
. . . . . .
99 xv
(a) A high-speed low-latency DAC cell (b) Timing matching in the HSLL
DAC cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
102
104
Time-interleaved sampling and reconstruction - Proposed model with mismatches
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
Rotation and cancellation of image replicas in the complex domain for (a)
Sub-Nyquist signal generation (b) Beyond-Nyquist signal generation . . .
109
. . . . . . . . . .
111
Effect of Gain Mismatch on SIRR (a) RZ mode (b) NRZ mode . . . . .
114
116
5.10 Effect of Timing Mismatch on SIRR (a) RZ mode (b) NRZ mode . . . .
117
Conception of an N -bit R-2R DAC . . . . . . . . . . . . . . . . . . . .
123
(a) Return-to-zero Hold Waveform (b) RZ hold response . . . . . . . . .
125
(a) Voltage-mode RZ (b) Current-mode RZ . . . . . . . . . . . . . . . .
126
Interpolation DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
(a) A simplified block diagram of an RF DAC (b) Noise-shaping RF DAC
(c) Noise-shaping RF DAC Output using 2 nd -order, 3-bit ∆Σ Modulator
129
(a) Global mixing in RF DACs (b) Local mixing in RF DACs . . . . . . .
131
Power Mixer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
(a) Binary search algorithm (b) Flash algorithm . . . . . . . . . . . . . .
136
140
(a) Harmonic levels in each bit (b) Magnitude of the harmonic levels in each bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
Effective fundamental and harmonic levels as a function of the number of
MSBs used in the representation
. . . . . . . . . . . . . . . . . . . . .
144
Analog-to-digital-analog conversion: (a) Without sampling in time (b)
With sampling in time . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
146
The effect of mismatch in binary weights upon the achievable SDR for
1000 test cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
148
149
Mixer-based model for a 5-bit DAC . . . . . . . . . . . . . . . . . . . .
150
7.10 Mismatched mixer-based model for a 5-bit DAC
. . . . . . . . . . . . .
151 xvi
7.11 Improvement in distortion levels with binary mismatches in a 5-bit DAC .
152
7.12 Improvement in distortion levels with binary mismatches in an 8-bit DAC
153
154
. . . . . . . . . . . . . . . . . . . . . .
155
7.15 Case 3 - An 8-bit DAC with non-binary weights on the second and third
LSBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156 xvii
List of Tables
Table Page
Comparison of the binary, unary and segmented DAC architectures
. . .
97 xviii
Chapter 1
Introduction
The rapid and revolutionary growth of wireless communication following the First World
War, with applications ranging from commercial cellular communication to space weather
modeling and prediction, has resulted in an increased competition for scarce spectrum 1 .
Since the inception of smart phones, the demand for spectrum access and the growth in
that demand are increasing exponentially with stringent performance specifications [1–4].
Additional high-growth demand for spectrum exists across multiple sectors such as aviation, homeland security, public safety and national defense - all of them being increasingly data-driven. Such unprecedented surge in demand for high data rates, along with the coexistence of “software revolution”, has motivated the preferment for efficient spectrum
access, or otherwise referred to as the software radio (SR) technology. Furthermore, op-
tical networks once thought to offer abundant capacity, is now scrambling to meet data
demand, and thus employing complex modulation formats [5]. This accelerated shift to
GHz-per second in wireless and Tbps in wired networks would not have been possible, if not for the continued scaling in power, area and speed called for by the Moores law.
The perennial challenge in these systems then becomes how to move such unprecedented bandwidths of data across from the digital domain to the physical (analog) domain. After
1 The use of the spectrum in the United States of America is regulated by the Federal Communications
Commission (FCC) and the Department of Commerce’s National Telecommunications and Information
Administration (NTIA)
1
all, the world is analog in nature.
The concept of SR was introduced in the late 1990s as a successor to digital radio
[1]. It referred to a radio transceiver where the antenna signal is sampled directly by an
while offering ultimate re-configurability and hardware reuse, it required data converters that were far from being realizable at the time with unparalleled dynamic range over
several gigahertz of bandwidth. Alternatively, a software-defined radio (SDR) was touted
as a realizable version of software radio by allowing for some additional hardware and filtering, thus greatly relaxing the requirement on data converters. More recently, SDRs were broadly defined and classified into four tiers - from Tier 1 being a pure hardware
centric conventional radio solution to Tier 4 being an entirely software radio [2]. Tier
4 software radios possess the unique feature of operating across a multi-GHz frequency band with simultaneous operation in multiple bands, being adaptable to any of the existing
communication standards. Figure 1.1 illustrates the evolution of radios over the spaces
of programmability and increasing functionality. Current state-of-the-art radios still lie in between Tiers 2 and 3, i.e. they have not been completely digitized yet. Besides
intelligence by sensing the spectrum environment, tracking and adapting to changes in real-time. Such radio systems can automatically adapt its physical system parameters, such as carrier frequency, dynamic range, and power consumption, in response to the
radio environment and user demands. CR technology is anticipated to become a general-
purpose programmable radio that will serve as a universal platform for wireless system development, much like microprocessors have served a similar role for computation.
Initially thought CRs and SDRs promised software programmability of a variety of mod-
2
ulation waveforms, enabling multiple radios to operate simultaneously across the entire
devices. Advances in electronics miniaturization have so far been the engine for cost and performance gains in both military and commercial systems. More recently, breakthroughs
in silicon-based technologies have accelerated the shift towards CMOS System-on-Chip
(SoC) solutions combining complex RF, analog and digital functionality. These advances
along with the introduction of newer generations of communication systems and the unprecedented surge in demand for high data rates, motivated the search for a purely digital
multiple signals, separately or simultaneously, have been lagging.
Figure 1.1: Radio evolution over the spaces of programmability and functionality
3
1.1 From a Single Band Transmitter ...
Prior to outlining the challenges involved in the design of digital transmitters, it is important to realize the limitations of a conventional single band transmitter. The conventional
transmitter architecture in Fig. 1.2(a) illustrates a classical homodyne transmitter. It is
clearly observed that significant amounts of RF processing are involved. The digital base-
the baseband signal to the carrier frequency. High-frequency translation may take place in a single step (direct or homodyne conversion) or in multiple conversion steps (heterodyne conversion). In general, homodyne conversions are more ubiquitous than heterodyne conversion, owing to their simplicity in frequency planning and reduced hardware cost.
(a) (b)
Figure 1.2: (a) Classical transmitter and (b) Detailed block diagram of a classical trans-
mitter
To get a better understanding of the transmitter signal processing chain, let us consider
4
the illustrative block diagram shown in Fig. 1.2(b). The DAC circuit is sub divided into
three main cells:
• A binary-switched current source array, each switching a current 2 k × I , where k = 0 , 1 , 2 , ..., N − 1 for an N-bit DAC and I represents the unit current source magnitude based on a particular full-scale current level
• Array of current-commutating switch-pair to steer the direction of the current into one of the differential arms of the DAC output based on the digital input level
• Two resistor cells (typically 50 Ω each) to convert the differential DAC output current to voltage (I-to-V)
The output of the DAC in the time domain generally comprises a non-return-to-zero
(NRZ) reconstructed baseband signal, as shown at the bottom of Fig. 1.2(b). In the
frequency domain, the output shows the desired baseband signal, f
0
, in addition to the
DAC image replicas (aliases). A low-pass reconstruction filter (LPF) follows the DAC output to remove the unwanted image replicas. It is to be noted that the baseband modulation bandwidth representing the information content is set well below the Nyquist frequency of the DAC clock, which is typically in the order of hundreds of megahertz.
Similar to the DAC, the mixer stage following the LPF comprises three main stages:
• Transconductance ( g
M
) stage that converts the input baseband voltage signal into current (V-to-I)
• Current commutating switch pair that is controlled by the local oscillator (LO) signal and commutes the current between the two differential branches of the mixer
• Two resistor cells comprising the I-to-V stage.
A complex ( I/Q ) mixer is typically used to achieve single sideband up-conversion of the baseband signal near the LO carrier frequency. After the mixer, a balun is used to convert
5
the differential signal into a single-ended signal. A band-pass filter (BPF) is then added to remove the mixing harmonics before the signal is fed to the PA.
It is worth noting that across the transmitter signal chain, the frequency translation stage (i.e. mixer) is often the major contributor for nonlinearity. This can be attributed to the finite dynamic range of the transconductance (V-to-I) stage and the limited speed of the switch-pair device. Moreover, the spectral purity of the up-converted signal is often a major limitation in RF and microwave systems primarily due to the finite purity of
available frequency synthesizers
. In addition to these limitations, the need for I-to-V and
V-to-I conversion stages between every block in the chain further contributes nonlinearity and mismatches. Apart from suffering from nonlinearity issues, there are I/Q gain/phase mismatches, LO leakage and spurs.
All of these contribute to a degraded EVM 3
at the transmitter output. Thus, it is difficult to adapt this architecture to multi-band transmitters.
1.2 ... to a Multiband Transmitter
A straightforward approach to architecting transmitters for multi-band applications is to
use a single radio with a swept local oscillator (Fig. 1.2(a)). With improvements in
the CMOS integration, multi-carrier direct conversion transmitters have been the most prevalent architecture for a long time, but bring with it extremely stringent requirements on sideband suppression and spur levels. Assuming SDR’s Tiers 3 and 4 requirements for continuous-band operation, there is either the need for multiple voltage controlled oscillators (VCOs) or a single VCO that spans a multi-GHz range of frequencies. Recently, a lot of work has been devoted to the study of single oscillators that can span over a multi-GHz band. While new circuit architectures have shown some promising results in achieving ultra-wide tuning capability, their phase noise performance remains to be sub-
2 The spectral purity is often represented in the form of phase noise and spurs added by the LO signal
3 Error Vector Magnitude
6
par. In addition, for the phase locked loop (PLL) that generates the local oscillator signal, there exists a tradeoff between switching speed and phase noise agility, which ultimately limits the multi-mode feature or the spectral purity. Moreover, a single DAC-mixer path combined with a single or multiple VCOs, while meeting the wideband operation, does not permit simultaneous multi-band operation, which is also a requirement for Tiers 3 and 4 SDRs.
Figure 1.3: Multiband transmitter using a radio array
Another alternative for multi-band transmitters is to architect an array of transmitters,
as illustrated in Fig. 1.3. Each transmitter of the array operates on a specific band, with
the combined output of all transmitters ’stitching’ spectrums together to achieve multiband capability. However, such a radio implies addition of multiple parallel radios with the introduction of newer bands of operation, thus leading to high cost as well as size, weight, and power inefficiency. Another challenge stems from combining several PLLs in the same silicon substrate and operating them simultaneously, since this increases the risk of coupling between VCOs and false locking. Further, great care needs to be taken in for the harmonics of a band to not fall into other bands given the large combinations of mixers and mixing products. The use of a switch to choose between the outputs of the various transmitters still presents us with the issue of simultaneous multiband operation. As a result, there is the need to develop software radios that have the flexibility of re-targeting
7
system requirements from software re-programming rather than hardware re-design which is costly and require a long development cycle.
1.3 The Holy Grail: Ultimate Radio
Over the past half a century, transmitters have evolved tremendously in enabling wider bandwidths and higher performance than their conventional hardware-centric counterparts.
Figure 1.4 summarizes the evolution of wideband SDR transmitters from the past to the
future, with the ultimate goal being re-configurability.
Figure 1.4: SDR evolution: Past, present and future
The design for transmitter re-configurability involves a great number of challenges in
various fronts. As discussed earlier, the transmitter in Fig. 1.2(a), comprises three major
8
stages, viz. the digital baseband to analog conversion, mixer up-conversion, and finally the power amplification stage. Much of the nonlinearities is attributed to the mixer upconversion and power amplification. While there have been numerous efforts in reducing the effects of these nonlinearities such as digital pre-distortion, harmonic mixers, polyphase mixers, etc., the most straightforward solution to suppress the mixer nonlinearity at the transmitter output is the removal of the mixer itself, and eventually building a mixerless transmitter. This Holy grail of digital radios offers unparalleled programmability and hardware reuse.
If we look closer into this Holy grail, it comprises no more than a digital baseband, followed by high-speed high-power D/A conversion. This eventually leads to four major challenges: 1. Design of a highly linear ultra-high bandwidth digital-to-analog converter;
2. A digital I/O channel capable of handling very high speeds; 3. Wideband Power
Amplification; and finally 4. Wideband Matching between the PA and the antenna
Let us briefly discuss each one of the above challenges. While narrowband antennas can
be tuned to reach optimal gains, the well known Chu [9] and Fano-Bode [10] limits place
theoretical restrictions on the maximum achievable gain-bandwidth product, subject to a pre-specified antenna size. Indeed, the achievement of wide bandwidths with conformal antennas (very thin) has been a lofty goal. However, this has been made possible with the use of slow-wave structures on a current-sheet that helped achieve 20:1 bandwidths.
Thus, they provide further impetus towards the realization of wholly-digital ultra wideband transmitters.
Wideband power amplification has also been the subject of research for a very long time. The design of wideband high efficiency power amplifier requires controlling the fundamental matching network and its harmonics for a wide frequency range. Several techniques have been used to design the matching network, for example Simplified Real
Frequency Technique (SRFT) [11]. Excellent experimental results have been recently
9
reported for wideband high efficiency power amplifiers exceeding 40% to 50% relative
bandwidth [12]. The combination of wideband power amplifiers with existing drain mod-
ulation techniques can lead to a truly multi-standard/multi-band transmitter. A synopsis
of various power amplification techniques has been reported in [4].
The digital I/O channel needs to handle the speed requirements of the digital-to-analog converter. For an 8-bit 32GS/s DAC, data must be supplied at the rate of 256Gbps;
Meeting this data rate is a formidable challenge. Moderate-speed DACs (around 500
MS/s) often solve this issue by internally muxing a parallelized data stream provided by an FPGA. Nevertheless, the maximum off-chip data transfer rate places exorbitant demands on the number of parallel streams. Such I/O bottlenecks are often addressed by
means of GHz-speed SERDES channels or on-chip memories [13].
Finally, the challenge of designing highly linear DACs with large bandwidths; So far,
DACs with unparalleled dynamic range over several gigahertz of bandwidths have been non-realizable. While the process f
T limits the maximum sampling speed of a DAC, circuit-level imperfections such as limited impedance, finite gain, process variations and many more, affect the achievable linearity and resolution. Furthermore, the design for high-speed also comes at a sacrifice of dynamic range, linearity and resolution, which will be explained in subsequent chapters.
1.4 Dissertation outline
There has been a myriad of efforts in the recent past towards improving the bandwidth of DACs, while providing high resolution. However, the fundamental conception of the
DAC poses several challenges at the architectural, circuit and technological levels that need a solid understanding, in order to enable DAC designers to move up and down the device-circuit-architecture ladder with dexterity. This dissertation aims to provide both a neoteric and holistic view of the fundamental conception, limitations and challenges in the
10
design of digital-to-analog converters. Some of the material in the following chapters has already been published in journals authored by the dissertation author. These publications have been peer-reviewed prior to the compilation of this document. The dissertation is outlined as follows:
Chapter 2 details the digital-to-analog conversion process and implementation. While the realization of DACs can be voltage or current mode, the latter is often preferred for high-speed operation ( > 100 MS/s), esp. when designing standalone DACs. The rest of the dissertation is therefore limited in its discussion to current-mode DACs. Chapter 2 also provides a review of some of the fundamental metrics to quantify the non-idealities in the D/A conversion process.
Chapter 3 delves into the fundamental limitations imposed by the conversion process.
The process of quantization in a DAC is studied from the perspective of the final representation in order to obtain the bounds on linearity of a converter: a 9 dB/bit trend in linearity, with a frequency-dependent degradation is predicted for DACs.
In the realization phase, a number of other challenges appear that hinder the achievable performance of the D/A conversion process. Chapter 4 focuses on developing the current-steering architecture, device-at-a-time, while describing the technological challenges involved in achieving various specifications. Upon completion of the DAC core and laying out the peripheral circuitry, several other challenges still remain that indirectly, yet significantly, impact the DAC’s achievable performance. These challenges will also be detailed in this chapter.
Chapter 5 presents a few solutions at the circuit and architectural level to alleviate the impact of some of the challenges explained so far, in order to develop wide-bandwidth
DACs. This chapter also details a universal model for studying and specifying interleaved
DACs.
In order to obtain an overall picture of the efforts that have been put into pushing high-
11
resolution DACs into the GHz regime, a summary of recent innovations and developments are presented in chapter 6.
Having understood the notorious challenges in designing high accuracy and highbandwidth DACs, and realizing the need for high-frequency synthesis, it is clear that we need a radical change in the way we conceive and design DACs. Chapter 7 presents a bit-by-bit engineering model that stems from the contributions in chapter 2. This model provides the framework to analyze and appropriately manipulate the bits to enable highlinearity performance with low-resolution DACs, thus establishing the founding principles of a new field coined “compressive transmission”, a field never attempted before. The developed methodology, being highly fundamental, also holds great importance in the study of evolving timing-centric architectures, such as switched-mode RF power amplifiers, which are increasingly becoming attractive compared to analog power amplifiers,
Chapter 8 concludes this dissertation and provides insights into future developments.
12
Chapter 2
Digital-to-Analog Conversion
Digital-to-analog conversion has been investigated since the days of Shannon and Nyquist, and is today a fairly well-established field of research. Today, digital-to-analog converters are the lynchpin of every transmitter, at all levels of complexity. The initial portion of this chapter delves into the theory of D/A conversion as a process. The limitations of the process will be highlighted, followed by a description of specific performance metrics. The
D/A conversion process will be highlighted from a new perspective that enables the study of DACs in the presence of mismatches and their effects on the achievable performance numbers.
2.1 The Big Picture of Data Representation
Before we delve into the specifics of digital-to-analog conversion, let us take a step back
to see what the grand picture looks like. Shown in Fig. 2.1 is a checker board, that we
shall refer to as a quantizer grid, or simply the “grid”. On the bottom of the grid is the analog axis, bounded between 0 and 1. This analog domain can represent the normalized voltage or current or charge. The grid is composed of two colors, black and white. These colors individually represent the binary bits ‘0’ and ‘1’, respectively. The bottom row of the grid represents the most-significant bit (MSB) of the binary representation of the analog parameter. For instance, the MSB is ‘0’ for analog values less than 0.5 and ‘1’
13
for analog values greater than 0.5. The height of this row represents the binary weights associated with this bit. Similarly, the second row represents the second MSB, and its height is half of that of the MSB row, hence accounting for half the MSB weight. As we go up the rows, the row heights become exponentially smaller, and the last row represents the least significant bit (LSB). The granularity of quantization is represented by the width of the tiny boxes in the LSB row, and is referred to as the step-size of the quantizer, ∆ .
Figure 2.1: The Quantizer Grid
Let us now consider a signal that is fed into this quantizer grid, say 0.69. Assuming a 5-bit quantizer, the equivalent quantized representation will be 22
10 in decimal, or
10110
2
in binary. As observed from Fig. 2.2, a vertical line through the abscissa of
0.69 passes through the 22 nd box of the LSB row, directly indicating the equivalent decimal representation. Furthermore, as the same line passes through the various bit
14
rows, the colors that the line sees, correspond to the binary representation, read as MSB through LSB. The colors beneath the line are read out as white, black, white, white, black, or equivalently 10110! If the uppermost row (or the LSB row), were represented by a discretized equivalent of the continuous-analog scale, we obtain the equivalent output of a digital-to-analog converter. In this example, the equivalent 5-bit discretized analog value would be 22/32, or 0.6875.
Figure 2.2: The Quantizer Grid: Data representation
The significance of the quantizer grid lies in its capability to encompass both the ADC and DAC transfer characteristics simultaneously. The grid can also be used to explain ternary or even quaternary data representations that can be used in other forms of ADCs and DACs.
15
2.2 What is Digital-to-Analog Translation?
In reality, the digital-to-analog translation process involves the weighted summation of voltages, charges, or currents, where the effective weights are derived from digital input codes. A representative analog value, typically in the voltage domain, is then produced, where the full scale voltage ( V
F S
) is defined as the difference between the maximum
and minimum voltage levels. In the context of current-steering DACs
analog value is in the form of current, which is then converted to a voltage using a resistive load.
In the case of finite resolution, say an N -bit DAC, the input digital data can be described as having N binary input bits defined as:
B = { b
N − 1
, b
N − 2
, b
N − 3
, ..., b
1
, b
0
} (2.1) where b i
∈ { 0 , 1 } , b
N − 1 is the most significant bit (MSB), and b
0 is the least significant bit (LSB). In simple terms, this binary data word, B , is then converted to a corresponding decimal value, D , such that,
D =
N − 1
X
2 i b i
.
i =0
(2.2)
This weighted decimal value is then multiplied by a gain factor, such as V
LSB
(where
V
LSB
= V
F S
/ 2
N
) for voltage- or charge-based DACs and I
LSB
(where I
LSB
= I
F S
/ 2
N
) for current-steering DACs, to yield the final analog voltage (or current):
V
OU T
( D ) = D · V
LSB
I
OU T
( D ) = D · I
LSB
(2.3)
(2.4)
Let us consider a sinusoidal input to the grid, digitize it and equivalently represent it
4 to be explained in subsequent chapters
16
in a finite analog domain, as shown in Fig. 2.3. It must be noted that the bounds of the
signal have been made ± 1 , which make the binary bits +1 (‘1’) and -1 (‘0’). While the input signal is bounded within the quantizer limits, the quantizer output is limited to the minimum and maximum representable values. This figure clearly indicates how an infinite precision analog signal gets converted into a finite precision quantized signal. However,
Figure 2.3: A sinusoidal signal within the quantizer grid the equations and the grid discussed so far, have no notion of the time scale in which the quantizing operations are being performed. In real implementations, the order of time-scale is defined by a process called sampling and hold. Contrary to analog-to-digital converters (ADCs), where a signal is sampled by the system to yield digital samples, the
DAC is fed with a set of digital samples, x ( n ) , at fixed time intervals, ( T
CLK
) , defined by the sampling clock of the DAC ( f
CLK
= 1 /T
CLK
) . Assuming an ideal sampling process, the DAC is fed with data in the form of impulse trains. However, finite switching time in real circuits makes it impossible to generate such impulses. Instead, the input signal is supplied as square-wave pulses, i.e. a bit ‘1’ is represented as a pulse whose width is
T
CLK
. In such a scenario, a re-timing register is often needed to ensure that all digital input bits are aligned and synchronized to the sampling clock, f
CLK
. This process of square waveform generation through holding the input data for the duration of T
CLK
, is
17
known as the zero-order hold (ZOH).
The subsequent step involves the weighted translation from the digital to the analog domain. This step is intentionally referred as weighting, since the converter circuit assigns analog (i.e. current, voltage, or charge) weights corresponding to the digital input code.
The magnitude of these weights are set by the radix of the digital input code, i.e., the weights are in multiples of two for a binary code, and in multiples of one (in other words identical) for a thermometric code. After the digital bits are assigned appropriate weights, the weighted signals are summed up to yield a final discrete (stair-step) output, x
D
( t ) .
Fig. 2.4 illustrates these two primary functions of a 3-bit DAC.
Figure 2.4: Basic functions within a 3-bit digital-to-analog converter
2.3 Performance Metrics
The concept of D/A conversion is realized by means of voltage, charge or current mode processing. Several architectural conceptions (to be detailed in later chapters) exist that enable the realization and deployment of DACs. Just as any other real system, DACs also suffer from real-word imperfections, causing non-idealities in the D/A conversion process.In order to assess the quality of a D/A conversion, the performance of any given
18
DAC is quantified using a set of static and dynamic metrics. Static metrics quantify the behavior of the DAC based on its input-output DC transfer function; i.e. no frequency behavior is predicted nor estimated. Dynamic metrics, on the other hand, enable us to assess the DAC performance from a spectral point of view. The choice of metrics to be given importance, depends on the desired application ranging from high precision systems such as potentiometers and medical instrumentation to waveform synthesis in high-speed communication systems. This section briefly introduces the commonly used metrics to
characterize the DAC performance [14–17].
2.3.1 Static Metrics
Unlike the ADC’s stair-step transfer function, the DAC’s response is represented by discrete
points, which maps a specific digital input code to a discrete analog value
function of the real DAC and its comparison to an ideal transfer function are used to evaluate the static (i.e. near DC) performance metrics. Generating the transfer function plot from a real DAC is a straightforward process by simply applying a digital input code and observing the output using a high-precision voltmeter. For simplicity, the transfer
function of a real 3-bit DAC is overlaid on the ideal response as depicted in Fig. 2.5.
The DAC static performance metrics, including offset, gain, monotonicity, differential nonlinearity, and integral nonlinearity errors can be extracted from the transfer function plots.
Offset and Gain Errors
A typical DAC transfer function is depicted in Fig. 2.5(a).
The DAC’s offset and gain errors can be extracted from the transfer function using various methods. These include dividing the full scale voltage range by the number of quantization levels, using the end-points to generate a linear fit, or employing the best fit line. Owing to its simplicity, the end-point fit is the most preferred method to measure the DAC’s
5
The transfer function of a DAC can also be visualized as a one-dimensional curve, as noted in [18]
19
(a) (b)
(c) (d)
Figure 2.5: 3-bit DAC Transfer Function: (a) Offset error (b) Gain error (c) DNL (d) INL
offset [14]. The straightforward method to determine the DAC offset is by calculating
the deviation between the real and ideal transfer functions when the binary input is all
zeros. As illustrated in Fig. 2.5(a), the y-intercept of the transfer function denotes the
offset error. For target applications such as waveform synthesis, the DC offset can result in large carrier feed-through, when up-converted in an RF transmitter.
After removal of the offset, the gain error is extracted from the deviation of the slope of the extracted transfer function versus the slope of the ideal transfer function ( y = x ),
as depicted in Fig. 2.5(b) [17]. The gain error is seen as less critical, since it is often
20
calibrated out by adjusting the input digital code. It is worth noting that both offset and gain errors need to be removed before extracting any further static metrics such as differential or integral nonlinearities.
Differential Nonlinearity (DNL) The DNL error measures the step distance between the code i and the code i − 1 for the extracted DAC transfer function (after removal of
offset and gain errors), as illustrated in Fig. 2.5(c). The difference is then compared with
the ideal LSB value. The DNL for a given code i can be calculated as
DNL( i ) [LSB] = Code i
[LSB] − Code i − 1
[LSB] − 1 [LSB] (2.5)
For a given DAC, the minimum and maximum DNL values are typically reported to summarize its static performance. The DAC is considered monotonic when the output signal is increasing (decreasing) as the digital input code is increasing (decreasing). Monotonicity is guaranteed if the minimum value of the DNL is greater than -1 LSB.
Integral Nonlinearity (INL) The INL error can be quantified as the deviation of the
extracted DAC transfer curve to the end-point line, as depicted in Fig. 2.5(d). The INL
for a code i can be calculated from the DNL as
INL( i ) [LSB] = i
X
DNL( k ) [LSB] k =0
(2.6)
In order to summarize the INL performance of a DAC, the absolute maximum INL is reported.
2.3.2 Dynamic Metrics
The DAC’s dynamic performance is inferred from its output spectrum. The most often used metrics to characterize the DAC’s dynamic performance are NSD, SNR, SDR, SNDR,
ENOB, SFDR, and IMD. It is worth mentioning that all of these metrics are typically mea-
21
sured within the desired Nyquist band of operation. Most often, the achieved metrics are not quite impressive across the entire Nyquist band; in such cases, the effective bandwidth is reported alongside. A single-tone test is employed when measuring SNR, SDR, SNDR,
ENOB, and SFDR, while a two-tone test is used to characterize IMD. A behavioral simulation of a 12-bit DAC with intrinsic nonlinearity is used to illustrate the extraction of
Figure 2.6: Spectral plots for a 12-bit DAC
Noise Power Spectral Density (NSD) The power density of noise at the DAC’s output, as observed on a spectrum analyzer is referred to as the noise power spectral density, or the NSD. It is usually specified in dBm/Hz, and accounts for the contribution of the quantization noise and circuit-induced noise.
Signal-to-Noise Ratio (SNR) Signal-to-noise ratio is defined as the ratio of the desired signal power ( P sig) to the integrated noise power, excluding harmonics and DC offset. In
22
terms of the NSD, the SNR over a bandwidth, B , may be expressed as
SNR [dB] = 10 log
10
( P sig[dBm]
) − NSD [dBm/Hz] − 10 log
10
B [Hz] (2.7)
Typically, the measured noise power of an active (clocked) DAC, includes quantization noise ( N
Q
), DNL error ( N
DNL), thermal noise (
N thermal), and random jitter (
N j
), all specified over a bandwidth, B .
SNR [dB] = 10 log
10
P sig
N
Q
+ N
DNL
+ N thermal
+ N j
!
(2.8)
The SNR is generally specified over the entire Nyquist bandwidth. However, in some applications a narrow band filter is used following the DAC, and thus sets the integrated noise bandwidth well below its Nyquist. This process is otherwise known as oversampling and can effectively enhance the DAC resolution beyond its quantization limit.
Harmonic Distortion (HD n ) The n th order harmonic distortion is defined as the ratio between the power of the desired signal and the power of the n th harmonic, where n =
1 , 2 , 3 , ...
, and expressed as,
HD n
[dBc] = 10 log
10
P sig n th Harmonic Power
!
(2.9)
When generating a single output tone at f
0
, the n th harmonic component is observed at the | nf
0
± kf
CLK
| frequency where k is chosen to fold the harmonic term into the desired
Nyquist zone.
Signal-to-Noise-and-Distortion Ratio (SNDR) Signal-to-noise-and-distortion ratio measures the ratio of the power of the desired signal to the power of the total noise, including harmonic distortion products ( P dist). The measurement does not include the
23
DC component.
SNDR [dB] = 10 log
10
P sig
N
Q
+ N
DNL
+ N thermal
+ N j
+ P dist
!
(2.10)
Effective Number of Bits (ENOB) ENOB is used to represent the effective resolution of the converter including all sources of noise and/or distortion. ENOB can be calculated from either SNR or SNDR and is represented as
ENOB [bits] =
( SNR or SNDR, [dB] − 1 .
76)
6 .
02
(2.11)
Spurious-Free Dynamic Range (SFDR) Spurious-free dynamic range measures the relative power of the desired signal to the power of the highest spur component generated
within the targeted bandwidth.
SFDR [dBc] = 10 log
10
P sig
Highest Spur Power
!
(2.12)
This metric is considered the most critical in frequency synthesis since it determines the spectral purity of the output waveform with or without the presence of harmonics.
Intermodulation Distortion (IMD n ) In the presence of two or more input signals, inter-tone harmonic mixing can result in intermodulation distortion (IMD) products, located close to or further apart from the desired signals. IMD n measures the power of the n th -order intermodulation product ( P imd n
) , relative to the power of the desired signals
( P sig
) . The IMD products for two signals at f
01 and f
02 can span across | ( mf
01
± nf
02
) | where m, n = 1 , 2 , 3 , ...
Furthermore, the DAC sampling and aliasing processes can result in the folding of the IMD products to multiple Nyquist zones, which can be expressed as
6
Care should be taken in choosing appropriate FFT resolution bandwidth (or bin spacing) to set the minimum detectable power level.
24
| ( mf
01
± nf
02
) ± kf
CLK
| , where m, n, k = 1 , 2 , 3 , ...
IMD n
= 10 log
10
P sig
P imd n
!
(2.13)
In general, the third order intermodulation ( IM D
3
) is of most concern, as it generates the highest in-band distortion levels.
2.3.3 Influence of static metrics on the dynamic metrics - INL
Induced Distortion
Even though the previously described metrics can be divided into static and dynamic categories, their effects are not entirely independent. For instance, there is a clear link between the DAC static INL performance and its low-frequency distortion behavior. A high INL error represents a large deviation of the DAC transfer curve from the straight line
( y = x
). This places an upper bound on SFDR at frequencies near DC [17, 19]. Thus,
the INL can provide an estimate of the maximum SFDR before further degradation due
to timing- and amplitude-related errors [14].
Continuing with the example of a 12-bit, 250 MS/s DAC, we estimate the prominent harmonic distortion order and its magnitude from the shape and maximum value of the
INL, respectively. Expanding on the works of [17] and [19], the INL is modeled using
correlated second- and third-order polynomials, as noted in Fig. 2.7. However, it is
important to realize that this approach over-simplifies the problem, by replacing the hard non-linearity curves with a soft non-linearity approach. The second-order model is defined as y = a · x
2
+ x − a, (2.14) while the third-order model is expressed as y = b · x
3
+ (1 − b ) · x.
25
(2.15)
In the above equations, a and b are chosen such that the maximum INL is set to be equal to INL
M AX
. Fig. 2.7 illustrates the second- and third-order INL curves and their
respective spectra with INL
M AX
= 0.5, 1, and 2 LSB. For each example of INL, the magnitudes of HD2 and HD3 are comparable. From the analyses of these two models, a heuristic approximation for SFDR as a function of the maximum INL can be expressed as
SFDR [dBc] = 20 log
10
2
N
INL
M AX
(2.16)
Figure 2.7: Static INL shaping and the resulting effects on power spectral density
2.4 Implementation of DACs
The most straightforward implementation of the DAC involves an array of binary-weighted passive (capacitors and/or resistors) or active (current sources) components. Assuming a binary-weighted current-steering DAC with an LSB current of I
LSB
, and denoting b
as the i th binary bit of a digital code, the output of the N -bit binary-weighted DAC can be
7 b i takes discrete values of 0 or 1 and referred in little-endian format.
26
expressed as
I
OU T
= I
LSB
N − 1
X
2 i b i i =0
(2.17)
Alternatively, in a unary-weighted DAC, the current sources are all equal in magnitude;
Thus, an N -bit DAC comprises 2 N − 1 unary current sources. Denoting t
as the i th thermometer bit of a digital word, the effective analog current in response to the digital thermometer code is expressed as
I
OU T
= I
LSB
2
N
− 2
X t i i =0
(2.18)
Both the aforementioned architectures have their advantages and disadvantages. The binary architecture carries the benefit of using fewer control signals than the unary architecture. However, the accuracy requirements of the MSB cell versus LSB cell increases exponentially with the resolution. This results in the potential to exhibit code-transition glitches and loss of monotonic behavior. Such nonidealities can be mitigated by the unary architecture at the expense of increased chip area. A compromise between the two architectures is often made by segmenting the DAC, i.e. the MSBs and LSBs are represented by unary and binary structures, respectively. For an N -bit DAC segmented as k : m , such that the first k bits (MSBs) are realized as a unary structure, and the lower m bits are represented in binary, the effective analog output current is given by
I
OU T
= I
LSB m − 1
X
2 i b i
+ 2 m
I
LSB
2 k
− 2
X t i i =0 i =0
(2.19)
For instance, a 12-bit DAC built using a 9-bit thermometer array and a 3-bit binary array is said to be 75% segmented. The unary and binary architectures are two extreme cases of segmentation: a unary-weighted DAC is referred to as 100% segmentation, while an all-binary DAC is 0% segmented.
8 t i takes discrete values of 0 or 1 and referred in little-endian format.
27
2.5 High-Speed DACs: The current-steering architecture
A majority of high-speed DACs use the current-steering (CS) architecture, which offers faster switching and wider bandwidths compared to voltage- or charge-based DACs. This is primarily because the active devices are well known to switch faster in current than in voltage mode. More important, the transistor is inherently a current-mode device. In addition, attempts to linearize the output buffer amplifier in voltage and/or charge mode
DACs using feedback techniques, limit their speed of operation. This can be contrasted with using a simple load resistor in CS DACs.
Figure 2.8: A segmented current-steering DAC architecture
An illustration of the current-steering architecture on a high-level abstraction is seen
in Fig. 2.8. The DAC core comprises an array of binary and/or unary weighted current
sources. The binary-switched current source array is scaled in units of 2 k × I
LSB
, where k =
0 , 1 , 2 , ..., ( N − m − 1) for an N -bit DAC segmented with m thermometer bits. The unary
28
current source array, which is only used in thermometer or segmented DAC architectures, comprises 2 m − 1 current sources, each of magnitude 2 N − m × I
LSB
. A corresponding array of current-commutating switch-pairs steer the direction of the current into one of the
of the DAC’s output based on the input digital code. The switching pair cells can also be used to implement various hold operations at the output. Two load resistors, are used to convert the DAC’s differential output current to a voltage signal
(I-to-V). A binary-to-thermometer encoder maps the m most significant binary bits to a thermometer code that feeds the unary current source array.
A key observation here is that the output swing of the DAC is set by the full-scale
DAC current and the load resistor. Denoting the full-scale DAC current as I
F S
, and load resistor as R
L
, the differential DAC swing is expressed as 2 I
F S
R
L
. Thus, a large load resistor implies a huge swing or large output power.
2.6 State-of-the-art in DACs
The development of wideband communication and RADAR systems, and the use of directdigital synthesis (DDS) have motivated the need for high-linearity high-speed DACs. Such applications require DACs operating well above 100 MS/s and a 25 - 300 Ω resistive load.
Fig. 2.9 illustrates the achieved spurious-free dynamic range (SFDR) of state-of-the-art
current-steering DACs. This plot specifically denotes the SFDR achieved across the entire
Nyquist band. Much of the degradation in SFDR is said to be caused by static and
dynamic non-idealities [18]. Furthermore, a steep fall in SFDR is observed as sampling
frequency increases. At 100 MHz of sampling speed, the Nyquist SFDR is hardly 80 dB. The high f
T of BiCMOS or bipolar technologies like GaAs, InP and SiGe, compared to CMOS technology enables higher sampling speeds.
As a result, BiCMOS designs dominate at high sampling speeds. However, the SFDR is still limited to about 50 dBc
9 Some books also use the term ‘arm’ as an equivalent to ‘leg’.
29
Figure 2.9: State-of-the-art DACs: Achieved SFDR across the Nyquist band vs. sampling speed, for various technologies.
at 20 GS/s (or 10 GHz of bandwidth). It is important to realize the sources and reasons for such limitations in SFDR, in order to develop efficient design solutions or calibration methodologies to circumvent them.
30
Chapter 3
Fundamental Limitations in DACs
Having discussed the basic conception of a DAC, we shall proceed to study the detrimental effects of the D/A conversion process. In general, DACs are known to suffer from three inherent limitations: (1) quantization or truncation error, (2) image replicas, and (3) hold
distortion, collectively illustrated in Fig. 3.1 [14–17]. While these limitations are observed
at the output of a DAC, not all of them are generated by the DAC. The following section shall delve into the generation of each of these issues in detail.
3.1 Sampling and Hold Operation
The instantaneous jumps in analog levels of the resultant stair-step waveform that occur every sampling interval, indicate that the signal comprises a wide bandwidth. In order to envision this, let us denote the desired signal as x ( t ) and the sampled signal as x ( n ) .
In order to simplify the math, let us make an important assumption of having infinite amplitude resolution when obtaining x ( n ) , i.e. quantization is neglected. This assumption is justified because sampling and quantization are orthogonal to each other, as detailed
x [ n ] = x ( t ) δ ( t − nT
CLK
) (3.1)
31
Figure 3.1: Fundamental limitations in an ideal DAC
Let X ( j Ω) denote the continuous-time fourier transform (CTFT) of x ( t ) . Hence, the discrete-time fourier transform (DTFT) of x [ n ] may be defined as
X ( e jω
) =
=
X
1
( j Ω)
ω
Ω = k =+ ∞
X
X j
T
T k = −∞
−
2 πk
T
ω
T
−
2 πk
T
∀ k ∈ Z
∀ k ∈ Z (3.2)
Equation (3.2) indicates the generation of alias components of the original signal, occur-
ring at periodic intervals of 2 π/T . It is worth noting that these alias components are generated from the fundamental nature of sampling, and have nothing to do with the
D/A operation.
In order to express the effects of the hold operation, let us denote the the CTFT of the zero-order hold rectangle function of pulse-width, T
CLK
, as
P
ZOH
( j Ω) = sin (
Ω T
CLK
2
Ω T
CLK
2
) e
− j
Ω TCLK
2
(3.3) it is important to remind the reader that the signal x ( n ) is considered to be an infinite resolution signal, i.e. no quantization has been performed. Moreover, x ( n ) is treated as a composite of all its bits; hence, the weighting process simply translates to a gain. Thus,
32
the CTFT of the output may be written as,
X
D
( j Ω) = T
CLK
X ( e jω
)
ω =Ω T
CLK
.P
ZOH
( j Ω) (3.4) which simplifies to,
X
D
( j Ω) = l =+ ∞
X
X j Ω −
2 πl
T l = −∞ sin (
Ω T
CLK
2
Ω T
CLK
2
) e
− j
Ω TCLK
2
(3.5)
This suggests that when a DAC clocked at f
CLK is used to synthesize a sinusoidal signal at f
0
, it results in image replicas to be generated at f
CLK
± f
0
, 2 f
CLK
± f
0
,
3 f
CLK
± f
0 and so on. A reconstruction filter, also known as the image-reject filter, is typically an external component that smoothens this stair-step waveform and thus eliminate out-of-band frequency components. For signals generated at baseband, a lowpass filter is designed to eliminate frequencies greater than the Nyquist bandwidth (DC to f
CLK
/ 2 ). Furthermore, the sinc nature of the rectangular hold, P
ZOH
( j Ω) , results in attenuation at higher frequencies and nulls at every other f
CLK
. The attenuation results in distortion when synthesizing multi-tone or wide-bandwidth signals, while the nulls restrict the DAC from being capable of generating a signal at multiples of f
CLK
. Interestingly, when the desired signal f
0 moves near f
CLK
/ 2 , its sampling image replica also moves closer to f
CLK
/ 2 and is of comparable magnitude. This places stringent requirements on the order and quality of the image-reject filter. Furthermore, the exponential term in
(3.5), contributes a frequency-dependent linear phase-shift. This is equivalent to a fixed
latency of T
CLK
/ 2 from the onset of sampling to the holding action. In reality, DACs have additional delays due to multiple re-timing stages in its implementation.
The primary take-aways of this discussion are:
• Replicas in DACs are equivalent to aliases in ADCs. They appear at the DAC output, because of their inherent presence in the time-sampled digital data, and are not generated by the DAC itself.
33
• The ZOH results in amplitude distortion or attenuation at high frequencies.
• The fundamental operation of the infinite resolution D/A conversion results in a fixed latency or a constant group delay.
3.2 Finite Quantization
Quantization error is attributed to the finite resolution of the DAC and is inherent in any ADC or DAC. To be specific, quantization noise is created by the quantizing process within the ADC or the finite word-length of digital signal processing (DSP), i.e. finite precision. The DAC does not create the quantization noise; instead, quantization noise is treated as an additive input to the DAC. The nature of its treatment has been the subject of research for a very long time. Critical properties of quantization error, such as their spectral and stochastic characteristics, reveal that the quantization error is manifested
as a white noise floor [20, 22]. To visualize the effect of the quantization noise, let us
neglect sampling, i.e. there is no discretization in time. Let the desired analog value of x is represented by a quantized value x
Q
. Let the quantization error be expressed as e
Q
( x ) .
Denoting Q
N
( .
) to be the N -bit quantizing operation, x
Q
( t ) = Q
N
( x ( t )) = x ( t ) + e
Q
( x ( t )) (3.6) where, e
Q
( x ( t )) is the time-domain representation of the error between the actual signal and its quantized version. The Q
N
( .
) function, also referred to as the desired-to-quantized
(D2Q) signal transfer function, is assumed to be a mid-rise quantizer, as shown in Fig.
3.2(a). The X-axis is a continuous analog domain, while the Y-axis is a quantized or
discretized analog domain.
The Y-axis is specified by two fundamental metrics: (1) resolution, N , and (2) step size, ∆ . Together, they set the full-scale range at the output of the quantizer, which is expressed as 2 N ∆ . For the chosen transfer function, the error as a function of the input signal takes the form of a sawtooth wave, as depicted in Fig.
34
(a) (b)
Figure 3.2: A mid-rise Quantizer (a) Transfer function (b) Quantization error
3.2(b). Generally, the error signal for the
N -bit quantizer is bounded between ± ∆ / 2 .
The shape and bounds of the error waveform is the same even for a mid-tread quantizer.
Let us first consider a band-limited Gaussian signal. If the samples of this continuous function are random and statistically independent of each other, the process may be described as a first-order probability density function, W ( x ) . Its characteristic function,
W
U
( u ) is given by its Fourier transform and expressed as,
W
X
( u ) =
Z
∞
−∞
W ( x ) exp( − jxu ) dx (3.7)
While the quantizer input can take continuous values, the output of the quantizer can take only discrete values. Thus, the probability density function of the quantizer output,
W
Q
( x
Q
) , comprises a series of impulses that are uniformly spaced along the amplitude axis, with each one centered in a quantization box. The distributions of the input and
output of the quantizer described so far, is shown in Fig. 3.3. Any event occurring
within a quantization interval is always hard-limited to the center of that box. Thus, the amplitude of the impulse is equal to the area bounded by the quantization box under the
35
curve, W ( x ) . In other words, the probability of a quantized signal to be at a certain level is equal to the total probability of the input taking values within the corresponding quantization box.
Figure 3.3: Density distributions for the input and output of the quantizer
If D ( x ) is the cumulative distribution function of W ( x ) , then W
Q
( x
Q
) can be constructed by sampling the difference between D ( x + ∆ / 2) and D ( x − ∆ / 2) , as illustrated
in Fig. 3.4. This process of obtaining
D ( x ) and operating on its successive differences
can be represented as a block diagram, as depicted in Fig. 3.5. The advance and delay
blocks that operate on D ( x ) are represented by exponential functions of u . This block diagram enables us to visualize W
X
( u ) to be shaped by a linear “filter”, whose transfer function is given by,
H ( u ) = exp( ju ∆ / 2) − exp( − ju ∆ / 2)
= ju sin(∆ u/ 2)
∆ u/ 2
(3.8) which is then area sampled to obtain W
Q
( x
Q
) . This concept of area sampling may be perceived similar to the Nyquist sampling theorem in time, such that the granularity of samples is finer than the highest ‘frequency’ component in the shape of W ( x
10 Frequency here refers to how frequent W ( x ) changes with x
36
the characteristic function of the quantized output is given by
W
Q
( u ) = | W
X
( u ) H ( u ) |
Area − sampled
= W
X
( u ) sin(∆ u/ 2)
∆ u/ 2
Area − sampled
(3.9)
Similar to sampling in time, area sampling with sufficient granularity results in spectral repetition of the scaled W ( x ) at radian multiples of 1 / ∆ . However the fine granularity in area sampling results in no overlap in these spectral copies. As a result, it is possible to recover W ( x ) from the quantized distribution W
Q
( x
Q
)
of two factors and is also a characteristic function by itself. It is also well known that the characteristic function of a sum of two variables is the product of their individual charac-
teristic functions. On comparing equations (3.6) and (3.9), the characteristic function of
the quantization error can be found to be
W e
Q
( u ) = H ( u ) = sin(∆ u/ 2)
|
Area − sampled
∆ u/ 2
(3.10)
The corresponding density function, obtained by an inverse Fourier transform and illus-
trated in Fig. 3.6, is given by
W e
Q
( x ) =
1
∆
, − ∆ / 2 < x < ∆ / 2 (3.11)
Statistical properties of the distribution indicate that the quantization error is zero mean with a variance of ∆ 2 / 12 . Thus, the quantization error is zero mean, additive, and gaussian in nature.
For a random signal with gaussian properties, the quantization error is also Gaussian with its samples being independently and identically distributed (i.i.d). The independence between the samples of the error suggests that there exists no correlation, or in other words, a white spectrum. This whiteness is key to simplifying the analysis of Nyquist quantizers and in the development of noise-shaping quantizers. Together with sampling
37
Figure 3.4: Illustration of the process of obtaining the density distribution of W
Q
( x
Q
) at f
CLK
, the quantization error is distributed between 0 to f
CLK
/ 2 with a power of
∆ 2 / 12 . The choice of ∆ thus dictates the noise floor at the output of the quantizer.
For a quantized sinusoidal signal whose peak-to-peak swing equals a known fraction
(say α ) of the full-scale range ( 2 N ∆ ), the signal power is expressed as,
Signal Power =
( αF SR/ 2)
2
2
= α
2
2
2 N
∆
2
8
(3.12)
38
Figure 3.5: Block diagram of the area sampling
Figure 3.6: Probability density distribution of quantization error (noise)
The signal-to-noise ratio (SNR) is expressed as,
Signal Power
SNR =
Noise Power in the Nyquist bandwidth (0 to f
CLK
/ 2 )
SNR
=
=
α
2
2
2 N
8
∆
2
∆ 2
12
3
2
.
2
2 N
α
2
(3.13)
SNR (in dB) = 1 .
76 + 6 .
02 N + 20 log
10
( α ) (3.14)
Thus, the SNR increases by 6 dB for every additional bit. The maximum value of α can never exceed 1. For a quantizer output of -3 dBFS (half of the full-scale range or equivalently α = 0 .
5 ), only half the total number of levels are contained in the output.
39
This is equivalent to a quantizer of N − 1 bits. Hence, it is important to realize that the total SNR achieved at the quantizer output is also a function of the number of codes exercised to produce an output signal. In noise-limited applications, the desired noise floor and system bandwidth together set the minimum resolution required for the quantizer.
Key take-aways of this discussion are:
• Quantization noise is attributed to the notion of finite resolution. It is generated by the quantizer (ADC) and not within the DAC. Stated otherwise, quantization noise is treated as an input to the DAC.
• Quantization error is treated as additive noise
• Quantization error is uniformly distributed within ± ∆ / 2
• Successive samples of the quantization error, when uncorrelated, imply that it is white in nature. However, this is true only for coarsely-sampled signals
• The total quantization noise power is ∆
2
/ 12 . For a sampled signal, this is distributed as white noise between 0 to f
CLK
/ 2 .
• The quantization noise power in the Nyquist bandwidth decreases by 6 dB for every additional bit, or the SNR improves by 6 dB per bit
• The SNR of a quantizer is at its maximum of 1 .
76 + 6 .
02 N , when the codes are excited as full-scale at the output.
3.3 Spurious limitations of a DAC
When a continuous-time continuous-amplitude signal is fed to the quantizer (analog-todigital-to-analog conversion), the output waveform comprises instantaneous jumps between discretized amplitude levels. From a spectral view, these instantaneous code-jumps
40
imply that the quantized signal comprises a very wide bandwidth. In other words, the quantization of a single-tone sinusoid results in infinite tones of varying magnitudes. Since, the synthesis of the fundamental signal is of most interest, all other tones are considered as spurs, or more appropriately quantization spurs. While several non-idealities can manifest
as spurs 11 , these quantization spurs limit the highest achievable signal-to-distortion ratio
in a DAC. Nevertheless, it is important to realize the ultimate achievable performance numbers. This section provides a fresh look at the location and magnitude of every component in the output spectrum of an ideal DAC.
Let us consider the DAC exhibiting characteristics similar to the one shown in Fig.
3.2(a). The X-axis is a continuous analog domain that represents the signal levels that
are desired, while the Y-axis is a quantized or discretized analog domain representing signal levels that are permissible at the output of a DAC. Specifically, we shall assume that the signals on the X- and Y-axes are bounded between ± F SR/ 2 , where FSR represents the full-scale range. For an N -bit DAC, the quantization levels are separated by ∆
N
=
F SR/ 2
N
. Following equation (3.6), the stair-step DAC output is expressed as,
y ( t ) = Q
N
( x ( t )) = x ( t ) + e
N
( x ( t )) (3.15) where x ( t ) is the desired signal and e
N
( .
) represents the quantization error for the N bit DAC. The quantization error exhibits a sawtooth relationship with respect to x , as
depicted in Fig. 3.2(b) and can be expressed as a Fourier series as,
e
N
( x ( t )) = ∆
N n = ∞
X nπ n =1
1 sin
2 πnx ( t )
∆
N
Thus, the output of the DAC may be written as, y ( t ) = Q
N
( x ( t )) = x ( t ) + ∆
N n = ∞
X nπ n =1
1 sin
11 These will be discussed in subsequent chapters
2 πnx ( t )
∆
N
(3.16)
(3.17)
41
For a full-scale sinusoidal input, i.e. peak-to-peak swing equals FSR, x ( t ) =
F SR sin( ωt )
2
(3.18)
Therefore, y ( t ) =
F SR sin( ωt ) + ∆
N
2 n = ∞
X n =1
1 nπ sin
2 πn
F SR
2
∆
N sin( ωt )
!
Assuming that the signal is bounded between ± 1 , i.e. FSR = 2, y ( t ) = sin( ωt ) +
2
2 N π n = ∞
X
1 n sin 2
N
πn sin( ωt ) n =1
Substituting α = 2 N nπ , y ( t ) = sin( ωt ) +
2
2 N π n = ∞
X
1 n sin ( α sin( ωt )) n =1
Using the Jacobi-Anger expansion,
(3.19)
(3.20)
(3.21) sin ( α sin( ωt )) = 2 k = ∞
X
J
2 k +1
( α ) sin ((2 k + 1) ωt ) k =0
(3.22) where J k
( α ) is the Bessel function of the first kind, with order k and argument α . Thus, the quantized signal can be expressed as,
2 y ( t ) = sin( ωt ) +
2 N π n = ∞
X n =1
2 n k = ∞
X
J
2 k +1
( α ) sin ((2 k + 1) ωt ) k =0
4
= sin( ωt ) +
2 N π k = ∞
X sin ((2 k + 1) ωt ) n = ∞
X
J
2 k +1
( α ) n k =0 n =1
(3.23)
(3.24)
The significance of the above equation lies in the fact that the process of quantization upon a single-tone sinusoid results in the generation of odd harmonics of the fundamental signal. Stated otherwise, the process of quantization does not result in the generation of even harmonics. Moreover, the power of the generated harmonics is a function of the resolution of the DAC, N . The powers of the various tones are derived as follows:
42
The effective amplitude of the fundamental tone at the output of the quantizer is given by
A
1
4
= 1 +
2 N π n = ∞
X
J
1
( α ) n n =1
(3.25)
It should also be noted that the quantization error contributes to a summation of Bessel functions, whose effective sum is a negative number. In other words, the quantization error comprises a fundamental term which is lesser in magnitude and out-of-phase with respect to the signal. This term reduces the effective power of the fundamental tone that is generated at the output of the quantizer (DAC). To be precise, representation of the signal by a single bit results in a loss of 3.9 dB of power. A similar result was also
obtained by the authors in [21] and [23]. Stated otherwise, the MSB or signed bit weighs
one-half of the signal level, but contains only 40.7% of the total signal power. However, with increasing resolution, or the addition of more LSBs, the magnitude of the summation term decreases, and hence the power of the fundamental signal increases, as depicted in
Figure 3.7: Effect of resolution on the power of the fundamental
43
On the other hand, the amplitude of the odd harmonics are given by
A k
| k is odd
=
4
2 N π n = ∞
X
J k
( α ) n n =1
(3.26)
Fig. 3.8 illustrates the harmonic levels of the quantized signal,
y ( t ) , as a function of the
Figure 3.8: Effect of resolution on the levels of the harmonics quantizing resolution, N . The third harmonic ( k = 3 ) is observed to be the highest in magnitude. For higher resolutions, the amplitude (and therefore power) of the harmonics decrease continuously. The signal-to-distortion ratio (SDR) of a quantizer is expressed as the ratio of the power of the fundamental to the power of the highest harmonic (i.e. the
third harmonic), as observed at the output. Using equations (3.25) and (3.26), the SDR
44
of an N -bit quantizer is expressed as,
SDR
N
=
1 +
4 n = ∞
X
J
1
( α )
4
2 N π n =1 n = ∞
X n
J
3
( α )
2 N π n =1 n
2
(3.27)
SDR matches extremely well with (3.27).
Figure 3.9: Effect of resolution on signal-to-distortion ratio (SDR)
45
3.3.1 Derivation of 9 dB/bit trend
Given that the quantizer operates on a continuous-time domain, and from observations in
N . Hence, the expression for SDR can be approximated as,
2
SDR
N
2
N
π
4 n = ∞
X
1
J
3
( α )
n
n =1
In dB scale, this reduces to
SDR
N
[dB] = 20 log
10
2 N π
4
− 20 log
10 n = ∞
X
J
3
(2 N nπ )
!
n n =1
This may be rewritten as,
(3.28)
(3.29)
SDR
N
[dB]
∼
.
02 N − 2 .
098 − 20 log
10 n = ∞
X
J
3
(2
N nπ )
!
n n =1
(3.30)
The logarithm of the summation term can be numerically fitted to a straight line to obtain the overall SDR as,
SDR
N
[dB]
∼
.
02 N − 2 .
098 + 2 .
95 N + 2 .
2
SDR
N
[dB]
∼
.
1 + 8 .
97 N
(3.31)
(3.32)
This suggests that for every additional bit, the SDR at the “output” of the quantizer improves by roughly 9 dB. Key take-aways of this discussion are:
• The process of quantization inherently introduces distortion. Specifically, it results in the generation of odd harmonics only.
•
The third harmonic is the dominant harmonic of all, as observed from Fig. 3.8;
46
hence dominates the overall SDR.
•
The SDR improves by 9 dB for every additional bit, as observed from Fig. 3.9.
3.3.2 Effect of sampling on the achieved SDR
While there exists a 9 dB/bit trend in SDR for signals in the continuous-time domains, i.e. infinite sampling resolution, the finite sampling in time can result in the achievable
SDR to deviate from this trend. Fig. 3.10 illustrates the amount of deviation in SDR
when synthesizing a single-frequency sinusoid across the Nyquist band. In particular, the
SDR degrades when the synthesis frequency approaches f
CLK
/ 2 . Such a degradation is attributed to the folding of harmonic spurs into the Nyquist zone. For lower frequencies, very high-order harmonics that are of extremely low amplitudes fold back. In the case of near-Nyquist frequencies, the harmonics as low as the fifth, can fold back. Depending upon the choice of the signal frequency relative to the sampling frequency, the out-ofband harmonics can fold back over the signal or in-band harmonics, effectively increasing or decreasing the effective power. As a result, a higher degradation is observed for signals
close to Nyquist, as depicted in Fig. 3.11.
Nevertheless, the concept of prime sampling (common in the domain of ADCs) is beneficial in obtaining unique samples of the signal. Prime sampling is referred to as the situation when the signal frequency and the sampling frequency exhibit the relationship, f sig f
CLK
= p
, p = mq, p, m, q ∈ Z q
(3.33)
This is visualized in the time-domain as folding of the out-of-band harmonics into the inband, without disturbing the powers of the in-band signal and harmonics; i.e. the prime sampling guarantees that the out-of-band spur never folds onto the signal or any other harmonic. In such scenarios, there exists no degradation in SDR, as observed from Fig.
3.12. Thus, an arbitrary choice of sampling frequency can indicate poor SDR, while the
47
Figure 3.10: Deviation in SDR for various resolutions
DAC is capable of providing significantly superior performance. This further emphasizes the importance of the choice of sampling frequency relative to the signal frequency, while testing the DAC.
Furthermore, it is observed from Fig. 3.11 and Fig. 3.12, that there exists a lower band
of frequencies, which suffer no distortion, irrespective of the choice of sampling frequency.
This frequency limit is applicable to both ADCs and DACs and will be elaborated in detail
3.4 Two-tone analysis
Two-tone tests are widely used as a standardized procedure to evaluate the linearity of a system. When two tones of equal amplitudes are fed into a system, the system nonlinearity results in the generation of intermodulation products. Unfortunately, for closely-spaced
48
Figure 3.11: SDR as a function of frequency: Non-prime sampling tones, the odd-order intermodulation products lie around the signal frequencies, resulting in in-band distortion; or in other words, in-band spectral regrowth. This is highly detrimental to systems that deal with wideband signals. While the process of generation of intermodulation products is well studied in the literature, it is interesting to see how they are generated in quantizers.
Let us consider a two-tone input signal, x =
1
2 sin( ω
1 t ) +
1
2 sin( ω
2 t ) (3.34)
The factor of half guarantees that the signal is bounded between ± 1 . Considering the same quantizer as before, the output of the quantizer may be expressed as y = x + Im
( n = ∞
X
∆
N nπ n =1 exp j
2 nπx
∆
N
)
(3.35)
49
Figure 3.12: SDR as a function of frequency: Prime sampling
Thus, for the two-tone signal, we obtain y =
1 sin( ω
1 t ) +
2
Im
( n = ∞
X
∆
N nπ n =1
1
2 sin( ω exp j
2 t ) +
2 nπ sin(
2∆
N
ω
1 t ) exp j
2 nπ sin( ω
2 t )
2∆
N
)
(3.36)
At this juncture, it is useful to reduce the above equation by using the exponential form of the Jacobi-Anger expansion, exp ( jα sin( ωt )) = n = ∞
X
J n
( α ) exp( inωt ) n = −∞
(3.37)
50
y =
1
2
Im sin( ω
1
( n = ∞
X n =1 t ) +
∆
N nπ
1 sin( ω
2
2 p = ∞ t ) +
X nπ
J p
2∆
N p = −∞ e jpω
1 t q = ∞
X
J q q = −∞ nπ
2∆
N e jqω
2 t
)
(3.38)
Using the above expression, the amplitudes of the intermodulation products at pω
1
+ qω
2 can be computed by appropriately substituting the values for p and q . The third-order intermodulation products are designated by p = 2 , q = − 1 and p = − 1 , q = 2 , and their levels w.r.t to the signal can be expressed as
IM
3
=
1
∞
X
+
2
∞
X n =1
∆
N nπ
J
2 nπ
∆
N n =1
J
1 nπ nπ
2∆
2∆
N
N
J
− 1
J
0 nπ
2∆ nπ
2∆
N
N
(3.39)
Fig. 3.13 illustrates the signal-to-IM3 level as a function of resolution - roughly 12 dB/bit
improvement is clearly seen. However, similar to the SDR, this trend holds good only when the frequencies are very low compared to the sampling frequency.
Note As noted so far, the signal-to-IM3 level is higher than the signal-to-HD3 ratio in a data converter. In contrast, nonlinearity in amplifiers causes the signal-to-IM3 level to be lower than the signal-to-HD3 ratio. This suggests that data converters cannot be treated by a soft non-linearity model, as in the case of amplifiers. The analyses developed in this chapter do not make any assumptions and strictly models the quantizing phenomena to yield exact bounds on the distortion limits in a DAC.
51
Figure 3.13: Signal-to-third-order-intermod level improves with resolution, by roughly 12 dB/bit.
52
Chapter 4
Practical Challenges in DACs
The concept of D/A conversion is realized by means of voltage, charge or current mode processing. Several architectural conceptions exist that enable the realization and deployment of DACs.
Just as any other real system, DACs also suffer from real-word imperfections, that manifest on top of the fundamental noise and spurious limitations, discussed so far. Specifically, these non-idealities can be lumped into two broad categories: timing-related errors and amplitude-related errors. While not seen as independent, each of the two categories can be further classified into static and dynamic errors. In simple terms, static refers to time-invariant errors that are induced by random or systematic mismatch effects. In contrast, dynamic refers to time-variant errors that can
be attributed to code-dependent 12
transitions, jitter, glitches, and impedance variation.
Fig. 4.1 illustrates the four categories of error – static and dynamic timing, as well as
static and dynamic amplitude errors.
Examples of static timing errors (Fig. 4.1(a)) can be observed in delay mismatches
amongst retiming flip-flops, clock skew between DAC circuit blocks, and delays attributed to switching pair mismatches. On the other hand, dynamic timing error includes both random and deterministic clock jitter or phase noise. Similar to quantization noise, random jitter can increase the DAC’s noise floor, while deterministic jitter is manifested as spurs
12 Code-dependency is equivalently mentioned as signal dependency, where signal refers to the desired output waveform.
53
(a)
(b)
Figure 4.1: (a) Static and dynamic timing errors (b) Static and dynamic amplitude errors
in the DAC’s output spectrum. Examples of amplitude-related errors are illustrated in
Fig. 4.1(b). The relative mismatch between the weighted current sources can induce static
amplitude errors in the form of differential and integral nonlinearities as well as offset error.
54
Whereas dynamic errors caused by large code transitions, parasitic loading, finite slewing, and finite settling times, further degrade the output amplitude accuracy. Timing-related errors can also be induced concurrently with amplitude-related errors resulting in varying settling times, slewing rates, and glitches.
Having described the severity of these non-idealities, let us proceed with analyzing the source of these challenges. In simple terms, non-idealities can occur due to device limitations or at the architectural level. The device-related non-idealities will be called micro-level challenges, while the system level limitations will be referred to as macro-level challenges; These will be the focus of the remainder of this chapter.
4.1 The current-steering cell
As noted earlier, the current-steering architecture comprises an array of switched current
cells, as shown in Fig. 4.2. In reality, the current source is replaced by a bias transistor.
The sourced current is steered to the positive or negative output leg in response to the input differential data signals, D and
¯
, by means of a commutating switch pair. The size of the switch pair is scaled with the magnitude of the current, in order to maintain the
same source node voltages across all current cells 13 . The differential switching architecture
is implemented owing to its benefit of immunity against noise from both the digital and analog supplies. Thus, a basic DAC current cell comprises at least three transistors. With the notion of high speeds in mind, let us examine the limitations of each component in the current-steering cell.
4.2 Challenges at the Micro-level
In general, scaling of transistors, interconnect dimensions and power supply are quite favorable for digital designs. However, such trends are not entirely beneficial to analog
13 This is seen as critical to maintain an N -bit accuracy of the current source.
55
Figure 4.2: An array of switched current cells
and mixed-signal circuits. While the DAC (in Fig. 2.8) exhibits a degree of repeatability
that lends itself to an automated design methodology, the designer is often confronted with a complex design space and forced to resort to a custom design flow. To this end, a number of process-related limiting factors affect the performance of the DAC, resulting in failure to meet the target specifications. The design space of a DAC can be highlighted in terms of four major challenges at the micro-level: switching speed, output impedance, device noise and signal swing. A successful DAC design can only be achieved by carefully optimizing across this space to meet the desired specifications. The remainder of this section will address the DAC design space in detail.
4.2.1 Switching Speed
The near-Nyquist performance of the DAC is highly dependent on the switching behavior of the current cell. We shall denote the switch’s behavior by two regions of transitions:
switching time and settling time, as illustrated in Fig. 4.3. The switching action is further
denoted by two sub-regions. The time it takes for the transistor to detect a transition at the input is denoted as response time. This is primarily a technology-dependent parameter.
The remaining portion of the switching period comprises the rise time of the current within the transistor; this is a function of the intrinsic parasitic capacitance, drain capacitance and the magnitude of current flowing through the transistor. The settling or glitch recovery
56
period is a function of the overall capacitance, as seen on the drain.
Figure 4.3: Switching and settling behaviors in a transistor
The switching and settling behavior is also strongly dependent on the rise time of the input signal. Furthermore, the finite gate-drain capacitance of the transistor causes a signal feed-through to occur. This results in voltage glitches on the drain of the switch,
further increasing the settling times. Fig. 4.4 details the switching action in a current-
steering cell, where the data signal at the gate switches between voltage levels separated by
∆ V
IN
, with a rise time t
R
. Using the model described in [24], the delay of a current-mode
switching transistor can be expressed as
Delay = k
RC
∆ V swing
( C load
) + t
R min
∆ I swing
V
OD
∆ V
IN
, 1 (4.1)
57
where, k
RC
:
∆ V swing
: Single-ended voltage swing at drain of the switch
∆ I swing
: Single-ended current swing = Cell current t
R
: Rise time of the input at the gate of the switch
V
OD
: Overdrive voltage of the switch = V
GS
− V
T
∆ V
IN
: Input voltage swing
Figure 4.4: High-speed switching phenomena
While a large value of ∆ V
IN improves the switching characteristics, it also increases the swing at the drain of the switch pair ( ∆ V swing
), resulting in an increase in the overall cell delay. In addition, the maximum achievable ∆ V
IN within a rise time t
R is limited by the process node. Further, the high-speed transition at the gate node increases the instantaneous voltage swing on the switch-pair drains. Keeping the load capacitance fixed, the total delay of the switch (sum of the switching and settling time to achieve over 95% of the final value of current) is simulated in a 90 nm CMOS process and the results are
58
plotted with respect to the cell current in Fig. 4.5. The curves correspond to different
widths for the switching pair, while the lengths are kept at minimum. Based on the curves, we can deduce that high current densities result in fine switching times. However, there is no improvement in switching speed beyond certain values of current, which is when we reach the technology limitation!
Figure 4.5: Dependence of the transistor switching time on current
This in turn is seen to be limited by the device transit or cut-off frequency ( f
T
) for
a given process technology. Fig. 4.6 illustrates a hyperbolic increase in intrinsic device
speeds with the reduction in gate lengths, as outlined by the International Technology
Roadmap for Semiconductors (ITRS) [25]. Thus, finer process technologies are mandated
in order to achieve DACs with high sampling speeds. In current-mode circuits, a general rule of thumb is to restrict the transistor switching speed to lesser than f
T
/ 20
the DAC target speed can be set by the process f
T
, which can also be used to set the LSB
59
Figure 4.6: Trend in device f
T as a function of feature length current and the physical size of the switching pair. It is important to note that the current cells operating at lowest and highest current magnitudes have to switch simultaneously at the desired operation speed. In the event of mismatch in switching speeds between the
MSB and LSB cells, segmentation of the DAC is adopted.
4.2.2 Output Impedance
Another challenge in a DAC cell is to create an accurate bias current that precisely scales across all binary and thermometric cells. Since the drain of the bias transistor is connected to the switch pair, any switching action will cause an instantaneous glitching on this node.
Owing to the finite output impedance of CMOS transistors, this glitching can affect the instantaneous accuracy of the current source, thereby causing loss of linearity. More important, the glitching action occurs at the sampling speed. In order to avoid linearity
60
degradation across the entire Nyquist band, a high current source impedance is desired even at high frequencies. Cascoding is a circuit technique often used to improve the output impedance, at the cost of headroom. For the cascoded current source, shown in
Fig. 4.7, the cascoded current source impedance (
Z
CS
( s ) ) is analytically expressed as
Z
CS
( s ) = r ds 1
+ r ds 2
+ g m 2 r ds 1 r ds 2
+ sC
1 r ds 1 r ds 2
1 + s ( C
1
+ C
2
) r ds 1
+ sC
2 r ds 2
+ sC
2 g m 2 r ds 1 r ds 2
+ s 2 C
1
C
2 r ds 1 r ds 2
(4.2)
Figure 4.7: A cascoded current source
Fig. 4.8(a) illustrates the improvement in the low frequency impedance of the current
source as a function of the ratio of the lengths of the transistors M
2 to M
1
, for various
M
1 lengths.
While it is observed that a large channel length for M
1 improves the output impedance, increasing the length of M
2 further enhances the cascoding effect, resulting in output impedances in the order of tens of megohms. This significantly aids in achieving high static accuracy for the current sources. However, increasing transistor length, while maintaining its aspect ratio, increases the drain capacitances ( C
1 and C
2
), thus degrading the
impedance at high frequencies (hundreds of megahertz). Fig. 4.8(b) illustrates the impact
61
(a)
(b)
Figure 4.8: (a) Low-frequency (DC) output impedance (
Z
CS
(0)
put impedance ( Z
CS at 100 MHz) of increasing channel lengths for M
1 and M
2 on the high frequency output impedance.
Such opposing effects of increasing channel lengths call for an optimal choice to be con-
62
sidered when sizing the current sources, in order to strike a balance between the high and low frequency distortion limits. Even if we ignore the headroom issues associated with cascoding, we still face the problem of low output impedance at high frequencies.
Let us take a closer look at this phenomenon. Fig. 4.9 illustrates the impact of
current and transistor length on the output impedance. As expected, when we increase the current, while maintaining size, we see a drop in output impedance (red to blue circles).
This is caused by channel length modulation effects that are further exacerbated in newer process technologies. In order to increase the impedance at higher current, we need to increase the device in proportion and hence its width, so as to maintain a constant current density (shown in blue squares). The interesting thing to realize is that the impedance bandwidth drops in 1:1 relationship with its DC value. In essence, we find that the 1ohm AC impedance intercept point for the current source is essentially a function of the
transistor output capacitance and hence its size. We notice from Fig. 4.9 that roughly a
6x increase in DC impedance, corresponds to increasing the cell capacitance by a similar amount, and hence a drop in the impedance bandwidth in proportion. Thus, there exists another technology limitation, dictated by the oxide capacitance C
OX of the process.
Finite cell impedance
Having discussed and established the fundamentals behind impedance issues in a transistor, let us proceed to examine the manifestations of finite output impedance of a transistor.
Stated otherwise, how much of impedance do we need? Let us first consider the impact of finite cell impedance and remind ourselves that the DAC’s output current is fed into a load resistor, R
L
. If the cell impedance were infinite, then the effective output impedance would simply be R
L
. However finite impedance causes a code-dependent output impedance
modulation, that causes both static and dynamic non-linearities 14 .
14 The static performance of the DAC is also dependent on the intrinsic accuracy of the current sources,
while will be described in detail in section 4.2.5
63
Figure 4.9: Impact of transistor size and current on impedance
Consider the current cell in Fig. 4.10. Let us denote
Z
DAC
( s ) to be the effective parallel impedance looking into the DAC array. As the DAC cells are turned on, more cells are added in parallel, thus reducing Z
DAC
( s ) . Assuming an all-unary DAC, the total output impedance pertaining to the n th code is given by
Z
DAC
( s ) =
Z
CELL
( s ) n
(4.3)
Accounting for the load impedance, R
L
, the differential output voltage can be expressed as
V
OU T
= I
LSB
R
L
( n
1 + n
R
L
Z
CELL
( s )
2 N − n − 1
−
1 + (2 N − n )
R
L
Z
CELL
( s )
)
(4.4)
It is observed that the total output impedance of the DAC changes as a function of the input code. Such an effect is termed code-dependent impedance modulation, and is one of the fundamental factors limiting the distortion performance of a DAC. In the event of
64
Figure 4.10: Impedances in a current-steering cell finite | Z
DAC
(0) | , the static transfer characteristics become nonlinear. For a differential implementation, the third-order distortion level, HD
3 may be expressed as,
HD
3
=
R
L
.
2
N
4 Z
CELL
2
(4.5)
A 12-bit DAC with an R
L
/ | Z
CELL
(0) | of 5 × 10
− 5 results in an HD
3 of about -53 dBc at low frequencies. This distortion level is significantly higher than the intrinsic performance
of the DAC. Fig. 4.11 illustrates the HD
3 as a function of R
L
/ | Z
CELL
(0) | for various resolution. Two key observations must be made: (1) The increase in resolution places more stringent requirement on the cell impedance, and (2) The HD
3 improves quadratically with the cell impedance, i.e. doubling the impedance lowers the HD
3 by a factor of four.
65
Figure 4.11: HD
3 performance vs.
R
L
/Z
CELL
(0)
While this clearly introduces static and dynamic errors, the DC errors can be quite minimal owing to the fact that the impedances are purely resistive at low frequencies. The capacitive component of the cell and the load impedance further degrade the linearity at high frequencies. In case of a differential DAC, the resultant INL due to code-dependent impedance follows an S-shaped curve.
This implies only odd-order distortion will be
generated. The static linearity metric for such a scenario, can be estimated as [15, 26]
INL
R
L
.
2 2 N
4 R
CELL
(4.6)
In a single-ended implementation, the INL has a bow-shaped curve, thus causing both even and odd-order distortion. Furthermore, the INL is an order of magnitude higher than that of a differential DAC. Cascoding at the cell-level using transistors M
5 , 6 helps improve the low frequency output impedance and make this effect sufficiently small. However, no
66
benefits at high frequencies is seen, as observed from Fig. 4.12. This drop in impedance
at high frequencies causes a rapid drop in SDR as signal frequency increases. Furthermore, a higher resolution DAC demands higher impedance and is therefore limited in bandwidth, thus manifesting the fundamental trade-off between bandwidth and dynamic distortion.
Figure 4.12: Cell-level cascoding offers no benefits at high frequencies
Finite current source impedance
We have already noted that as the magnitude of current increases, as larger device is required to provide sufficient impedance. The use of a large device also permits tolerance towards process mismatches. However increasing the size of the current source results in increased capacitance at the source node ( V
S
) of the switching pair. The manifestation of this capacitive effect is better understood in the temporal domain. As illustrated in Fig.
67
4.13(a), when the data switch, transistors
M
3 and M
4 shift from cut-off to saturation region or vice-versa. However, this transition is not instantaneous; there exists a finite amount of time for which both switches are simultaneously on. During this period, the current source is immediately choked and the node V
S
is discharged [27]. Once the switch
pair’s operating region transition is complete, the current source is forced to recharge the node, V
S
, instead of delivering the desired current to the output node. The presence of a large capacitance at this node increases the recharge time constant. This effect is manifested as an output glitch that is proportional to the weight of the unit current source. In a DAC with multiple weighted cells connected together, the weighted glitches propagate to the output, creating a code-dependent glitch pulse.
Another form of dynamic distortion arises from the large aspect ratios of M
1 and
M
2
, thus resulting in large gate-drain capacitances and gate-source capacitances. These capacitances aid in the propagation of the switching behavior at node V
S to their bias
nodes, as depicted in Fig. 4.13(b). The bias fluctuation influences the magnitude of the
i th current source by a weighted coefficient α i
, such that
I
OU T
( t ) = I
LSB
.
N − 1
X
2 i
α i b i
( t ) i =0
(4.7) thus causing both odd and even-order distortions. Intuition reveals that α i is a function of several parameters such as the size of the switch pair, the impedance of the current source and the magnitude of the current. More accurately, the distortion levels due to
current source modulation are expressed as [28, 29]
HD
2
=
HD
3
=
πf Z
L
C
CS
2 N
2 g m,SP g ds,SP
πf Z
L
C
CS
2 N
4 g m,SP g ds,SP
(4.8)
(4.9) where, Z
L represents the load, C
CS denotes the capacitance looking into the current
68
(a)
(b)
Figure 4.13: (a) Glitch propagation from the source node (b) Modulation of the current
source source, g m,SP and g ds,SP denote the transconductance and output conductance of the switch pair transistor, respectively. Interestingly, the HD
2 component is higher than the
69
HD
3
.
This observation can be used at design-time to identify the transistor that is impacting the distortion performance. If HD
2 dominates, then the distortion is due to the current source, while a dominant HD
3 is caused due to finite impedance at the DAC cell level. The current source modulation effect is mitigated by decreasing C
2 and increasing
the gate capacitance of the bias nodes 15 . Care should also be taken to minimize the
layout-induced coupling capacitance between the gates of M
1 and M
2
.
4.2.3 Device Noise
In addition to the intrinsic quantization noise, the DAC performance is also limited by the noise contribution from various circuit elements. The DAC’s target resolution and desired bandwidth together set the maximum tolerable noise floor. In CS DACs, the current source array is the major contributor of noise. In addition to its own noise contribution, noise induced by the reference bias is further magnified by the current mirroring action,
and can limit the overall noise performance. Fig. 4.14 illustrates the noise sources in
the DAC’s circuit and its associated bias network. An a : 1 current mirroring ratio is assumed between the bias network and the LSB cell. Accounting for the bias thermal noise contribution, the DAC’s total output noise can be given by i
2 d
DAC
= 4 kT
γ
α g m
M 1(0)
2
N
1 +
2
N a
∆ f (4.10) where γ and α
are process-defined noise parameters [30], and
g m
M 1(0) is the transconductance of the current source, M
1(0)
.
Fig. 4.15 illustrates the total output noise of a 12-bit DAC along with the isolated
contribution of the bias network, as a function of
a 16 . It is observed that the bias noise
is the major contributor to the total output noise. In order to reduce the impact of the bias noise, a needs to be set much larger than 2 N . This noise can be further reduced
15 Gate capacitances need to be relatively larger than the gate-drain capacitances of M
1
16 The flicker noise has been turned off in the simulation and M
2
.
70
Figure 4.14: Noise sources in a DAC by increasing the bias ratio a . However, the power consumption specifications limit the maximum value of a that can be used; i.e. for a given LSB current and a bias mirroring ratio a , there is an expense of a times the LSB current in the bias cell.
Assuming a full-scale output sinusoid current, the RMS signal power is given as
Signal Power =
(2
N
I
LSB
)
2
.
2
Thus, the thermal SNR of the DAC over a bandwidth B
(4.11)
Signal-to-Thermal Noise Ratio aI
LSB
( V
GS
− V
T
) α
16 kT γB
(4.12) where V
GS
− V
T refers to the overdrive voltage of the current source transistor, M
1(0)
. The
SNR is seen to be independent of the resolution of the DAC, and can be only improved by increasing the bias mirroring ratio, a , or the LSB cell current, I
LSB
. Let us consider a 12-bit DAC having an effective bandwidth of 100 MHz. The signal-to-quantization noise ratio is 74 dB. If the thermal noise floor is desired to be at least 10 dB below
17
The noise contribution of the DAC core is assumed negligible compared to the bias noise
71
Figure 4.15: Total output thermal noise contribution in a 12-bit DAC for various bias sizing ratios at 100 kHz the quantization noise floor, and assuming a = 1024 , V
GS
− V
T
= 100 mV and noise parameters, γ = 2 / 3 , α = 1 , the minimum bound for LSB current is set to be 10.76
µA .
The noise specification and bias sizing ratio together limit the minimum current (LSB cell) that may be used in the DAC. Along with the resolution and swing, it also sets the minimum achievable static current consumption of the DAC (including bias) in a given process technology.
4.2.4 Signal Swing
The noise-specified LSB current and resolution together determine the total current in a
DAC. This eventually sets the output swing for a given load resistor, R
L
. Thus, for a given supply voltage and transistor bias points, the maximum permissible signal swing is set to
72
ensure all transistors are kept in saturation. For high-resolution DACs, the output swing can be allowed to increase further by raising the supply voltage. However, breakdown limits often mandate the use of thick-gate cascode devices ( M
5 , 6
) on top of the switch
pair. Fig. 4.16 illustrates the output swing as a function of the LSB current for different
DAC resolutions. From the upper bound on swing limitations, the maximum permissible
LSB current can be deduced.
Figure 4.16: Output swing as a function of the LSB current for various DAC resolution
Another major concern with large output swings is the linearity degradation due to the voltage-dependent drain capacitances of transistors, M
5 , 6
. When the data switches,
73
the output capacitance of the cell carrying no current is approximately given by
C
OF F
= C gd 5 , 6( OF F )
( V ) + C db 5 , 6
( V ) (4.13) where C gd is the gate-drain overlap capacitance of M
5 , 6
, and C db is the drain-bulk capacitance. In the ON state, the output capacitance of the cell is roughly given by
C
ON
= C gd 5 , 6( ON )
( V ) + C db 5 , 6
( V ) (4.14)
This difference in capacitances in the ON and OFF states, along with the fact that the capacitance is voltage (output signal) dependent, results in code and amplitude dependent delays in addition to output load modulation. Together with the intrinsic transistor capacitances, interconnects can further increase the drain capacitance to the substrate. This eventually limits the maximum operation speed of the DAC cell. The parasitic capacitance at the output node can be minimized by layout techniques, while the mismatch in the ON
and OFF impedances is alleviated by the use of leaker currents, as proposed in [8], and
illustrated in Fig. 4.17. It is shown that a leaker current of 1 to 2% of the cell current
is sufficient to maintain a fairly constant ON and OFF impedance [8]. While the use of
leaker currents does not affect the differential output swing, it changes the single-ended swing by a constant DC value of I
LEAK
× R
L
. The total sum of all leaker currents must be taken into consideration when estimating the lower bound of the single-ended swing, thus guaranteeing M
5 , 6 are maintained in saturation.
We have so far discussed four major limiting parameters in the DAC design space,
collectively illustrated in Fig. 4.18, as a function of the LSB current. The signal swing
and output impedance together set the upper bound on LSB current, while the device noise and switching speed determine the smallest permissible current. Such a quad-parameter design space facilitates easy design of DACs and assists the designer in choosing the appropriate process technology for a given DC specification. However, process variations
74
Figure 4.17: A modified DAC cell with leakers and neutralization switches impact the design significantly and the impact worsens with finer process technologies.
In such cases, the design parameters have to be chosen based on a margin of variability.
For example, the size of a transistor might have to be larger than required. The following subsection explains how transistor operating points are affected to counteract process variability.
4.2.5 Mismatches
Based on the previous sections, the DAC LSB current ( I
LSB
) is chosen to optimize across the design space. Subsequently, the transistor size and overdrive voltage need to be determined. An overdrive voltage of at least 100 mV is typically needed to ensure that the transistor is operating in strong inversion, and also to guarantee sufficient matching
between the reference bias cell and the current mirrors. As discussed in section 4.2.2,
75
Figure 4.18: The DAC design space: device noise, output impedance, signal swing and switching speed the lengths of the current source transistor and its cascoding device are set based on the output impedance requirement. As a result, the width of the transistor can be calculated.
Another critical element that dictates the minimum size of the transistor is the mismatch accuracy between the MSB and LSB cell. One of the primary contributors to the variation between the two cells is the threshold voltage ( V
T
) mismatch between transistors [31, 32].
Let us denote the LSB and MSB currents for an N -bit DAC as
I
I
LSB
M SB
=
=
1
2
µC
OX
2
N − 1
W
1
L
µC
OX
2
V
2
OD
W
( V
OD
L
− ∆ V
T
)
2
(4.15)
(4.16) where µ is the channel mobility, C
OX is the specific oxide capacitance, W ( L ) is the width (length) of the LSB current source transistor, V
OD is the overdrive voltage, and
76
∆ V
T is the maximum mismatch error between MSB and LSB cell. In a binary cell array, the error in the MSB current source must be kept well below 0.5 LSB in order to maintain
full accuracy. From (4.15) and (4.16), the maximum tolerable mismatch error can be
expressed as
∆ V
T
≤ V
OD
(
1 ± r
1
1 +
2 N
)
(4.17)
This equation suggests that a lower V
OD implies a lower maximum tolerable V
T mismatch.
On the other hand, if the V
T mismatch were to be fixed, we need a large V
OD to circumvent
the mismatches. Fig. 4.19(a) illustrates that the maximum tolerable
V
T mismatch reduces as a function of the DAC resolution, further highlighting the issue of designing highresolution DACs for a given mismatch constraint.
V
T ation, σ
V
T
= A
V
T 0 mismatch as a Gaussian distribution with standard devi-
/
√
W L , where A
V
T 0 is a technology-dependent parameter. Therefore, in order to reduce the magnitude of σ
V
T
, the transistor area can be increased, while main-
taining a constant aspect ratio. Fig. 4.19(b) illustrates the impact of increasing the area
of the transistor on σ
V
T for a 90 nm CMOS process, assuming a V
OD of 100 mV. It is seen that even for a moderate resolution DAC, a large transistor area is required to minimize the impact of V
T mismatch. However, this results in reducing the high-frequency impedance of the current source, thus limiting the dynamic linearity of the DAC. The high-speed
DAC designer is thus confronted with the challenge of meeting both static and dynamic linearity requirements. In the case of high-resolution DACs, the mismatch requirements dictate a transistor area that is prohibitive. In order to relax the transistor area requirements, a segmentation topology is adopted, such that the mismatch constraint is applied
to the highest binary cell [32, 33].
77
(a)
(b)
∆ V
T
σ
V
T mismatch as a function of gate area
Impact of process variations on the DAC architecture
Process variations can affect the current source matching significantly. Assuming a LSB current standard deviation of σ
LSB
, the integrated error of all current sources is the same
78
in all three architectures - binary, unary and segmented; hence, the INL of the DAC does not vary with segmentation. However, the DNL is a function of the step size or the magnitude of the switching current source. In a binary DAC, the MSB cell current accuracy must be met with respect to the LSB cell current; i.e. the percentage error in the MSB current cell must be lower than the LSB cell current. For example, in a 10-bit
DAC, the MSB current is 2
9 times the LSB current, I
LSB
. This implies the error in the
MSB current should be no more than I
LSB
. In reality, it should be less than 0 .
5 I
LSB
. Fig.
4.20 depicts the bound on the amount of error that can be tolerated in the binary cells
for various resolutions. It must be noted that the 2nd LSB cell can have an error as high as 25%, for all resolutions. For higher resolutions, say 10-bits, the percentage error of the
MSB current source must be maintained less than 0.098%. Hence, high resolution binary
DACs demand stringent accuracy requirements on the MSB current cell. Conversely, in a thermometer DAC, all current cells are equal in magnitude; hence the required accuracy is low and set by the unit current cell. With similar argument, the accuracy requirements in a segmented DAC can be shown to be set by the maximum number of binary bits.
Table 4.1 compares and summarizes the three architectures for an
N -bit DAC in terms of complexity and static linearity metrics.
4.3 The Segmentation Philosophy
Although segmentation has been accepted as a mainstream option, it remains to be argued as to what is indeed the optimal choice of the ratio of unary MSBs to binary LSBs. Let us proceed to learn how various micro-level challenges affect the degree of segmentation.
4.3.1 Segmentation driven by Area and static linearity metrics
The limited accuracy of the MSB current sources can result in high levels of nonlinearity
(i.e. large INL), which in turn degrades the dynamic performance of the DAC. Table 4.1
79
Figure 4.20: Maximum permissible error in MSB current cell can be used to obtain the desired level of segmentation, based on tolerable mismatch constraints.
Realizing that the mismatch numbers are a function of the area of the
current sources, as observed from Fig. 4.19(b), the optimal segmentation for the DAC is
determined by estimating the analog and digital decode logic areas for a given DNL and
INL spec. For a fixed overdrive voltage, the current mismatch is dependent on process
parameters and area, and obtained from [31] as
σ
LSB
I
LSB
=
∝
=
∆ β
−
β
1
√
W L c
√
Area
∆ V
T
V
GS
− V
T
(4.18)
(4.19)
80
where c is a process-dependent constant of proportionality. For a given DNL specification,
DN L
M AX
, let A
LSB denote the area of the LSB current source in a unary DAC. Then
A
LSB
∝
1
DN L 2
M AX
= c 2
DN L 2
M AX
(4.20)
In order to maintain the same DN L
M AX
, the k : m segmented DAC must have an
LSB current of size, A
LSB,SEG
, expressed as (From Table 4.1)
A
LSB,SEG
= 2 m
A
LSB
(4.21)
Thus, the total analog area of the segmented DAC is given by
A
AN ALOG
= 2
N
A
LSB,SEG
(4.22)
For a high degree of segmentation i.e. large k , the complexity of the digital logic to decode the binary to unary bits increases. Denoting the digital area for a single thermometric cell as A
DIG,T HERM
, the total digital area is represented as
A
DIG
= 2 k
A
DIG,T HERM
(4.23)
Fig. 4.21 illustrates the required analog and digital area for a 10-bit DAC as a function
of the segmentation ratio. The area set by an INL requirement of 1 LSB is drawn as a horizontal line. The abscissa of the points intercepted by this line with the analog or digital area determines the optimal segmentation ratios. In the case where two optimal solutions are obtained, the higher segmentation ratio is chosen as it results in lesser mid-code
transition glitch energies [32]. In the case when the area is set by an INL of 2 LSB, the
point where analog and digital areas are equal is chosen to be the optimal segmentation ratio. Considering the fact that digital logic scales down twice for every factor of two reduction in length, the optimal segmentation point can be roughly defined where the
analog and digital areas are equal. Combining equations (4.20) - (4.23), the total DAC
81
area is given by
A
T OT AL c 2
= 2
N
2 m
DN L 2
M AX
+ 2 k
A
DIG,T HERM
(4.24)
Figure 4.21: Optimum segmentation based on area and static linearity specifications
In view of providing a numerical solution, the optimal segmentation point is defined as that which occupies minimum area. This is guaranteed when both the analog and digital areas are equal. Thus,
A
AN ALOG c 2
2
N
2 m
DN L 2
M AX c
2
2
N
2 m
DN L 2
M AX
= A
DIG
= 2 k
A
DIG,T HERM
= 2
N − m
A
DIG,T HERM m =
1
2 log
2
82
A
DIG,T HERM
DN L 2
M AX
2 c 2
(4.25)
(4.26)
(4.27)
(4.28)
Equation (4.28) denotes the maximum number of binary bits that is permitted in the
design to meet the given DNL spec. A larger DNL tolerance spec implies that a larger mismatch can be tolerated, indicating a larger number of binary LSBs (m). Ignoring the improvement in device matching over a constant area (assuming c is constant), and with the assumption that the digital area decreases with feature lengths, an increase in the number of thermometer decoded bits is seen, as we progress to shorter channel lengths.
However, this is not quite true. If the area is maintained constant while porting the design to finer lengths, matching improves significantly, leading to a more binary-centric architecture.
4.3.2 Segmentation driven by micro-level challenges
Apart from mismatch-induced errors between the DAC current cells, fundamental circuitlevel challenges, such as parasitic capacitance and finite output impedance, also influence the degree of segmentation. The degradation in transistor output impedance as channel lengths decrease, limits the maximum current that can flow through a transistor. As a result, a 100% segmentation (unary DAC) is favored for low impedance processes. On the other hand, 2 N − 1 current cells in a unary DAC increase the effective parasitic capacitance at the output node, thus limiting the speed of operation. In such cases, a 0% segmentation (all-binary DAC) is preferred. In addition, a high degree of segmentation results in a significant increase in the DAC area (digital logic, analog current cells and interconnects) that makes timing compliance a challenge at the desired speed of operation.
Thus, an optimal choice of segmentation needs to be made, with both process technology and circuit topology in mind. The reader is also reminded that changes to the choice of segmentation can result in redesign of the DAC cell.
As discussed in Sec. 4.2.2, a high current source impedance determines the accu-
racy of the current sources, while a high DAC cell impedance mitigates the effect of
83
code-dependent impedance distortion. The extent by which a high Z
CS is required, is determined by the voltage fluctuation at the switch pair source node, V
S
, relative to the
LSB. It is noted that the resolution accuracy of the current sources needs to be maintained over the desired synthesis bandwidth of the DAC; i.e. both DC and AC impedances need to be sufficiently large. The LSB cell is designed to have the highest possible Z
CS over the synthesis bandwidth. As the current source is scaled in powers of two, Z
CS halves.
The largest current cell that guarantees the desired output impedance across the synthesis bandwidth is where segmentation begins; all subsequent current cells are unary-weighted.
This is the lower bound on segmentation (refers to the maximum number of binary cells that can be used) for the DAC. On the other hand, the desired DAC output bandwidth
(computed from the load resistor and effective capacitance of all current cells) sets the upper bound on segmentation (or the maximum number of thermometer cells that can be used in the DAC). Given the bounds on segmentation, the lower limit is more preferred as it implies fewer number of cells to be connected together, resulting in short routing lengths. This significantly aids in the reduction of the overall routing capacitance, thus decreasing clock skew mismatch and improving output bandwidth. Furthermore, a smaller effective area for the current sources helps decrease the ground line IR drop, which improves the cell matching. However, as discussed earlier, low segmentation designs demand high accuracy current sources.
In addition, there exists a large ratio between the current magnitudes in the LSB and
MSB cells in high-resolution DACs. In an N-bit DAC, the unary current cell sinks 2
N − 1 times the LSB current. We have already seen that the switching time of a transistor is dependent on the current flowing through it. As a result, the response times of the
LSB cell ( τ
LSB
) and the MSB cell ( τ
M SB
) differ significantly, resulting in a mismatch
in switching time instants, as depicted in Fig. 4.22(a). In swing-limited high-resolution
designs, the difference in timing can be exorbitantly large, owing to very fine LSB currents.
84
(a)
(b)
Figure 4.22: (a) Temporal view of timing mismatch between current cells (b) Timing
variations across the binary cells
This is a typical case of the designer’s paradox: The Resolution-Bandwidth trade-off. Fig.
4.22(b) depicts how the timing of four binary cells can vary significantly, when operating
85
in the low current regime. Such cell-by-cell timing mismatches result in the formation of output glitches that can limit the speed of operation, especially in gigahertz DACs.
A timing difference in the order of few tens or hundreds of picoseconds can significantly impact the DAC SFDR, when operating even above few 100s of MHz.
A simple solution to mitigating this problem is to increase the current through the cells. However, headroom limitations impose a constraint on the total allowable current.
On the other hand, segmentation can be adopted based on the criticality of timing mis-
. Depending on the current regime of the LSB transistors, the number of binary
LSBs can be set, such that the overall timing is not affected much. Although, a high degree of segmentation addresses the problem of intra-DAC timing, it poses the penalty of increased area and capacitance. Furthermore, a large chip area results in being sensitive to process variations across the chip that affect the matching between the current cells, both temporally and spatially. Consequently, the resolution-bandwidth trade-off comes into play.
4.4 Challenges at the Macro-level
While the challenges described so far might seem overwhelming, it is highly unfortunate that more challenges exist. In fact, these challenges occur due to physical placement and arrangement of the design. Upon appropriate choice of segmentation, the DAC cells are designed and laid out individually. While arranging the DAC cells together, one of the primary challenges we face is the growth in size. As the resolution increases, a large array
is to be laid out, specifically for unary cells, as depicted in Fig. 4.23. This growth in
size leads to several challenges, that hinder the achievable performance. The following subsections will delve into these macro-level challenges one by one.
18 The segmentation approach is based on the effect that is most severe - low impedance, switching time mismatch, or process variations
86
Figure 4.23: Macro-level challenges in a DAC
4.4.1 Intra-DAC Timing Mismatch
Timing mismatch between the DAC cells, is one of the major issues faced in a DAC design, and is the cause for severe degradation in dynamic performance. We have already discussed the effects of intra-DAC timing caused at the DAC cell level. Assuming that this problem is sorted out, by appropriate choice of segmentation or design innovation, physical placement of these cells can result in timing mismatch. Such mismatches can occur due to process variations, and can be mitigated by using large-size transistors. But the subsequent increase in area, results in the need to route clocks using long interconnects.
Mismatches accumulating on these clock lines, or even unequal interconnect lengths, can cause a mismatch in clock arrival times, thereby leading to intra-DAC timing mismatch.
In order to provide accurately matched clocks, an H-tree is often used, as shown in Fig.
87
4.24(a). This routing construct guarantees that the path lengths from the clock feed to
all inverters are identical, hence guaranteeing matched clock arrival times. Unfortunately, as the DAC resolution increases, the associated clock network grows with it. Realizing the fact that the fanout of buffers in nanometer CMOS is limited, we are forced to insert
buffers along the clock tree (Fig. 4.24(b)). Employing a fanout of 2, it is seen that the
number of buffers required grow with the size of the H-tree.
(a) (b)
Figure 4.24: (a) A H-tree for clock feeds (b) Buffer requirements in a H-tree
The use of buffers indeed sharpens the rise/fall times of the pulses, and aids in improving the drive strengths. It is often advised to increase the drive strengths of a path by the insertion of buffers, i.e more buffers are good. Although this means more power consumption, the buffers also pose two other serious problems - noise accumulation and
skew mismatch, as illustrated in Fig. 4.25
Random jitter accumulation in a buffer chain The random fluctuations of charges in a transistor, attributed to temperature, causes thermal noise. The thermal noise results in jitter in the clock feeding to the DAC. In addition to the intrinsic thermal noise, noise from the supply can also affect the pulse transients. It is important to understand how
88
Figure 4.25: Issues caused in a buffer chain noise propagates through a buffer chain. Let us consider a chain of buffers that are
progressively increasing in size, similar to the one shown in Fig. 4.25. Tests conducted on
this chain reveal that the accumulated jitter increases logarithmically as the depth of the
buffer chain increases. It is observed from Fig. 4.26(a) that a 5-stage buffer driver results
in an RMS thermal noise of roughly 20 fs in a 90 nm CMOS process. The random noise causes an increase in noise floor or degradation in SNR across the Nyquist band. It can also be shown that the SNR at the output of the DAC is related to the RMS jitter as,
SNR = 10 log
1
2( πBW σ j
) 2
(4.29)
It is seen that the 20 fs jitter roughly limits the achievable SNR to 80 dB in a bandwidth of 1 GHz. What this suggests is that, no matter what the sampling speed is or what resolution DAC is designed, the absolute bandwidth in which an 80 dB SNR can be achieved, is limited to 1 GHz.
Skew mismatch accumulation in a buffer chain The next grave timing problem is attributed to the physical separation between various buffer paths in the clock distribution network. The differences in clock arrival times, owing to process mismatches, leads to
89
(a)
(b)
Figure 4.26: (a) Jitter accumulation in a buffer chain (b) Jitter limitations on SNR
clock skews. Using the same example of a buffer chain, it is seen that skew mismatch increases logarithmically with the chain depth. Further, the mismatch is measured as a fraction of the clock period. As a result, buffers for high sampling clocks accumulate a
90
larger skew. It is observed from Fig. 4.27(a) that a 3-stage buffer exhibits a 10% sigma in
skew variation at a sampling speed of 4 GS/s. Such skew mismatches result in increased distortion, or otherwise a drop in SDR. The SDR is seen to be a function of not only the resolution, but also the sampling speed and the signal frequency. A 10% skew mismatch indicates that the achievable distortion cannot be better than about 40 dB across the
Nyquist band.
The above discussion on how the buffer chain impacts the DAC performance highlights the fact that improper design and layout of peripherals (buffers, drivers, flip-flops, etc.) can significantly impact the DAC’s performance, even if the core is excellently implemented.
4.4.2 Analog and Digital IR Drop
It is well known that the metal lines in any given process have finite resistivity. The finite resistance of the supply feed network for a large DAC array causes a great deal of IR drop issues. The problem is magnified in long feed lines and those that carry huge currents; e.g. supply feeds to CML buffers, drivers and switching logic. We can further classify the effects of IR drop, based on the domains that get affected as, Analog IR drops and Digital
IR drops.
Analog IR drops specifically refer to ohmic drops on the common ground line of the
. This leads to a systematic current mismatch that can be observed
even during the design cycle. Specifically, the relative placement of the current source transistors with respect to the reference line can result in a current mismatch that has a
graded or symmetric profile, as illustrated for the unary current array in Fig. 4.28(a). To
elaborate this, if the GND connection is provided to this array from one side, say, left, the transistors on the far right see a larger ohmic drop on the ground line. This suggests
19 For a PMOS-based DAC, the current sources will comprise PMOS transistors, and the common node is a supply line.
91
(a)
(b)
Figure 4.27: (a) Mismatch accumulation in a buffer chain (b) Skew mismatch limitations
on distortion
92
that the V
GS
− V
T
, and hence the absolute value of current decreases for the DAC cells, compared to the ones on its left. This type of feed results in a graded profile for current.
If the GND connection is provided on either side of the array, the overall ground line ohmic drop halves, leading to a symmetric profile for the current mismatch.The impact of such ohmic drops leads to a degraded SFDR and sacrifice in signal fidelity at low and high frequencies. In order to evaluate the permissible IR drop on the current source feed lines, an 8-bit DAC was designed and a graded profile of IR drop was simulated on the
analog ground lines of the various DAC cells. Fig. 4.28(b) illustrates the steep decrease
in SFDR as the analog IR drop increases. It is observed that to obtain a 40 dB SFDR from an 8-bit design, the analog IR drop needs to be limited to well within 15 mV. While this is not a golden number to design DACs, it explains the trend with increasing analog ohmic drops.
Any IR drops (or bounce), or specifically mismatch in IR drops, on the digital supplies causes the various cells to exhibit varied switching delays. This is applicable to latches,
flops, buffers, drivers, etc. shown in Fig. 4.29 are two identical DAC cells, including the
decoder, latch and drivers. One of them is assumed to have a lower supply than the other. As a result, the transistors are slowed down, causing the data feeding into the
DAC current cell to exhibit varying amplitudes and delays. To a fair extent, the delays
are linearly proportional to the bounce on the digital supply, as shown in Fig. 4.30(a).
However, tests conducted on an 16 GS/s 8-bit DAC design reveal that a digital VDD
bounce of 40 mV can limit the achievable SFDR to 45 dB, as noted from Fig. 4.30(b).
For lower sampling clocks, these delays are a smaller fraction of the clock period, thus resulting in a slightly higher SFDR of roughly 48 dB. Bounce on the digital cells of the data-path can lead to excessive delays causing setup violations, while delays on the clock can lead to hold-violations. Thus, we also need to focus on limiting the digital supply variation across the DAC cells, as the resultant timing violations significantly impact the
93
(a)
(b)
Figure 4.28: (a) Ohmic drops on the analog ground (b) Impact of analog IR drop on the
achievable SFDR dynamic performance.
To summarize, all the macro-level challenges discussed so far pose severe limitations to the achievable performance. The important thing to note is that these are only peripherals
94
Figure 4.29: The problem of digital supply bounce that provide access to the DAC, be it supply feed or data feed or clock feed. Such a holistic view and understanding of the DAC is mandatory to keep the designers on their toes, so that the performance is not sacrificed.
95
(a)
(b)
Figure 4.30: (a) Impact of digital VDD bounce on digital delays (b) SFDR limitations due
to digital IR drop
96
97
Chapter 5
Towards Higher Speeds
There are a number of innovative solutions that have aimed to address the micro-level and macro-level challenges, and push the speed of the DACs into the GHz regime. This chapter details an innovative solution to reducing the resolution-bandwidth trade-off in a
DAC cell. Another solution is presented at the architectural level, where the interleaving phenomena is employed in DACs to mitigate non-linearities and aid in replica cancellation. A mathematical study is conducted to highlight some of the remarkable benefits of interleaving.
5.1 A high-speed low-latency DAC cell
One of the critical issues with the DAC core is the mismatch in switching times between the binary cells. These timing mismatches occur at the design level, and pose a fundamental impediment to achieving high resolutions at high speeds. The older methods to alleviate this problem, as explained in earlier chapters, is by the use of segmentation. Unfortunately, it leads to a penalty in increased occupied area and capacitance.
A large chip area further results in being sensitive to process variations across the ends of the chip, and
IR drops affect the matching between the current cells, both temporally and spatially.
Consequently, the resolution-bandwidth trade-off comes into play again. Further, the high-speed transition at the gate of the switch pair produces a charge injection through
98
the gate-drain capacitance; this increases the instantaneous voltage swing on the switchpair drains, as well as those of the cascode transistors ( M
5 , 6
). In particular, the glitching on
Figure 5.1: A modified DAC cell with leakers and neutralization switches the MSB current cells, can leak into the LSB cells causing distortion. In order to reduce these glitches, neutralization switches ( M
7 , 8
), are used to feed an equal and opposite
glitch, as depicted in Fig. 5.1. The size of the neutralization pair can be adjusted to
control the amount of opposing charge, so as to minimize glitching activity. The cons of this technique is that a larger drive strength is required on the previous stage.
Another feature to note that is existent in this cell, is that the effective output current is the difference of current in the two arms. Since, the DAC cell is processing the difference of a current, say I
LSB
, and 0 (no current), why don’t we engineer the cell to process differential currents itself? i.e. switch between two large currents I
1 and I
2
, such that the difference is I
1
− I
2
= I
LSB
, as illustrated in Fig. 5.2(a). If for the LSB cell,
I
1 and I
2 were chosen to be 2 N − 1 I
LSB and (2 N − 1 − 1) I
LSB
, then the difference in currents is I
LSB
, while the switching speed is comparable to that of a conventional MSB cell, carrying a large current, I
1( or )2
, as depicted in Fig. 5.2(b). This cell shall be referred to as
99
(a)
(b)
Figure 5.2: (a) A high-speed low-latency DAC cell (b) Timing matching in the HSLL DAC
cell
100
a high-speed low-latency (HSLL) DAC cell, or simple a cross-couple DAC cell. Depending on the choice of I
1 and I
2
, the LSB cells can have their timing matched to the MSB cells with a better accuracy than before. Since the modified DAC cell processes difference in currents as opposed to absolute currents, a higher resolution DAC may be designed without sacrifice in speed or bandwidth. Theoretically, this circumvents the resolutionbandwidth trade-off. However, achievable speeds still remain limited by the process f
T
.
The drawback of this technique is the increased current in the DAC core, which may be limited by using appropriate choice of currents and also by incorporating this technique only in a few of the LSB current cells. In addition, when the gate of M
3 switches from low to high, a rising switching glitch is created at its drain. This occurs owing to feed-through from its gate drain capacitances. At the same time, the falling pulse at the drain of M
4
0 creates a falling glitch at the same node (as their drains are connected.) The opposing glitch activity cancels each other, resulting in a switching glitch-free output. Thus, the proposed cell acts as a neutralization cell to remove switching glitches, without the need for additional neutralization circuits [4, 5].
Two cases of cross-coupled cell, carrying different currents such that they yield the same I
LSB
. were simulated: I
1
= 8 I
LSB
, and I
1
= 16 I
LSB
switching times for various I
LSB currents. A 75% improvement in the switching times is seen in the HSLL cell, compared to the conventional cell. However, the timing accuracy of the HSLL cell is sensitive to mismatches in the differential paths. Key advantages of this cell are:
1. Speed vs.
resolution trade-off has been removed, enabling the design of highresolution high-speed DACs. The maximum speed is however limited by the process f
T
.
2. The speed enhancement of binary cells helps reduce the segmentation ratio in DACs, enabling smaller chip area, reduced digital logic and improved output capacitance.
101
3. The use of cross-coupled cells also helps in reducing glitch activity at the drains of
M
3 , 4
, by means of neutralization
Figure 5.3: Switching performance comparison between the conventional and the HSLL cell
5.2 Interleaved DACs
Time interleaved ADCs have been well studied and shown great promise in extending their
operating bandwidth [34]. In such ADCs, the same input signal is fed across all the sub-
ADCs, each clocked at multiple phases of the sampling clock. In contrast, the interleaving action in DACs can be categorized into two different groups - data interleaving and hold
interleaving. Figure 5.4 shows the various types of four-way interleaving structures. In
102
Fig. 5.4(a), multiphase clocked-interleaving or
L
-fold interleaving [35] uses the same
data for all DACs, with each DAC being clocked at time-shifted versions of the sampling clock at τ
1
, τ
2
, ..., τ n
. While this cancels spectral components determined by the signal and the clock frequency, it is unsuitable for wide-band suppression. Staggered operation
(Fig. 5.4(b)) of multi-phase DACs was proposed in [36, 37], but the design requirements
imposed on a single DAC operating at f
CLK is equivalent to that operating at N f
CLK
.
In order to relax the DAC hold requirements, the data feeding the DAC is processed at
N f
CLK
resolution (Fig. 5.4(c)), so as to yield the same output as that of a staggered
operating DAC [38]. Another option is to use interleaved data feeding the DACs, each
operating on interleaved phases of a clock, and having their outputs held for the entire period of a clock, thus manifesting both data and hold-interleaving in them. Since, all
DACs together influence the effective output, a normalization factor of 1 /N helps visualize
the output to be the mean of all DAC outputs, as shown in Fig. 5.4(d).
The Direct Digital-to-RF (DDRF) DAC comprising N
parallel DACs [39] falls under
the category of both data interleaving and hold interleaving. Figure 5.4(d) illustrates its
structure for a four-way case. Interleaved digital data samples of a signal at the rate of f
CLK
=
1
T feed multiple DACs, each reconstructing at interleaved time instances of a multi-phase clock. On summing the DAC outputs, this enables the cancellation of the first N − 1 image replicas. It is worth noting that all DACs concurrently hold their output values and do not operate in a staggered or round-robin fashion.
5.2.1 Proposed Model
A generalized mathematical model for the N
-path DDRF DAC is illustrated in Fig. 5.5.
The output node of the DDRF DAC is updated with a new value every T /N , where
T refers to the reconstruction period. This is represented by an N times upsampling operation following the sampling operation. The N -point digital hold block replaces the
103
(a) (b) (c) (d)
Figure 5.4: (a) Hold interleaving [35] (b) Data interleaving [36] (c) & (d) Data and hold
newly inserted zeroes of the upsampling operation by the previous sample value, to be equivalent to a full-clock hold operation. Finally, each path is shifted in time relative to the first path, as represented by the delay block. The outputs of all paths are added and normalized by 1 /N . The individual DAC gain ( G i
) and offset ( O i
) error are modeled preceding the summation node.The continuous-time (CT) hold operation is represented by a rectangular pulse of time-width, T /N . Thus, the CT hold operation of time-width,
T , is represented by a discrete-time (DT) hold operation of N samples followed by a CT hold of time-width, T /N .
5.2.2 Mathematical Analysis
This section assumes an ideal DAC interleaving, where the individual path gains and offset
errors in Fig. 5.5 are ignored. Let the input signal be represented as
x ( t ) and the sampled
104
Figure 5.5: Time-interleaved sampling and reconstruction - Proposed model with mismatches signal be denoted by x i
( n ) where i refers to the path index.
x i
[ n ] = x ( t ) δ ( t − nT + iτ ) (5.1) where τ =
T
N
specifies the time delay of the sampling clock. Equivalently, (5.1) may be
rewritten as x i
[ n ] = x ( t + iτ ) δ ( t − nT ) (5.2)
Let X i
( j Ω) denote the continuous-time fourier transform (CTFT) of x ( t + iτ ) . Hence, the discrete-time fourier transform (DTFT) of x i
[ n ] at node A in the i th path, may be defined as
X
A i
( e jω
) = X i
( j Ω)
=
1
ω
Ω = k =+ ∞
X
X j
T
T k = −∞
−
ω
T
2 πk
T
−
∀ k ∈ Z
2 πk
T
∀ k ∈ Z e j iω
N e
− j
2 πik
N
(5.3)
105
Equation (5.3) indicates the generation of alias components of the original signal, occuring
at periodic intervals of 2 π/T , in the i th
path at node A (see Fig. 5.5). It is worth noting
that the individual sampled signals across all i paths exhibit identical magnitude spectrum and exhibit a deterministic phase relationship with respect to each other. Upsampling by
a factor of N (at node B in Fig. 5.5) yields
X
B i
( e jω
) =
1
T k =+ ∞
X
X j k = −∞
N ω
T
−
2 πk
T e jiω e
− j
2 πik
N
(5.4)
Upsampling results in the insertion of zeros, which are removed by passing the digital signals through an N-point rectangle filter (interpolation function). Thus, the interpolated values are same as the original non-zero value. The DTFT of the N-point interpolation function is given by
Λ
N
( e jω
) = e
− jω
( N − 1
2
) sin sin
N ω
2
ω
2
Therefore, the spectrum at node C in Fig. 5.5 can be written as
(5.5)
X
C i
( e jω
) = X
B i
( e jω
)Λ
N
( e jω
) (5.6)
Following the discrete-time interpolation, the delay blocks are now referred to the higher sampling frequency of
N
T
. Still being in digital domain, the i th path delay is represented by e
− jiω . Thus, the spectrum at node D is expressed as
X
D i
( e jω
) = X
C i
( e jω
) e
− jiω
(5.7)
Combining (5.4), (5.5), (5.6) and (5.7),
X
D i
( e jω
) = Λ
N
( e jω
) .
1 k =+ ∞
X
X j
T k = −∞
N ω
T
−
2 πk
T e
− j
2 πik
N
(5.8)
106
The term e
− j
2 πik
N indicates that the interleaved sampling and reconstruction operations together help preserve the phase signature of the sampling clock in the signal, hence exhibiting a constant phase change over the entire bandwidth of the signal and each of its aliases . Summation over N paths yields
X
E
( e jω
) = i = N − 1
X
X
D i
( e jω
) i =0
= Λ
N
( e jω
1
)
T k =+ ∞
X
X j
.
N ω
T
− k = −∞
2 πk
T
N − 1
X i =0 e
− j
2 πik
N
(5.9)
(5.10)
However,
N − 1
X e
− j
2 πik
N i =0
=
0 ∀ k = (0 , N, 2 N, ...
)
N ∀ k = (0 , N, 2 N, ...
)
(5.11)
X
E
( e jω
) =
N
Λ
N
( e jω
)
T
X k =0 , ± N,
± 2 N,...
X j
N ω
−
T
2 πk
T
On using a variable substitution of k = lN ,
X
E
( e jω
) =
N
Λ
N
( e jω
) l =+ ∞
X
X j
T l = −∞
N ω
T
−
2 πlN
T
(5.12)
(5.13)
From (5.13), it is observed that the spectrum contains spectral copies of the signal at every
2 πN/T , instead of 2 π/T , indicating the removal of spectral copies of the original signal, around 2 π , 4 π until 2( N − 1) π . This implies that the use of interleaved signal samples helps cancel image replicas. An important remark here is that the concurrent operation of all DACs does not affect the replica cancellation, but accounts for a magnitude scaling
factor alone, as observed in (5.13).
107
Let P
ZOH
( j Ω) represent the CTFT of the zero-order hold rectangle function and given by
P
ZOH
( j Ω) = sin (
Ω T
2 N
Ω T
2 N
) e
− j
Ω T
2 N
Finally, the CTFT of the output may be written as,
(5.14)
Y ( j Ω) =
T
N
X
E
( e jω
)
ω =
Ω T
N
.P
ZOH
( j Ω) (5.15) which simplifies to,
Y ( j Ω) = N l =+ ∞
X
X j Ω −
2 πN l
T l = −∞ sin (
Ω T
2
Ω T
2
) e
− j
Ω T
2
(5.16)
Thus, the first N − 1
DAC image replicas are cancelled, as illustrated in Fig. 5.6(a).
It is worth noting that each DAC operates at f
CLK
, while together they behave like a single DAC operating at N f
CLK
. However, the interpolation and averaging creates an attenuation and limits the capability of signal synthesis at and very close to f
CLK
, 2 f
CLK
, until ( N − 1) f
CLK
.
Bandwidth Enhancement
The interleaved DAC reconstruction emulates an N -times higher effective reconstruction rate, thus increasing the effective synthesis bandwidth to N -times the Nyquist bandwidth of each DAC. Subsampled samples of the signal are fed in order to synthesize signals in the higher Nyquist zones. The benefit of replica cancellation is valid even for beyond-Nyquist
signal synthesis, as illustrated in Fig. 5.6(b). However, the concurrent operation of all
DACs reduces the power of the signals in the higher Nyquist zones.
108
(a)
(b)
Figure 5.6: Rotation and cancellation of image replicas in the complex domain for (a)
Sub-Nyquist signal generation (b) Beyond-Nyquist signal generation
Resolution Enhancement
Assuming each m -bit DAC comprises m binary reference sources, the addition of N − 1
DACs results in an additional ( N − 1) ∗ m reference sources, thus improving the effective resolution to m + log
2
( N )
, as reported earlier in [40]. However, with the signal being
correlated and the noise being uncorrelated across all DAC paths, there is an N times
109
increase in effective SNR, or an increase in effective resolution to
Effective Resolution = m + log
4
N (5.17)
The above argument is valid only when the bandwidth of interest is limited to the first
Nyquist zone. For beyond-Nyquist signal generation, the integrated noise increases. On including the dependence on signal bandwidth, B
SIG
,
Effective Resolution = m + log
4
N.f
CLK
2 B
SIG
(5.18)
Figure 5.7(a) illustrates the achieved additional resolution, with the filter bandwidth
being restricted to max (0 .
5 f
CLK
, B
SIG
) .
5.2.3 Area and Power Overhead
For the synthesis of a waveform with a given peak-to-peak swing, the currents per DAC path are scaled down by a factor of N . Hence, the total current for a system with N paths is identical to that of a single-path system. Scaling down the current N times is equivalent to achieving an N times lesser area per DAC. As a result, the total area of the N -path DDRF DAC is close to that of a single path DDRF DAC. An additional area and power overhead is created in the generation of the multi-phase clock. There is also the need for additional digital hardware with the challenge of creating interleaved digital signals at GHz speeds, which is less of a concern owing to the continued advances in
CMOS circuit technologies.
5.2.4 Return-to-Zero (RZ) DACs
The use of RZ-DACs can further enhance the performance by compensating for sinc distortion. The RZ hold time-width is incorporated into the length of the interpolation filter in the proposed model. If the DACs’ hold operation return at αT /N , then the length
110
(a)
(b)
Figure 5.7: (a) Additional resolution obtained in an
N
return-to-zero DACs on the scaling function for N = 4 of the interpolation filter becomes α , which when restricted to integer values denotes the number of DACs operating concurrently or the degree of hold-interleaving. In such a case,
111
the scaling function Λ
N
( e jω ) changes to
Λ
α
( e jω
) = e
− jω
( α − 1
2
) sin sin
αω
2
ω
2
(5.19)
It is to be noted that hold interleaving does not affect replica cancellation and merely
accounts for a frequency-dependent scaling determined by (5.19). The effect of
α on the
scaling function for a four-path DDRF DAC is illustrated in Fig. 5.7(b). When all DACs
are concurrently holding their output values, the nulls at π/ 2 , π , and 3 π/ 2 prevent the synthesis of signals at f
CLK
, 2 f
CLK and 3 f
CLK respectively. However, when one DAC is functional at a time (staggered operation), no nulls are present from 0 to 2 π , thus enabling the synthesis of all frequencies until π (or N f
CLK
/ 2 ). Thus, the final zero-order
hold present in the model in Fig. 5.5 determines the overall performance.
5.2.5 Mismatch and Nonidealities
In addition to the challenges posed by a single DAC, interleaved DACs pose challenges of inter-path mismatches like gain mismatch, offset errors and timing mismatch. Although, the interleaved DAC is similar in operation to a time-interleaved ADC, the mismatch effects are quite different.
Offset Mismatch
Offset errors, caused by process variations such as transistor W , L , and V
T mismatches, can be referred to the output of each DAC ( O i
), as observed in Fig. 5.5. Since all DACs
are connected to the same load, the effective offset error is the sum of the offset errors of individual DACs. Unlike time-interleaved ADCs, no tones at f
CLK or any other frequency are generated as a result of the individual path offset errors.
112
Gain Mismatch
In a parallel DAC structure, the gain errors are of less concern as long as the individual
DAC gain errors are identical in all the paths . It is the gain error mismatch between
the DACs that results in the reinforcement of replica spurs. In Fig. 5.5, the individual
DAC gain ( G i
) is modeled preceding the summation node. On comparing with (5.10), it
is seen that the coefficients of the exponentials are not equally weighted when the G i s are unequal, resulting in imperfect cancellation of replicas. The degradation in l th image replica rejection (∆ IRR ( l )) in dB is denoted by,
∆ IRR ( l ) = − 20 log
N − 1
X
G i e
− j
2 πil
N i =0
, l = 1 , 2 , ..., N − 1 (5.20)
Figure 5.8 illustrates the achieved signal-to-image replica ratio (SIRR) as a function of
the variance of the gain error mismatches that are Gaussian distributed across the paths of a four-path DDRF DAC. It is observed that doubling the gain mismatch error increases
the image levels by 6 dB. Figure 5.8 reveals that the mean signal-to-image replica ratio
(SIRR) is guaranteed to be more than 45 dB and 50 dB, for a gain mismatch within ± 2% in the RZ and NRZ modes, respectively. It is also observed that the gain mismatch affects the SIRR in the first image replica more than the second image replica. In addition, the hold interleaving is found to improve the achieved SIRR for both image replicas compared to the RZ mode. The knowledge of gain mismatch pattern may be used to re-order the clocking of the DACs to increase the tolerable gain mismatch by a percent or even more.
Gain compensation for mismatches of greater magnitudes may be achieved by digital data manipulation. Calibration may also be achieved at the circuit level, given a stable reference.
113
(a)
(b)
Figure 5.8: Effect of Gain Mismatch on SIRR (a) RZ mode (b) NRZ mode
Inter-path Timing Mismatch
The DDRF DAC is affected by both jitter and inter-path static timing mismatches. If the jitter in the multiple clock phases exhibit perfect or strong correlation, all DAC outputs are shifted by the same time error. However, inter-DAC timing mismatches are critical,
because they control the amount of replica rejection (Fig. 5.9(a)). In particular, the
inter-DAC timing mismatches should be less than 2% of the clock period to achieve over
114
40 dB of image replica reduction, as illustrated in Fig. 5.9(b). This calls for novel and
robust calibration schemes that can control the timing imperfections in GHz DACs in the order of picoseconds.
Furthermore, the notion of hold-interleaving offers a tremendous advantage in averag-
ing out the manifestations of the timing errors. Figure 5.10 illustrates the achieved SIRR
as a function of the variance of the timing error mismatches that are Gaussian distributed across the paths of a four-path DDRF DAC. The first image replica is observed to suffer more degradation in suppression than the second image replica. It is also observed that the use of hold interleaving improves the achieved SIRR in the presence of inter-path timing mismatches. At 2% of phase mismatch, hold interleaving offers a second replica rejection of 10 dB better than the RZ mode.
5.2.6 Bandwidth limitations
In contrast to time-interleaved ADCs, there exists no bandwidth mismatch in the DDRF-
DAC, as all DACs share the same output node. However, the intrinsic 3 − dB pole of the
DAC must be placed well beyond the maximum desired output signal frequency. Furthermore, the output impedance requirements of the parallel structure should be satisfied until
N f
CLK
. This issue is analogous to the fact that the sample-and-hold does not benefit from a bandwidth relaxation in time-interleaved ADCs.
Other Non-idealities
While the interleaved architecture enables wideband synthesis, great care is to be taken in the design of the output current-combining network. While one of the parallel DACs holds its output, the switching of the other DACs can instantaneously affect its hold operation. This issue of cross-talk between the individual DACs is similar to that between the current cells within a single DAC. However, when interleaving N parallel DACs, the
115
(a)
(b)
Figure 5.9: (a) Inter-DAC timing mismatch affects replica cancellation (b) Impact of
inter-DAC timing errors on replica cancellation
116
(a)
(b)
Figure 5.10: Effect of Timing Mismatch on SIRR (a) RZ mode (b) NRZ mode
rate of cross-talk is N times higher, thus imposing more stringent output impedance and isolation requirements. Since the desired output signal is also updated N times higher, the intrinsic 3 − dB pole needs to be placed well beyond N f
CLK
.
5.2.7 Observations and Design Considerations
The mismatch analysis indicates that the spectral degradation is more stringently dictated by timing mismatch than the gain mismatch, thus calling for robust calibration schemes
117
for timing mismatches. Both gain and timing mismatch are found to affect the SIRR in the first image replica more than the second image replica. This can be intuitively explained by the fact that the cancellation of the first image replica is dictated by four
unique basis functions (from Fig. 5.6 and equation (5.11)), while that of the second image
replica is dictated by only two unique basis functions, where the separation between the basis exponentials of the second replica is larger than those of the first image replica. In addition, hold interleaving improves the achieved SIRR for both image replicas compared to the RZ mode. This is attributed to the fact that the non-linearity error is averaged out across the parallel DACs in a given time window. The parallel structure features relaxed design constraints on the digital logic, since the maximum speed of operation is limited by the intrinsic CLK-Q delay of a flip-flop in a given process. However, there is an increased area for digital logic and multiple DACs. The power consumption of such structures is comparable to that of a single DAC operating N times higher, excepting the additional circuitry required to generate the interleaved data and multi-phase clock.
In this chapter, interleaving phenomena in DACs were analyzed using a general model that captured the effects of both data and hold interleaving. Interleaved samples together with interleaved reconstruction proves to cancel the effect of DAC image replicas, hence providing a bandwidth extension or relaxed post DAC filtering requirements. Holdinterleaving does not hinder replica cancellation and improves the effective SIRR in the presence of mismatches. Although parallel processing helps ease analog/RF specifications or achieve higher synthesis capabilities, stringent requirements on the clocking accuracy need to be met. However, the continuous scaling in process nodes offer the increased speeds to make this a reality at affordable area and power levels.
118
Chapter 6
Architectural Trends in DACs -
A Summary
Specifically in the context of transmitters, the effective bandwidth of the transmitted
signal is determined by the instantaneous bandwidth of the DAC [4].
As mentioned earlier, the motivation to transmit wideband signals at multi-GHz operation places the need for wideband DACs, while maintaining high linearity.
The continued scaling of process technologies like CMOS, GaAs, InP, etc. have offered significant advantages in
terms of speed, power and area [25]. Although BiCMOS technologies are the predominant
choice for high-speed operation, the issues of power, area and cost of integration have led to the wide adoption of CMOS-only processes. To this end, numerous circuit and architectural innovations have been proposed to improve the synthesis bandwidth and the linearity performance of DACs, enabling CMOS designs to compete with their BiCMOS counterparts. In modern DACs, high static linearity is obtained by using special layout techniques, trimming, calibration, dynamic element matching, etc. With the transistor, inherently being a current-mode device, high-speed capability in DACs is achieved using current-steering (CS) DACs. Although the CS DACs exhibit a high degree of regularity that lend themselves to an automated design methodology, the designer is confronted with a complex design space and forced to resort to a custom design flow, as described in
section 4 and [41]. Furthermore, the dynamic performance of CS DACs has been known
119
to fall rapidly with increase in signal frequency and clock rate [8, 18, 32, 41, 42]. This
chapter aims to introduce and summarize some of the well known architectural trends in addressing some of these challenges, so as to improve the synthesis bandwidth and linearity of the DAC.
6.1 Addressing the Grand Challenges
Several design techniques and architectural innovations have been conceived to address
the grand challenges of accuracy, bandwidth and output power [43]. Segmentation is one
of the earliest approaches to enable high-speed DACs with good dynamic linearity [14, 16,
32, 43]. It is seen as critical in minimizing the code-dependent glitches that occur due
to cell-to-cell timing skews. Nevertheless, segmentation increases the number of control signals to the DAC, and makes timing compliance a challenge. Such synchronization issues can occur from spatial variations or mismatch in the switch drivers. Spatial filtering using interleaving and inter-digitating compensate for process gradients and thermal variations,
thus improving intrinsic device matching accuracy [31]. Additionally, IR drops on the
supply lines are reduced by the use of wide and thick metal lines, while power bus variations
from the pins to the desired destination are addressed by binary tree structures [8]. Circuit
techniques like the use of leaker currents and cascoded current cells are proven to increase
the dynamic impedance and thus improve dynamic linearity [8, 41]. The impact of noise
from the bias circuit can be reduced by introducing noise-filtering capacitors. However, these techniques often introduce large parasitic elements thus limiting the DAC speed of operation. This section shall elaborate upon some of the recent trends that push DACs to achieve high accuracy and linearity over large bandwidths.
120
6.1.1 Intrinsic Accuracy DACs
With the move towards newer technologies, a number of process-related limiting factors affect the performance of the DAC, resulting in failure to meet the target specifications.
One of the primary contributors to the variation between the two cells is the threshold voltage ( V
T
) mismatch between transistors [31, 32]. We have already discussed in the
previous chapter that for a given V
T mismatch ( ∆ V
T
), a large V
OD is required to circumvent the mismatches. However with shrink in channel lengths, the reduction in gate oxide thickness limits the maximum voltage that can be applied on the gate of a transistor, while the threshold voltage scales only marginally. Consequently, the available room for a high overdrive voltage is limited. This makes the design of high accuracy converters more difficult, even though scaled technologies provide better matching for equal area
[1][3]. The most-often used way to mitigate the mismatch issue is to realize that the V
T mismatch can be reduced if the transistor area is increased, while maintaining a constant aspect ratio. DACs designed using such techniques of area explosion to circumvent the mismatch issue, are referred to as intrinsic accuracy DACs
[33]. It is shown that a 10-bit
converter design will have a 99.7% yield specification if the standard deviation in error is
less than 0.5% [44]. In order to relax the transistor area requirements, a segmentation
topology is adopted such that the mismatch constraint is applied to the highest binary
cell [32, 33]. Nevertheless, the large area requirements on these DACs lead to huge ca-
pacitances, and impact the dynamic linearity of the DAC, to the extent that cascoding is
6.1.2 R-2R DACs
Although the binary architecture benefits from limited number of control signals, the large ratios between the current cells in binary DACs not only impose stringent matching requirements, but also result in significant timing mismatches between the cells. Unary
121
DACs, on the other hand, have liberal matching requirements and their current cells are identical in timing. However, the exponential growth in the number of control signals makes timing compliance a challenge.
The benefits of the two architectures can be combined by the use of an R-2R ladder network for the output stage, as depicted in Fig.
N -bit R-2R DAC comprises N current cells, each carrying a current 2 N − 1 I . A corresponding array of N switch pairs is used to steer the current into the appropriate output arm, in response to the N -bit binary code. Instead of connecting the current cells directly, an output R-2R ladder stage is used. The identical current cells, similar to that of the unary architecture, impose relaxed matching requirements and similar switching times, while the use of the R-2R ladder network maintains the same number of control signals as the binary architecture. The regularity and modularity of this architecture thus enables the design of area-efficient DACs. However, use of the MSB current in all the
DAC cells significantly increases the core current consumption in high-resolution DACs.
These can result in large voltage swings on the output node that can eventually push transistors into the triode regions, thereby degrading linearity. Moreover, the output resistive network results in the DAC to be confronted with a unique output time constant for every binary code. Such code-dependent output time constants lead to code-transition timing glitches, and therefore impact the dynamic linearity. As a result, this technique is
often implemented only in the binary segment of a segmented architecture [45, 46].
6.1.3 High-Frequency Synthesis by Replica filtering
As discussed earlier, the synthesis of a signal in the first Nyquist zone is accompanied by a synthesis of a replica in every other Nyquist zone. One of the earliest and simplest techniques to synthesize high frequency signals beyond the first Nyquist zone relied on
band pass filtering the inherent image replica components [47]. However, replica filtering
in the higher Nyquist zones is accompanied by the demand for high selectivity filters.
122
Figure 6.1: Conception of an N -bit R-2R DAC
The design of such filters on-chip is limited by the quality of passives on that process.
Thus, there exists a limitation in the highest frequency that can be filtered. In addition, the amplitude of the replicas in the higher Nyquist zones is reduced owing to the sinc attenuation. This translates to very low power outputs or the need for linear post-DAC amplification, which is proven to be costly in terms of power and speed.
123
6.1.4 Return-to-zero (RZ) DACs
The power of the signals in the higher Nyquist zones can be improved by modifying the hold operation, such that the sinc nulls are pushed to higher frequencies. Return-tozero (RZ) DACs achieve an improvement in the amplitude of the high-frequency spectral copies, by introducing an RZ transition in the middle of the hold period, as illustrated in
Fig. 6.2(a) [48]. If the transition of the DAC pulse (
T
RZ
) occurs at D.T
CLK
, then the frequency response of this hold waveform is given by
H ( f ) = sin πD f f
CLK
π f f
CLK f exp − jπD f
CLK
(6.1)
As depicted in Fig. 6.2(b), RZ DACs with return times (TRZ) at half and quarter of the
clock period exhibit an output sinc response that have nulls at every 2 f
CLK and 4 f
CLK respectively, thus allowing the capability to synthesize signals in the higher Nyquist zones.
However, the flatness in the DAC’s output response, due to the increase in replica power in the higher Nyquist zones, is achieved by a corresponding decrease in power in the lower
Nyquist zones. Furthermore, the output rise/fall times need to be met with respect to the effective ON period of the DAC pulse-width ( D.T
CLK
), making the design of RZ DACs more cumbersome than non-return-to-zero (NRZ) DACs.
Classical RZ has been implemented in the analog domain by globally shorting across the differential outputs of the DAC. Such an approach, also referred to as voltage RZ (VRZ), is known for its simple implementation by using a return switch ( M
R
), as illustrated in
Fig. 6.3(a) [49]. Ideally, in the return phase, the two output nodes are brought to the
same common-mode voltage, referred to as “return voltage”. However, the finite ON resistance of M
R
, results in a voltage difference between the two output nodes. This voltage difference is a function of the current that is being sunk in each output arm. As a result, the mismatch in return voltages between the two output nodes is code-dependent
124
(a)
(b)
Figure 6.2: (a) Return-to-zero Hold Waveform (b) RZ hold response
125
and is directly proportional to the synthesized waveform. If the DAC current is given by
I
DAC and R
ON,M
R represents the ON resistance of the return switch, the mismatch in return voltages can be expressed as
∆ V
RZ
= I
DAC
× R
ON,M
R
(6.2)
Clearly, this indicates a second order distortion, that exists even if the two outputs are perfectly balanced. In addition, the use of large device sizes in an attempt to reduce the
ON resistance, leads to an increase in the output load capacitance, eventually degrading dynamic linearity.
(a) (b)
Figure 6.3: (a) Voltage-mode RZ (b) Current-mode RZ
To alleviate the limitations in the voltage-mode RZ, the return switches can be imple-
mented locally within each current source cell, as shown in Fig. 6.3(b) [48, 50]. A return
126
switch network (RSN), comprising transistors, M
R 1 through M
R 4
, is employed within the
DAC cell to commutate the cell current to a common-mode arm in the return phase. As long as the RSN switches operate between cut-off and saturation modes, the structure is fairly immune to the finite ON resistance of the switches. Current mode RZ also acts as a deglitcher by capturing the data after it has switched. Since the RZ action is implemented within the cell, the size of each cell will grow and in turn result in larger routing capacitances. In addition, there exists the possibility of inter-cell RZ timing mismatch in addition to the inter-cell data timing mismatch.
6.1.5 Interpolation DACs
Another means for high-frequency synthesis and to address the replica issue is the inter-
polation DAC [51], as depicted in Fig. 6.4. It uses low sample-rate data that are fed into
a digital interpolation filter and eventually fed to the DAC core. The interpolation filter is designed to cancel or suppress the image replicas, thereby extending the bandwidth.
Although, the speed of the digital interface is relaxed, the DAC still remains to operate at the update rate. In the case of analog interpolation, the desired waveforms are created using micro-stepping methods, or using RZ DACs that perform an analog equivalent of zero padding.
6.1.6 RF DACs
Recent attempts have been made to combine the DAC and mixer functionality into a
single topology to improve the overall system linearity and power consumption [52]. This
DAC/mixer construct, referred to as the RF-DAC, is depicted in Fig. 6.5(a). A mixer
switch pair is placed on top of the DAC cells such that the local oscillator (LO) directly modulates the DAC output. The current-to-voltage-to-current conversion between the
DAC and mixer, which introduces distortion, is completely removed. However, the up-
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Figure 6.4: Interpolation DAC conversion of the image-replicas and harmonic mixing of these replicas with the local
oscillator, makes the post-RF-DAC filtering a daunting task. Reference [53] employs
harmonic rejection mixers embedded into the DAC to suppress the harmonics caused by the mixer circuit, thus achieving greater than 70 dB of harmonic rejection. However, this technique greatly relies on the matching between the transistors that comprise the harmonic mixer.
Noise-shaping RF DACs
Noise-shaping ( ∆Σ ) techniques have also been employed in RF-DACs to improve the spectral quality of the DAC signal to obtain higher in-band SNRs, at the expense of
large out-of-band noise [54, 55](Fig. 6.5(b)). The delta-sigma modulator uses lesser
number of bits at the cost of increased rates of operation. However, the improvement in switching capabilities as processes emerge, makes this solution feasible to synthesize
digital signals at gigahertz frequencies. Fig. 6.5(c) illustrates the output spectrum of
a 5.25 GHz RF-DAC fed using a 2 nd -order, 3-bit ∆Σ modulator. It is observed that
128
(a) (b)
(c)
Figure 6.5: (a) A simplified block diagram of an RF DAC (b) Noise-shaping RF DAC (c)
Noise-shaping RF DAC Output using 2 nd
-order, 3-bit ∆Σ Modulator the ∆Σ noise starts rising rapidly beyond the bandwidth of the modulator, eventually violating spurious emission requirements. The increased out-of-band ∆Σ noise and the spurious emission specifications together place stringent filtering requirements after the mixer, hence limiting the instantaneous bandwidth of operation to well below 100 MHz.
Reference [54] integrates a high-Q passive LC bandpass filter to perform filtering of the
out-of-band spurious and noise. However, the feasibility of this approach depends on the
filtering requirements and the limited Q of on-chip passives. Alternatively, reference [55]
129
embeds a semi-digital FIR reconstruction filter in the digital-RF interface. The limitation of this approach lies in the need for large number of taps to obtain sufficient attenuation.
Recently, a highly digital RF-DAC based transmitter exhibiting high linearity was proposed
in [56]. The work demonstrated multi-band operation in 3G using a polar architecture, in
which separate phase and amplitude paths were derived from the baseband digital signal.
The phase signal modulates a digital controlled oscillator (DCO) and later acts as the
LO signal, while a 14-bit amplitude signal is oversampled and then applied to the DAC current cells. A high dynamic range DAC with no noise-shaping was designed to relax the filtering requirements and obtain -160 dBc/Hz far-off noise specifications. However, there still exists the issue of image replicas in this structure, which limits the ability to further extend the bandwidth of operation.
Global vs. Local Mixing
Several linearity limitations exist in the RFDAC structure, the most important of them
being the mixing locality [57]. Realizing that the RFDAC is an array of current cells, the
mixing operation may be performed globally after the DAC currents are combined. This is
referred to as global mixing and illustrated in Fig. 6.6(a). Another approach to realize the
up-conversion is to perform mixing locally within each cell and eventually current combine
to obtain the final output, as depicted in Fig. 6.6(b). Such an approach is referred to as
local mixing. Both these techniques have their own pros and cons. Global Mixing results in the need for large LO switches, thus limiting the output bandwidth. Furthermore, the mixing conversion gain is dependent on the DAC current. This results in signal-dependent mixing, besides any signal/code-dependent phenomena that may occur within the DAC core. Current-bleeding techniques may be incorporated to reduce any signal-dependent mixing, but this increases the overall mixer current, eventually causing output impedance distortion. Local mixing on the other hand, uses a mixer for each DAC cell, resulting
130
in increased area. In the simple example of a unary DAC, all DAC cells carry identical currents and therefore identical mixing gains. However, the spatial separation of the mixer cells and the presence of process variations can cause inter-cell LO timing mismatches that can severely impact the overall performance
(a) (b)
Figure 6.6: (a) Global mixing in RF DACs (b) Local mixing in RF DACs
6.1.7 Interleaved DACs
Another emerging architecture using time-interleaving topologies was proposed for high-
frequency beyond-Nyquist synthesis [39, 58]. As mentioned earlier, a time-interleaved DAC
comprises an N -path array of DACs fed with interleaved signal samples and operating at interleaved instants of a clock period. The outputs of all DACs are connected together with their hold periods overlapping, to yield the effective output signal. The output of such a construct has all replicas canceled, except for those around every N f
CLK
, as
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illustrated in Fig. 5.6. The use of interleaved samples also enables a beyond-Nyquist
synthesis capability, while maintaining replica cancellation. Another interesting feature of this architecture is its nonlinearity suppression that is achieved by simple digital phase-
shifting of the samples [39]. It is important to note that every DAC is operational at
all times; i.e. while one of the DACs is updating its output, the other DACs force their previously held values. This concept of hold and data interleaving was elaborated upon in
[58] and proven to not hinder replica cancellation, while enabling beyond-Nyquist synthesis.
Hold-interleaving is also shown to improve the replica suppression in the presence of gain
and timing mismatches in [58], making it suitable for high-bandwidth DACs in newer
process technologies.
Figure 6.7: Power Mixer Array
6.1.8 Power DACs
The concept of a power DAC/mixer has recently evolved as an extension of the RF-
DAC into the PA domain. In such a construct, as illustrated in Fig. 6.7, a high power
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transistor is used as the switching device and thus accomplishes both current commutating and current combining. However, the inherent trade-off between speed ( f
T
) and power capability (breakdown voltage) for semiconductor devices creates a maximum achievable bandwidth that is power-limited. Parallel arrays of such DAC and/or mixers, proposed in
[59, 60], was shown to cancel mixer nonlinearities by use of phase-shifted input signals
and corresponding phase-shifted LO signals. Such a polyphase mixer has been shown to
relax the mixer linearity requirements [61].
A brief summary of innovations to improve the speed and accuracy was presented in this chapter. While there is a continuous effort in pushing high-resolution DACs into the GHz regime, process variations ultimately limit the achievable performance metrics. Although the design of an intrinsically accurate DAC significantly mitigates the effect of these variations, the area requirements for higher resolution DACs are prohibitively large. As a result, excessive parasitic loading and timing variations arise that limit the operating speed and spectral purity of the DAC. In contrast, a digitally-assisted architecture combining less accurate, smaller analog components with additional digital calibration or compensation circuitry reduces the total effective area of the DAC while meeting the target specifications.
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Chapter 7
The Bit and its Character
While there exists innovative trends in designing high-speed DACs, we must realize that we have been cooking a new recipe in the same pot for all these decades. It’s about time we bought ourselves a new cooking pot!
Generally speaking, ADCs have received significantly more attention than DACs; this
is reflected not only in the large number of ADC publications
cantly lesser amount of material devoted to DACs in classrooms across the world. The fundamental science behind D/A conversion has traditionally been thought to be similar to
ADCs that were treated using a stochastic approach. However, we note that while ADCs receive a stochastic input comprising the desired signal and the ambient noise, DACs convert a deterministic (known apriori) digital stream of bits into a real-world signal. In essence, a stochastic approach to analyze D/A conversion is rather unnecessary and a more deterministic approach is well suited. Such a methodology shall serve to effectively understand the fundamental limitations in a DAC.
For example, if we consider a DAC with 6-bits of resolution, it is well known that the addition of an LSB improves the SNR by 6 dB, and the SDR by 9 dB. On the other hand, if we knew the contribution of this LSB as a standalone entity, we could engineer it in peculiar ways, such that we obtain more than 9 dBs of SDR improvement. This
20 As of July 21, 2013, IEEE Xplore shows 2897 publications on ADCs, compared to only 919 in DACs, over the last 60 years, i.e. 3:1.
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methodology is of immense importance, as it shall serve to develop DACs with spurious
performance, far superior than its fundamental limit. While chapter 3 speaks about the
fundamental limitations that induce spurs at the output of a DAC, this chapter shall aim to assess the contribution of each bit and develop accurate expressions for it. The discussion in this chapter is also applicable to ADCs.
7.1 Generic representation of a bit
Let us first take a step back and see how the bits are generally extracted. There are two primary schools of thought to obtain the bit representation: The Binary Search algorithm and the Flash algorithm.
Binary Search Algorithm The Binary Search is a well-known algorithm to resolve the quantized representation. In the circuits area, it is often known as the Successive Approximation algorithm and is the core idea behind the design of successive approximation
ADCs. Let us consider a signal value, x = 0 .
38 . The signal is at first compared to a known decision boundary. The outcome of this comparison yields a bit, and a new decision level to make the next comparison. To make things clear, let us consider a signal value, x = 0 .
38 . Given that the bounds of the quantizer are ± 1 , x is compared to a decision boundary of 0. Since x > 0 , the outcome is denoted by d
1
= 1 . The signal, x is then compared to a decision boundary of 0.5, whose outcome is d
2
= 0 . As a result, the next comparison is made with 0.25, and so on. After five comparisons, we obtain the first five
MSBs of the equivalent quantized representation, 10110, or equivalently 22. This process
is illustrated in Fig. 7.1(a), where the blue arrows indicate the decision boundaries at each
comparison. It is observed that the i th bit can be resolved only if its decision boundary is known, which in turn is set by the ( i − 1) th bit. This concludes that the binary search algorithm does not permit us to uniquely identify a bit, without the knowledge of any
135
other bit.
(a)
(b)
Figure 7.1: (a) Binary search algorithm (b) Flash algorithm
136
Flash Algorithm
way to resolve a signal is to simply denote
the index of the LSB box as the quantized representation. In our example in Fig. 7.1(b),
0.38 lies in the 22 nd box, hence the decimal representation being 22. In order to obtain the bits, the 22 (which is obtained as a thermometric code) needs to be encoded to yield the binary representation. Again, this process yields the i th binary bit, only using the knowledge of the other (unary) bits.
The question now arises, as to whether a bit can uniquely be obtained. We have
already discussed in section 2.1 that in a quantizer grid, the colors beneath the vertical
line drawn through the abscissa of x represent the binary bits, implying each bit can be estimated directly. But the question is: Can we really obtain a closed-form expression to any bit in a quantizer?
Following the convention described in section 3.3, we shall restate the conversion from
bits-to-signal as, y ( t ) = Q
N
( x ( t )) =
N
X
1
2 i d i ( t ) i =1
(7.1) where, the signal, x ( t ) , is bounded within ± 1 , the individual bit waveforms are represented
“MSB-first” as d
1
( t ) , d
2
( t ) , and so on, and take values +1 or -1. Our goal is to obtain the various d i
( t ) as a function of x ( t ) . A critical challenge in such a description is that the expressed bit can only take two levels (+1 and -1, or equivalently 0 and 1.); implying that a lossless mapping from an infinite resolution signal to a two-leveled bit is to be carried out. This process may be coined as the “it-by-bit engineering”. Unlike a Fourier transform pair that maps variables across time and frequency, it must be noted that the bit mapping is performed across the voltage and the logic domains. A closed-form solution for this mapping was initially attempted using recursive induction and fractal analyses. However, these methods failed to yield a closed-form expression for each bit, independent of one or
21
This also turns out to be a neat and efficient technique, when considering implementation issues
137
many other bits. A breakthrough to this challenge happened when it was observed that the mapping from infinite resolution signal to a weighted bit waveform was within the same domain (voltage, current or charge), i.e. the bits influence the final output along with their binary weights. Thus, we shall denote “weighted bits” expressed as d
( w ) i
( t ) =
1
2 i d i
( t ) .
(7.2)
Realizing that d
( w )
1
( t )
is the output of a 1-bit quantizer and using (3.17), it can be
expressed as, d
( w )
1
( t ) = Q
1
( x ( t ))
= x ( t ) + ∆
1 n = ∞
X nπ n =1
1 sin
2 πnx ( t )
∆
1
Given that ∆
1
= 1 , the above equation simplifies to, d
( w )
1
( t ) = x ( t ) + n = ∞
X n =1
1 nπ sin (2 πnx ( t ))
(7.3)
(7.4)
(7.5)
In order to determine the representation of the 2 nd MSB, let us first express the output of a 2-bit quantizer as, y
2
( t ) = x ( t ) + ∆
2 n = ∞
X
1 nπ
1 n =1 n = ∞
X
1 y
2
( t ) = x ( t ) + sin
2 πnx ( sin (4 πnx ( t )) t )
2 nπ
∆
2 n =1
(7.6)
(7.7)
Using equations (7.1) and (7.2), the output of a 2-bit quantizer may be equivalently
written as, y
2
( t ) = d
( w )
1
( t ) + d
( w )
2
( t ) (7.8)
Now, combining equations (7.5), (7.7) and (7.8), we can express the weighted second
138
MSB as d
( w )
2
( t ) = d
( w )
2
( t ) = n = ∞
X
1 sin (2 πnx ( t )) n =1 n = ∞
X
2 nπ
1 nπ sin (2 πnx ( t )) [cos (2 πnx ( t )) − 1] n =1 sin (4 πnx ( t )) − n = ∞
X nπ n =1
1
(7.9)
(7.10)
Similarly, d
( w )
3
( t ) = n = ∞
X
1
2 nπ sin (4 πnx ( t )) (cos (4 πnx ( t )) − 1) n =1
(7.11)
For all bits except the most-significant, we can obtain a generalized closed-form expression as d
( w ) k
( t ) = n = ∞
X
1
2 k − 2 nπ sin 2 k − 1
πnx ( t ) cos 2 k − 1
πnx ( t ) − 1 k > 1 (7.12) n =1
It is reminded that no prior assumptions have been made on the temporal characteristics of x ( t ) ; i.e. it could be a DC value, a linear ramp, a sinusoid, multi-tone, or even a chirp.
x ( t ) simply needs to be bounded between ± 1 . Given that the DAC is composed of a binary array of cells, each of these weighted-bit equations represent the signature of the output of each cell in a DAC. The closed-form expressions for the bit waveforms enable a detailed study on the performance of DACs with mismatches (both intentional
and non-intentional). This will be described in a later section (Sec. 7.5).
Figure 7.2(a) illustrates the first five bit waveforms for a sinusoidal signal, as obtained
from the developed equations. The ripple seen on these bit waveforms, is attributed to
the finite number of summation terms
. The sum of the weighted bits must yield the
output sinusoid. Figure 7.2(b) depicts the conformity of the developed equations to the
expected output of a quantizer, further validating the equations.
22
The index n was allowed to run only over 1000 summations.
139
(a)
(b)
Figure 7.2: (a) Waveforms for first five MSBs (b) Comparison of the sum of the weighted
bits to the expected output
7.2 Non-linearity of a bit
Having developed closed-form solutions for each weighted bit in a DAC (or any quantizer), we shall delve into estimating how each bit contributes to the overall DAC performance.
140
Assuming a sinusoidal tone, sin ( ωt ) , the weighted MSB can be expressed as, d
( w )
1
( t ) = sin( ωt ) + n = ∞
X nπ n =1
1 sin (2 nπ sin( ωt ))
Using the Jacobi-Anger expansion, the above equation reduces to,
(7.13) d
( w )
1
( t ) = sin( ωt ) + n = ∞
X nπ n =1
2 l = ∞
X
J
2 l +1
(2 nπ ) sin ((2 l + 1) ωt ) l =0
= sin( ωt ) +
2
π l = ∞
X sin ((2 l + 1) ωt ) n = ∞
X
J
2 l +1
(2 nπ ) n l =0 n =1
(7.14)
(7.15)
It is important to realize that the MSB comprises only the odd harmonics of the signal, with the harmonics weighed by Bessel functions.
Similarly, the next weighted bit, d
( w )
2
( t ) can be determined as, d
( w )
2
( t ) = l = ∞
X sin ((2 l + 1) ωt ) n = ∞
X nπ l =0 n =1
1
[ J
2 l +1
(4 nπ ) − 2 J
2 l +1
(2 nπ )] (7.16)
Again, this equation emphasizes the fact that the second MSB also does not contain even harmonics of the signal. Using the same approach, the weighted bit, d
( w )
3
( t ) can be shown to be, d
( w )
3
( t ) = k = ∞
X sin ((2 l + 1) ωt ) n = ∞
X
2 nπ k =0 n =1
1
[ J
2 l +1
(8 nπ ) − 2 J
2 l +1
(4 nπ )] (7.17)
By induction, the k th weighted bit can be expressed as, d
( w ) k
( t ) = l = ∞
X sin ((2 l + 1) ωt ) n = ∞
X
2 k − 2 nπ l =0 n =1
1
J
2 l +1
(2 k nπ ) − 2 J
2 l +1
(2 k − 1 nπ )
(7.18)
Figure 7.3(a) illustrates the normalized levels of the harmonics for different MSB
indices. It is seen that the MSB represents a significant portion of the signal ( ≈ 65% ).
It is also observed from Fig. 7.3(b) that the third harmonic contained within each bit is
not necessarily the most dominant of all. For instance, the second bit has more energy in
141
the fifth harmonic than in the third. The signal energy in addition need not be dominant within each bit, as in the case of the third MSB, where the eleventh harmonic is higher than the signal component itself!
Fig. 7.4 represents the effect of adding one MSB at a time. It is seen that the
fundamental signal power increases, similar to what was observed in Fig. 3.7. It is also
seen that the overall harmonic level progressively increases or decreases, depending on the phase of the harmonic of each bit. In addition, the third harmonic is observed to be the
dominant and agrees with the results obtained in Fig. 3.8.
7.3 Sampling a bit
A closer look at Fig. 7.2(a) reveals that the individual bits exhibit a signal-dependent
pulse-width modulation. Let us observe this even closer. Shown in Fig. 7.5(a) is an
equivalent cartoon depiction of the bit waveforms corresponding to a sinusoidal signal, which reveals that the width of these pulses are dependent on the slope of the signal.
Let us now introduce the concept of sampling into this picture (Fig. 7.5(b)), where the
unsampled waveform is shown in grey and the sampled waveform is shown in red. While the sampling theorem states the need to sample a signal more than twice its maximum rate, the 2x criterion may be insufficient to resolve the fine pulse widths of the lower bits in a quantized signal. Note that sampling an input sinusoidal signal is different from
sampling the fine pulses in the high resolution bits. Even at 10x sampling (Fig. 7.5(b)),
the very fine pulses from the third bit onwards are lost due to sampling. Such a loss of pulse information due to sampling strongly implies the degradation in linearity close to
This entails two key findings:
• Finer resolution bits contain high levels of activity, i.e. fine pulse-widths.
Inaccurate capture of this activity due to sampling causes a loss in linearity, when either res-
142
(a)
(b)
Figure 7.3: (a) Harmonic levels in each bit (b) Magnitude of the harmonic levels in each
bit
143
Figure 7.4: Effective fundamental and harmonic levels as a function of the number of
MSBs used in the representation olution or the input signal frequency relative to the Nyquist, increases. In order to capture these fine pulses, a finer sampling is required. Specifically, the pulse-width of a bit is dependent on the slope of the signal waveform: higher the slope, finer the pulses. For a sinusoidal signal, the pulse-widths may be obtained by straight-
forward math and depicted by the red curve in Fig. 7.6. The minimum pulse-width
of the fifth bit is 1/100th of the signal period. This implies that the minimum sampling frequency required to resolve five bits is 100 times the signal frequency, as denoted by the blue curve. If this sampling criterion is not met, it results in a loss of information in time, that translates to an addition of unnecessary information in frequency, i.e., increase in harmonic activity and affecting the SDR. In other words, as the signal frequency approaches the Nyquist limit, the signal-to-distortion ratio
degrades, which is the same result as obtained in Fig. 3.11.
144
(a)
(b)
Figure 7.5: Analog-to-digital-analog conversion: (a) Without sampling in time (b) With
sampling in time
• At Nyquist ( f
CLK
/2), there will be only two samples and the waveform generated here would simply be a high-low signal; i.e. the output of a DAC will always be a
square-wave, no matter what the resolution is, and has a linearity of 9 dB only 23 .
To summarize, the minimum sampling frequency for quantized signals is much higher than that suggested by the sampling theorem. Any violation to this minimum bound results in a sacrifice in linearity. While the study here was conducted on a single-tone, for any arbitrary signal, the exact minimum bound on sampling frequency can be obtained by assessing the minimum pulse-width of all bits.
23
Fourier analysis of this square wave reveals that the highest harmonic (3rd) is 9 dB below the fundamental, implying an SDR of 9 dB.
145
Figure 7.6: Minimum pulse-widths and sampling criterion for bits of a sinusoidal waveform
7.4 Bit Mismatches
While there are several metrics used to quantify the static and dynamic metrics of a data converter, the approach used to determine them are not quite related. For instance, temporal and statistical tests are conducted to determine the static metrics (INL, DNL, gain error, etc.), while spectral tests are performed to estimate the dynamic metrics (SNR,
SFDR, etc.). Particularly, while there exists a correlation between the static and dynamic metrics, no accurate relationships have been developed so far. Upon introducing a scaling factor, alpha k
, in the developed bit equations, we can conveniently describe DNL or intra-DAC amplitude mismatches between the bit cells. Thus, the bit equations under the influence of mismatches can be written as d
( w ) k
( t ) = α k n = ∞
X
2 k − 2 nπ n =1
1 sin 2 k − 1
πnx ( t ) cos 2 k − 1
πnx ( t ) − 1 k > 1
(7.19)
Specifically, α k describes the mismatch coefficient of the k th bit. For instance, α k
= 0 .
9 implies than there is a -10% error in the binary weight of the k th bit, while α k
= 1
146
indicates no error. Thus an array of α k describing the error in the weighting factor of the bits in a DAC can be used to represent DNL (or INL). More specifically, the distribution of
mismatch coefficients can also be used to accurately predict the achievable SDR. Fig. 7.7
illustrates the distribution of the achievable SDR for mismatch levels of 1%, 5% and 10% in the binary-weighted bits. It is seen that as the amount of variation in binary-weighted
bits increases, the mean and variance of the SDR degrades
from the expected value of
45 dB. This model thus facilitates in obtaining accurate relationships between the static
linearity metrics and the dynamic linearity metrics. The significance of (7.19) also lies in
the fact that it enables a joint analysis of mismatches and signal that can improve the achievable linearity. To explain this effect, let us consider the spectrum of a low-frequency
test conducted on a 5-bit DAC with and without mismatches, as depicted in Fig. 7.8. The
legend indicates the weights of the bits for the ideal DAC, while the percentage deviation in the binary weights is denoted for the mismatched DAC.
For the chosen mismatch coefficients, it is observed that the spur levels at most frequencies have increased. Interestingly some of the spurs in the mismatched DAC are at levels far below than in the ideal DAC. This raises the question: Can we engineer the DAC in such a way that the reduced spurious levels are obtained at pre-determined locations?
Stated otherwise, Can a 5-bit DAC be engineered such that it offers over 5-bits of spectral performance with regard to the desired harmonic locations? Such a phenomena is already
observed in some of the cases that achieve an SDR of higher than 45 dB in Fig. 7.7; we
would simply want to achieve this deterministically!
7.5 DACs with intentional bit mismatches
The benefits of intentionally engineering the mismatch in binary weights can be studied by first considering a simple DAC with a known resolution. More specifically, the DAC is
24 There are 9 test cases that achieve SDR higher than the expected level of 45 dB. This will be explained shortly.
147
Figure 7.7: The effect of mismatch in binary weights upon the achievable SDR for 1000 test cases
148
Figure 7.8: DAC output spectrum with and without mismatches. The legend indicates the weights of the bits for the ideal DAC, while the percentage deviation in the binary weights is denoted for the mismatched DAC.
modeled using a bit-by-bit model, as shown in Fig. 7.9. The bit waveforms,
d k
, are binary weighted and combined to yield the final stair-step quantized signal, x
Q
. The expected
signal-to-distortion ratio of the 5-bit DAC, shown in Fig. 7.9 is 45 dB, based on the
analyses presented in section 3.3.1. Let us now introduce a predetermined mismatch of
10% in the LSB, and an unknown mismatch of x % in the second LSB, as depicted in Fig.
7.10. We shall now study the effects of varying
x and how this affects the overall distortion performance. Upon varying x from 0 to 50%, we see that there exists specific values of deviation that results in significant suppression of the harmonics. This is explained through
Fig. 7.11 that depicts the signal to third (fifth and seventh) harmonic levels as a function
of the deviation in binary nature of the second LSB. The signal-to-third harmonic level increases to about 89 dB, for a second LSB mismatch of roughly 17%. In other words, a
149
Figure 7.9: Mixer-based model for a 5-bit DAC
5-bit DAC can provide up to 89 dB suppression in the third harmonic, if the binary weights are deliberately manipulated. In the event of mismatches in the accuracy of these weights, the 5-bit DAC can conveniently provide over 70 dB suppression in the third harmonic for
15 to 18% of deviation in the second LSB weight. The same 5-bit DAC can provide up to
90 dB HD5 suppression for roughly 24% mismatch. In cases where both third and fifth harmonic suppression are to be considered, over 6-bits of effective resolution is obtained when the binary mismatch is set to about 20%. Tests were also conducted on an 8-bit
DAC with a 10% LSB mismatch and a varying mismatch for the second LSB. Results reveal that the distortion curves to move closer. This suggests that we can comfortably achieve a 10-bit performance with a 17% mismatch in the second LSB. This result is
At times, manipulation of a binary cell current can affect the current magnitude of
150
Figure 7.10: Mismatched mixer-based model for a 5-bit DAC another binary cell. For instance, the current through a binary cell can be routed through another cell, thereby creating two binary cells with a positive and negative mismatch in binary weight.
Case 1
: Let us consider a simple case as depicted in Fig. 7.13. A fixed error of 10%
is assumed on the LSB cell (corresponding to d
8
) of an 8-bit DAC. The second ( d
7
) and third LSB ( d
6
) cells have opposing variation in their binary weights, say − x % and + x %, respectively. Upon varying x
, we observe from Fig. 7.13 that there exists a significant
range of x from 9% to 10.5%, that guarantees over 90 dB suppression until the 7th harmonic.
Case 2 : In cases where a current of fixed magnitude is “routed” from a binary cell and fed into another, the percentage mismatches are opposing in nature, but not equal in magnitude, owing to the ratio of the binary weights. For instance, a deviation of + x %
151
Figure 7.11: Improvement in distortion levels with binary mismatches in a 5-bit DAC on the second LSB cell ( d
7
) with a current magnitude of 2 I , is equivalent to an addition of a current 2 x/ 100 . When this current is routed from the third LSB cell ( d
6
), it results in a subtraction of 2 x/ 100 current, which is equivalent to a − 0 .
5 x % of deviation on the third LSB. This is a more realistic case, which when evaluated yields 90 dB suppression until the 7th harmonic, for x in the range of roughly 46% to 50%, as observed in Fig.
7.14. It must be noted that we have still assumed the 10% mismatch on the LSB cell.
Both case 1 and case 2 are strong examples of calibration by error induction, i.e. an error in the binary weight is introduced on the second and third LSBs to mitigate the effect of the error on the LSB, rather than correcting the error itself.
Case 3 : An interesting case of deliberately engineering mismatches in the binary cells, is by simply configuring the DAC to be non-binary in nature. For instance, let us consider
case 2 without the 10% mismatch on the LSB, as depicted in Fig. 7.15. At roughly
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Figure 7.12: Improvement in distortion levels with binary mismatches in an 8-bit DAC x = 60 %, the 8-bit DAC offers up to 90 dB suppression (ENOB = 10) up until the 7th harmonic. This implies that the binary weights on the first four LSBs are 1 : 3 .
2 : 2 .
8 : 8 , instead of 1 : 2 : 4 : 8 . Interestingly, this is a non-monotonic 8-bit DAC that performs on par with an ideal 10-bit DAC.
The key takeaway of this discussion is that the DACs may be intentionally engineered to be non-binary in nature. We have already seen in chapters 3 and 4, that although high resolution DACs are designed to provide high-linearity, several practical challenges limit the achievable linearity to well below the expected levels. However, the practical challenges exacerbate the problem only in high resolution designs. If we were to engineer an 8-bit
DAC to achieve a 10-bit effective resolution in the desired application bandwidth, this can lead to implementations that will be the cornerstone of future D/A converters. While this study is at a fairly simple level, it offers a deep insight into bit processing and opens the
153
Figure 7.13: Case 1 - An 8-bit DAC with mismatch on two bits with equal and opposing percentage deviation
154
Figure 7.14: Case 2 - An 8-bit DAC with mismatch on two bits with equal and opposing deviation in current magnitude
155
Figure 7.15: Case 3 - An 8-bit DAC with non-binary weights on the second and third
LSBs
156
doors to a new paradigm in D/A conversion. These re-engineered DACs are analogous to the analog-to-information converter in compressive sensing systems.
Furthermore, compressive aspects are more appropriate in transmitters/DACs, than in receivers/ADCs, since the information to be transmitted is known apriori.
157
Chapter 8
Conclusion
This dissertation aimed to provide the reader with a holistic study of digital-to-analog conversion as a process and as a realization. To the author’s knowledge, this thesis is the first to provide generalized closed-form expressions for each bit, while being applicable to an arbitrary waveform. Based on these representations, a fresh look at the distortion characteristics and their spectral dependence was provided.
An overview of practical challenges that affect the DAC’s static and dynamic performance was also provided. The complexity of the DAC design space, while perceived to be a simple array construct, forces a custom design flow. The technology-related challenges were discussed by using a quad-design space approach. The DAC design space was classified into four major parameters: device noise, output impedance, signal swing and switching speed. The reader was then introduced to the need for segmentation as a result of process variation and circuit limitations. A review of architectural and circuit techniques in the context of high-performance DACs to aid in circumventing various technological challenges was presented. Specific to bandwidth enhancement in DACs, a universal model for analyzing time-interleaved DACs was developed and presented, to study all classes of
DAC interleaving - data, time and hold. This model facilitates the designer in analyzing various overheads before choosing the desired architecture.
158
8.1 What next?
The need for high-resolution and high-speeds have kindled the interest towards RF-DACs and interleaving, that are foreseen as promising for future ultra-wideband applications.
Furthermore, the reduction of line-widths in III-V technologies, makes them competent
with CMOS as a candidate for the design of GHz DACs [13, 62]. Nevertheless, the
long-recognized fundamental limitations associated with process variations still remain a limiting factor in the implementation of high-performance DACs.
Calibration primarily leverages upon mathematical and signal processing techniques to correct for circuit imperfections. Calibration of a system parameter typically requires the ability to sense the initial conditions of the system. Moreover, the calibration process can either take place as a stand-alone phase, where the normal mode of system operation is interrupted, or continuously while normal operation is taking place. While there exist
several methods to accurately measure the mismatches [42, 63–75], the achievable perfor-
mance post calibration is limited by the accuracy of the calibration circuitry. Furthermore, calibration approaches specifically address the low-frequency performance of the DAC, and limit the effective resolution bandwidth to well below the Nyquist. Besides, calibration has been conventionally performed such that the error of the affected bit cell is minimized.
On the contrary, an error intentionally induced in another cell can serve to alleviate the imperfections of the affected cell, thus improving the overall accuracy. In fact, digital pre-distortion is a variant of such an approach. The findings of this dissertation greatly benefit in exploring various calibration schemes by error induction, to compensate for amplitude and timing inaccuracies. In addition, the prior knowledge on the accuracy of the calibration circuitry and the distribution of mismatches in the DAC bit cells can also be used to determine the most optimum signal to be fed to a bit cell; specific examples can include dithering of a bit waveform, or swapping of two bit waveforms, etc.
The fundamental approach of studying the bit signature provides us the benefit of
159
re-engineering it to develop DACs with spurious performance, far superior than what is known today. In other words, a 5-bit DAC can provide over 7 bits of effective resolution, hence relaxing speed-accuracy tradeoffs. The developed analysis can also be extended to conduct a study of waveforms that maximize the achievable performance in DACs.
The models developed in this work also pave way for the exploration of ternary and quaternary D/A conversion. The game changing aspect of this approach is that it can completely transform the worlds view of how we process bits from digital to the analog domain, which is far reaching beyond DACs. The bit engineering process, described in
chapter 7, can also be carried out from an optimization stand-point to create non-binary
DACs that provide superior performance than their binary counterparts, while employing significantly lower number of bits. Such a brand new class of DACs based on the bit-bybit engineering approach and the science of obtaining high-resolution performance from low-resolution systems is a game-changer in todays technological trend, and completely alters the notion of high performance implying more bits; thus creating the doors to a new field of Compressive Transmission , parallel to what has been done on compressive
The fundamental investigations on the bit-by-bit engineering hold opportunities, not only in DACs, but opens up prospects in the emerging field of pulse-width pulse-position modulation, a technique for directly driving power from the digital to the RF domain; ultimately moving the digital boundary line as close to the antenna, as possible.
In summary, the research findings described in this dissertation not only change the face of D/A conversion, but also act as an enabler for efficient transmission and hold significant potential in the growth of power-aware circuits and systems in biomedicine,
RFID and cognitive sensing.
160
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