DAA Design Guide -- AN347

AN347 DAA D ESIGN G UIDE 1. Introduction The Si3056 chipsets improve upon Silicon Laboratories' ground breaking family of silicon direct access arrangement (DAA) products by providing the highest integration, lowest cost, and smallest area DAA solution for modem and voice applications. Silicon Laboratories' DAA chipsets consist of two devices. These two integrated circuits are commonly referred to as the digital-side device (Si3056) and the line-side device (DAAs, which include Si3019/Si3018/Si3010). This nomenclature refers to the portion of the circuit each chip interfaces; the digital logic refers to the system or the telephone line. The Silicon Laboratories embedded silicon DAA provides a programmable line interface to meet global telephone line interface requirements. The system-side device is supplied as a netlist and synthesized into a standard cell process technology library of the customer's choice to be integrated into an application-specific integrated circuit (ASIC) or application-specific standard product (ASSP). Silicon Laboratories is a leading supplier of silicon DAA products. This application note discusses DAA design considerations that will assist the printed circuit board designer in developing a product that meets the target application's requirements. Functional Block Diagram Si3056 MCLK SCLK FSYNC SDI SDO FC/RGDT Si3018/19/10 RX Digital Interface Hybrid and DC Termination Isolation Interface Isolation Interface RGDT/FSD/M1 OFHK M0 RESET Control Interface AOUT/INT Rev. 0.3 9/11 Copyright © 2011 by Silicon Laboratories Ring Detect Off-Hook IB SC DCT VREG VREG2 DCT2 DCT3 RNG1 RNG2 QB QE QE2 AN347 AN347 2 Rev. 0.3 AN347 TABLE O F C ONTENTS 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1. Si3056 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2. Typical DAA Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.3. Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.4. Ring Detection/Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.5. Digital Hybrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6. Recommended Off Hook Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3. Certification Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1. The Brazil Over Current Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2. Other Country Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3. Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4. Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4. Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1. Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2. Isolation Barrier Creepage Spacing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3. Line Side Chip Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4. Assembly Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.5. Embedded DAA Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6. Layout Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5. DAA Trouble Shooting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.1. Visual Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2. Basic Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3. Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4. DAA Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6. Previous Application Notes Replaced by AN347 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Rev. 0.3 3 AN347 2. Device Operation 2.1. Si3056 Block Diagram 3.3 V DSP or ASIC Si3056 VD FSYNC VA FSYNC SCLK SCLK SDI SDO SDO SDI GPO RST GPO OFHK M0 RGDT/M1 FC GPI Clock Input MCLK VD or GND GND Figure 1. Si3056 Block Diagram 2.2. Typical DAA Application Schematics No Gr ound P lane In D AA Sec t ion Q1 R10 R3 + R12 R13 Q4 R5 C4 C1A C2A R11 R1 R2 Q2 C10 R4 Q5 U2 C1 1 2 3 4 5 6 7 8 C2 R9 C5 QE DCT2 DCT IGND RX DCT3 IB QB C1B QE2 C2B SC VREG VREG2 RNG1 RNG2 Si3018 R6 16 15 14 13 12 11 10 9 Q3 C6 R14 Z1 C7 C3 R8 FB2 RJ1 R16 C9 D1 - + RV1 C8 R7 FB1 Figure 2. Typical Si3018 Based DAA Application Circuit 4 Rev. 0.3 R15 1 2 3 4 5 6 7 8 9 10 11 12 AN347 2.3. Multiple Device Support A key feature of the Si3056 DAA chipsets is the ability to be cascaded on a common serial interface. This type of circuit is commonly referred to as a master/slave configuration. The master/slave capability of the DAA chipsets is accomplished by programming the digital side device (Si3056) as described in this section. The Si3056 digital side device provides the support for this multiple device operation on a common serial interface. Generally, an Si3056 is used as a master to control up to seven additional devices on a single serial interface. The Si3056 digital side device can also be slaved to an ASIC. With an ASIC as the master, there can be up to eight slaved DAA chipsets sharing a common serial interface. 2.3.1. Master with Single Slave A common application for Si3056 DAA is to be used with the Si3000 (voice codec) in applications such as a data/fax/voice modem (see Figure 3). In this configuration, the Si3056 (master) will be set in serial mode 0 or 1 (see Table 1). The Si3000 should be configured as a slave. On power-up, the Si3056 master device will be unaware of the additional device on the serial bus. The FC/RGDTpin is an input operating as the hardware control for secondary frames. The RGDT/FSD pin is an output operating as the active low ring detection signal. The master device should be programmed for master/slave mode prior to enabling the patented capacitive communications link to prevent a ring signal from falsely transitioning the slave device's FSYNC input. MCLK DSP Si3056 MCLK SCLK SDI SDO FSYNC SCLK SDO SDI FSYNC INTO FC/RGDT RGDT/FSD/M1 VCC 47 k M0 47 k VCC 47 k 47 k Si3000 SCLK MCLK FSYNC SDI SDO Voice Codec Figure 3. Si3056 Typical Connection for Master/Slave Operation (e.g. Data/Fax/Voice Modem) Rev. 0.3 5 AN347 Table 1. Serial Modes Mode M1 M0 Description 0 00 FSYNC frames data 1 01 FSYNC pulse starts data frame 2 10 Slave mode 3 11 Reserved The first step to enabling multiple devices is the programming of the MCLK rate and the sample rate of the master. When using multiple devices, the sample rate should remain fixed. Varying the sample rate will cause the PLLs in the slave devices to lose lock and require time to resynchronize. During this time, the behavior of the parts will be unpredictable. To program the MCLK and sample rate, refer to the “Clock Generation Subsystem” section of the Si3056 DAA data sheet. The SCLK generated by the master device is fed into the MCLK of the slave. The Si3056 will set M1 and N1 based on the following equation: M1 256  Sample Rate  -------- = 98.304 MHz N1 This will ensure an identical sample rate for each device. Register 14 provides the necessary control bits to configure the Si3056 for master/slave operation. When the Si3056 is in serial mode 0 or 1 (master), the default value of Register 14 is 00h. When the Si3056 is in serial mode 2 (slave), the default value is 3Dh. This register should be programmed after the PLLs are programmed and before enabling the capacitive communication link. The three most significant bits of Register 14 (NSLV[2:0]) set the number of slave devices to be supported on the serial bus. For each slave, the Si3056 configured as the master will generate an FSYNC to the DSP. The next two bits of Register 14 (SSEL[1:0]) determine the type of signaling used in the LSB of SDO. This can assist the DSP in isolating which data stream is the master and which is the slave. The default SSEL for the slave device will be 11b, indicating 15-bits of SDO receive data stream with the LSB = 0. If a 16-bit data stream is desired, the SSEL must be set to 00b. Bit 2 of Register 14 is the delayed frame sync control (FSD) bit. This will select the number of SCLKs from the beginning of the primary frame (output on FSYNC) to the generation of the delayed frame sync (FSD) signal from the master. If the FSD bit is high, the FSD signal will be generated 16 SCLKs after the beginning of the primary frame. In this mode, the slave device will be signaled to send or receive data immediately after the master finishes sending or receiving the 16-bit stream (see Figure 4). This is the recommended setting when using an Si3056 as the master and using either the Si3056 or the Si3000 as a slave. 16 SCLKs 16 SCLKs 96 SCLKs 16 SCLKs 16 SCLKs FSYNC FSD SDO RCV Data Master Control Data Master RCV Data Slave Figure 4. One Master, One Slave, Master Serial Mode 1, FSD Bit 1 6 Rev. 0.3 Control Data Slave AN347 If the FSD bit is set low, the FSD signal will be generated 32 SCLKs after the start of the primary frame. This will allow 16 SCLKs after the data transfer of the master before the data transfer occurs for the slave (see Figure 5). If the master is using serial mode 0 (where the FSYNC frames the data), it is necessary to have 32 SCLKs. This will allow the FSYNC signal to go high before pulsing low to frame the data for the slave (see Figure 6). This mode is not recommended for Silicon Laboratories devices and is only mentioned as a possible solution when using a nonSilicon Laboratories codec as the slave. 16 SCLKs 16 SCLKs 16 SCLKs 80 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs FSYNC FSD SDO RCV Data Master Control Data Master RCV Data Slave Control Data Slave Figure 5. One Master, One Slave, Master Serial Mode 1, FSD Bit 0 16 SCLKs 16 SCLKs 16 SCLKs 80 SCLKs 16 SCLKs 16 SCLKs FSYNC FSD SDO RCV Data Master Control Data Master RCV Data Slave Control Data Slave Figure 6. One Master, One Slave, Master Serial Mode 0, FSD Bit 0 In daisy-chain mode (DCE = 1), the polarity of the ring signal can be controlled by bit 1 (RPOL) of Register 14. When RPOL = 1, the ring detect signal is active high. Bit 0, Daisy Chain Enable (DCE), sets the Si3056 in master/slave mode. When this bit is set, the FC/RGDTpin becomes the ring detect output, and the RGDT/FSD pin becomes the delay frame sync output. Once the control registers of the master have been programmed, the communications link of each device can be enabled. It is up to the DSP or ASIC controlling the devices to track the time frames to ensure data is being transferred to and from the intended device. 2.3.2. Master with Multiple Slaves The Si3056 can support up to seven slave devices on a single serial bus. The master must be set in serial mode 1. The slave devices must be in serial mode 2 (see Figure 8). The PLLs of the master device should be configured on start-up. The number of slaves is set with the NSLV[2:0] bits of Register 14 in the master Si3056, and the FSD bit should be set high. These settings are used to avoid bus contention and false signaling. Figure 7 shows the relative timing for one master and three slave devices. After the master has been appropriately programmed, the communication between the line side and digital side devices in the DAA chipset can be enabled on each of the slaves. Rev. 0.3 7 AN347 16 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs RCV Data Master RCV Data Slave 1 RCV Data Slave 2 RCV Data Slave 3 64 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs Control Data Master Control Data Slave 1 Control Data Slave 2 Control Data Slave 3 FSYNC FSD1 FSD2 FSD3 SDO Figure 7. One Master, Three Slaves, Master Serial Mode 1, FSD = 1 8 Rev. 0.3 AN347 MCLK DSP Si3056–Master MCLK SCLK SDI SDO FSYNC SCLK SDO SDI FSYNC FC/RGDT RGDT/FSDM1 INTO VCC M0 47 k 47 k 47 k Si3056–Slave VCC MCLK SCLK FSYNC SDI SDO 47 k RGDT/FSDM1 VCC M0 Si3056–Slave 2 MCLK SCLK FSYNC SDI SDO VCC 47 k RGDT/FSDM1 VCC M0 Figure 8. Typical Connection for Multiple Si3056s Rev. 0.3 9 AN347 2.3.3. ASIC Master with Single Si3056 Slave In certain cases, it may be desired to have the Si3056 in slave mode without an Si3056 as the master (see Figure 9). This can be done if the proper signals are sent from the ASIC to the Si3056. CLK MCLK Optional OFHK FSYNC FSYNC 3.3 V SCLK M0 VD VA 0.1 µF Si3056 DATA_IN SDO GND DATA_OUT SDI C1A C2A To Line Side 3.3 V RGDT FC/ RGDT RST RGDT/FSD/M1 RESET 4.7 k AOUT Optional ASIC Figure 9. Si3056 as Single Slave to ASIC The most important concern is the clock rate. The Si3056 will set M1 and N1 based on the following equation: M1 256  Sample Rate  -------- = 98.304 MHz N1 The ASIC must supply a clock signal to MCLK that equals 256 x Fs, where Fs is the desired sample rate. This clock signal should have less than 100 ppm edge-to-edge jitter. During normal operation in this configuration, the clock signal should not be changed. On startup, the Si3056 should be held in reset until the MCLK input is stable. After RESET transitions high, SDI should remain 0 for a minimum of 1 msec to allow the PLLs to lock. Another signal of concern is the frame sync signal (FSYNC). This would normally be the FSD signal coming from the master. In serial mode 2, the Si3056 expects an FSYNC input from the master that frames the serial data. When using an ASIC as the master, the ASIC must generate this FSYNC for the Si3056 (see Figure 10). 128 SCLKs FSYNC SDO 128 SCLKs 16 SCLKs 16 SCLKs RCVO CONT 0 RCVO Figure 10. Relative Timing, Single Slave, ASIC Master 10 Rev. 0.3 AN347 2.3.4. ASIC Master with Multiple Si3056 Slaves Using the same signaling scheme, up to eight digital side devices (eight Si3056s) may share the same serial interface (see Figure 11). In this case, the clocking procedures used in the previous situation still apply. The ASIC will generate the FSYNC for the first slave; then, each slave will generate an FSD output, which will be the FSYNC input for the next slave in the chain. It is imperative that the ASIC keeps track of time slots and which slave is handling data in which time slot (see Figure 12). 128 SCLKs FSYNC 16 SCLKs FSD0 FSD1 FSD2 FSD3 FSD4 FSD5 FSD6 SDO RCV 0 RCV 1 RCV 2 RCV 3 RCV 4 RCV 5 RCV 6 RCV 7 Cont 0 Cont 1 Cont 2 Cont 3 Cont 4 Cont 5 Figure 11. Relative Timing, Multiple Slaves, ASIC Master Rev. 0.3 11 AN347 Si3056 FSYNC MCLK FSYNC CLK NC ASIC DO DI VCC 10 k SCLK SDI SDO M0 47 k RST FSD/M1 RST 10 k NC VCC Si3056 FSYNC MCLK SCLK SDI SDO M0 47 k FSD/M1 RST NC VCC Si3056 FSYNC MCLK SCLK SDI SDO M0 47 k FSD/M1 RST NC VCC Si3056 FSYNC MCLK SCLK SDI SDO M0 47 k FSD/M1RST Figure 12. Typical Connection of Multiple Si3056s as Slaves, ASIC Master 12 Rev. 0.3 AN347 2.4. Ring Detection/Validation 2.4.1. Ring Detection Methods Ring detection on the Si3056 can be achieved using one of three methods. The first method uses the RGDT pin. The second uses the RDT, RDTP, and the RTDN bits. Finally, the Serial Data out pin can be used to detect ringing signals. All of these methods require the DSP to qualify the frequency and cadence of the ringing signal. Alternatively, the hardware ring validation feature discussed can be used in place of using the DSP to monitor frequency. On the Si3056 DAA, the ringing signal is resistively coupled from TIP and RING to the line-side device. The signal appearing on these pins can be detected in Full-Wave or Half-Wave mode. Full-wave ring detection is accomplished by setting the RFWE bit. This bit affects each of the three methods as discussed below. The FullWave mode can be used to detect polarity reversals during caller ID, etc. The actual voltage level that trips the ring detector can be programmed with the RT bit. When cleared, the voltage threshold is in the range from 13.5 to 16.5 Vrms. When set, the threshold voltage is increased from 19.35 to 23.65 Vrms. The three detection methods are discussed in detail in the following sections. 2.4.1.1. RGDT Pin Method The RDGT pin can be monitored for activity on the RNG1 and RNG2 pins. In Half-Wave Detection mode, (RFWE = 0), every time the voltage on these pins crosses the positive threshold, the RGDT pin will be asserted. In Full-Wave Detection mode (RFWE = 1), a voltage above the positive or below the negative threshold will cause the RGDT pin to be asserted. In this case, the frequency on the pin is twice the frequency of the actual ringing waveform. The RGDT pin is an open-drain output, and the polarity of this pin can be changed by setting the RPOL bit (Register 14, bit 1). It requires a 4.7 k pullup or pulldown for proper operation. If multiple devices are used, the RGDT pins can be connected to a single input with the combined pullup or pulldown resistance equal to 4.7 k. 2.4.1.2. Ring Detect Bits Method The second method of ring detection uses the RDT, RDTP, and RDTN bits. RDTP is set whenever the voltage at the line-side device exceeds the positive threshold, and the RDTN bit is set when the voltage exceeds the negative threshold. When the signal at the device is between the thresholds, neither bit is set. The RDT behavior is also based on the voltage. When the RFWE bit is 0, a positive ring signal sets the RDT bit for a set period of time. When the RFWE bit is 1, a positive or negative ring signal sets the RDT bit. The RDT bit acts as a one-shot pulse. When a new ring signal is detected, the one-shot is reset. If no new ring signals are detected prior to the one-shot counter reaching 0, the RDT bit clears. The length of this count is five seconds. The RDT bit is also reset to 0 by an off-hook event. When the RDTM bit is set, a hardware interrupt occurs on the interrupt pin when RDT is triggered. This interrupt can be cleared by writing the RDTI bit to 0. The function of the interrupt pin is slightly different if Ring Validation mode is enabled as described in the Ring Validation section. 2.4.1.3. Serial Data Out Method The third method of ring detection uses the data communication interface to transmit ring data. If the isolation capacitor link is active (PDL = 0) and the device is in the on-hook state, the ring data is presented on the Serial Data Out Pin. The waveform on this pin depends on the state of the RFWE bit and whether the DAA is in On-Hook Monitor mode. When RFWE is 0, the serial data is near negative full-scale (–32768) (0x8000) while the voltage at the device is between the thresholds. When a ring is detected, the data transitions to near positive full-scale (+32767) when the ring signal is positive and then goes back to near negative full-scale when the ring is near 0 and negative. Thus, a near square wave is presented by the SDO data that swings from near negative full-scale to near positive full-scale in cadence with the ring signal. Rev. 0.3 13 AN347 When RFWE is 1, the serial data pin sits at approximately +1228 while the voltage at the device is between the thresholds. When the ring becomes positive, the SDO data transitions to near positive full-scale. When the ring signal goes near 0, the SDO data remains near 1228. As the ring becomes negative, the SDO data transitions to near negative full-scale. This repeats in cadence with the ring signal. A simple method to see the ring signal on the serial data pin is to observe the MSB of the data. The MSB toggles at the same frequency as the ring signal independently of the Ring Detector mode. This is adequate information for determining the ring frequency. 2.4.2. Hardware Ring Validation Ringing signals are validated using a state machine with a series of bits to specify valid frequencies and cadences. These bits can be used to distinguish between actual ring signals and false ring trips and to detect and distinguish between distinctive ringing signals. They also eliminate software algorithms required to qualify ringing signals in previous generation products. The state machine is shown in Figure 13. SLEEP count1 <— ring_timeout count2 <— inversion_assert output line_reversal = FALSE output valid_ring = FALSE State-Machine Operation State machine is evaluated at 16 kHz intervals line_activity & ring validation enabled CHECK_REVERSAL decrement count1 decrement count2 on line_activity line_activity & timeout2 line_activity & (count1 <= rmax) count2 <— distinctive_ring_conf ASSERT_REVERSAL output line_reversal = TRUE count1 <— ring_assert TRIGGER State-Machine Inputs Reject short events, transients, out-of-band signals decrement count1 decrement count2 line_activity : Tip/Ring voltage crosses ring voltage threshold timeout1 : count1 = = 0 timeout2 : count2 = = 0 timeout1 (low frequency detect) line_activity & (count1 > rmax) (high frequency detect) timeout2 line_activity count2 <— ring_conf ring_timeout = RTO[3:0]x2048 inversion_assert = IAS distinctive_ring_conf = f(RCC[2:0]) ring_assert = RAS[5:0]x32 rmax = RMX[5:0]x32 ring_conf = RDLY[2:0]x4096 count1 <— ring_timeout SCREEN Filter out multiple triggers from distinctive ringing cadences decrement count1 decrement count2 State-Machine Outputs line_reversal 1: = battery reversal detected valid_ring 1: = ring signal validated timeout1 timeout2 line_activity count2 <— ring_conf count1 <— ring_timeout ENDRING timeout1 Find end of a valid ringing signal decrement count1 output valid_ring = TRUE Figure 13. Si3056 Ring Validation State Diagram 14 Rev. 0.3 AN347 The following is a summary of the relevant bits:           RNGV-Ring Validation Enable, Enables/Disables hardware ring validation. RAS [5:0]-Ring Assertion Time, Sets minimum valid ring frequency. RMX [5:0]-Ring Assertion Maximum Count, Sets maximum valid ring frequency in conjunction with RAS. RCC [2:0]-Ring Confirmation Count, Sets minimum valid cadence on-time. RTO [3:0]-Ring Timeout, Sets minimum valid cadence off-time. RDLY [2:0]-Ring Delay, Sets delay from valid ring frequency to interrupt generation. Can be used to avoid going off-hook during power cross tests. RDT-Ring Detect, Indicates ring is occurring. RDTI-Ring Detect Interrupt, Indicates valid ring had occurred. RDTM-Ring Detect Mask, Used to mask RDTI to AOUT/INT pin. RDI-Ring Detect Interrupt Mode, Controls whether an interrupt occurs at the beginning only or the beginning and the end of a ring burst. By programming these bits to proper values as shown in the following sections, the programmer can accurately distinguish between valid and invalid ringing signals. 2.4.2.1. RNGV-Ring Validation Enable (R24 [7]) When set, this bit enables the usage of the built-in hardware validation feature. When cleared, this feature is disabled, and ring detection must be performed using one of the methods described previously. 2.4.2.2. RAS-Ring Assertion Time (R24[5:0]) At the first positive detect of any signal, a counter previously loaded with the value in the RAS bits begins to count down at a constant rate. As it counts down, the state machine checks for additional positive detects. If no additional positive detects occur during a period defined by a counter loaded with the value of the RAS bits, a polarity reversal has occurred, and the state machine outputs a line reversal and resets itself. If additional positive detects are present and the RAS counter has not expired, the frequency of the signal is high enough and may be considered valid. The actual value loaded into the RAS bits is in binary coded increments of 2 ms. The value is calculated using the following formula: 1 RAS [5:0] = --------------------------------------1  f min  2 ms where fmin is the lower limit of the valid ring frequency range. fmin is multiplied by 2 because there are two detects per cycle of the ringing signal. Also, the 2 ms factor is used because of the coding mentioned above. The default value of RAS is 11001b, which translates to an fmin of 10 Hz. 2.4.2.3. RMX-Ring Assertion Maximum Count (R22 [5:0]) At the negative detect of the ringing signal, the value in the RAS counter is compared to the value of the RMX bits to determine if the signal frequency is in or out of the valid frequency range. If the RAS timer value is less than or equal to the RMX value, the frequency is valid; otherwise, it is too high. The value loaded into the RMX bits is also in binary coded increments of 2 ms and is calculated using the following formula: 1 RMX [5:0] = RAS [5:0] – ---------------------------------------2  f max  2 ms where fmax is the upper limit of the valid ring frequency range. The default value is 10110b, which translates to an fmax of 83.3 Hz. A timing diagram for both RAS and RMX is shown in Figure 14. Rev. 0.3 15 AN347 RING FREQUENCY TOO LOW RING FREQUENCY IN RANGE RING FREQUENCY TOO HIGH Valid High f Region Region Low f Region RAS Timer RMX RMX RMX Value Value Value Figure 14. Ring Validation Frequency Example 2.4.2.4. RCC-Ring Confirmation Count (R23 [2:0]) The value of the RCC bits is loaded into another counter that begins counting down after the signal frequency has been validated by RAS and RMX. If the frequency falls out of the valid range any time before the counter expires, the ring is not valid. If the frequency stays in range until the counter expires, the ring signal meets the on-time requirement. The range of the RCC bits is 100 to 1024 ms, and the default value is 512 ms. The function of RCC is summarized in Figure 15. 384 ms 1024 ms On - time On - time RCC = 640 ms RCC = 640 ms On-time > RCC Valid On-time < RCC Figure 15. Ring Validation --- RCC [2:0] Bits 16 Rev. 0.3 Invalid AN347 2.4.2.5. RTO-Ring Timeout (R23 [6:3]) After the ring signal has been present for a duration equal to RCC, the state machine stops looking at frequency and starts looking for the end of the ring burst. The state machine determines the end of a ring burst by starting a timer that is previously loaded with the value encoded in RTO. This timer is reset whenever a detection occurs. If the timer expires, the ring burst is considered to have ended. In addition, the state machine is reset at this time. These bits can be used to detect and distinguish between distinctive ringing signals. The default value for RTO is 640 ms, and the range is from 128 to 1920 ms. Figure 16. shows the function of RTO. 512 ms Off - time Detect 1024 ms 1024 ms On - time Off - time 1024 ms On - time RTO RTO Off-time < RTO 2 nd Detect Detect No 2nd Detect Off-time > RTO 2nd Detect Figure 16. Ring Validation (RTO [3:0] Bits) 2.4.2.6. RDLY-Ring Delay (R23 [7], R22 [7:6]) The RDLY bits are used to delay the interrupt from occurring a certain amount of time from when the frequency and on-time has been validated. This is accomplished using a countdown timer. To get an interrupt, the RDLY timer must expire before the RTO timer expires because the latter causes the state machine to be reset. RDLY can be used to keep the DAA from going off-hook during 50/60 Hz power cross tests, which could be detected as a valid ring. The RDLY default value is 512 ms, and the range is from 0 to 1792 ms. A timing diagram for RDLY is shown in Figure 17. Detect No Detect—RDLY never reaches 0 1024 ms On-time 384 ms On-time RDLY = 128 ms RCC = 512 ms RDLY = 768 ms RTO = 256 ms Figure 17. Ring Validation --- RDLY [2:0] Bits Rev. 0.3 17 AN347 2.4.3. Interrupt Generation in Ring Validation Mode With Ring Validation enabled, the output of the state machine controls when an interrupt is generated and the RDTI bit is set. The RDTI bit follows the rising edge of the RDT bit. The RDT bit still acts like a one shot, but the RDTI bit can be cleared during the ring signal. In Ring Validation mode, the state machine controls the RDT bit instead of RDT being a one-shot pulse with a 5 second width. If an interrupt is needed at the beginning and the end of the ring burst, the RDI bit should be set. This bit allows an interrupt to occur on the rising and falling edge of the ring burst. To see both interrupts, the RDTI bit must be cleared before the end of the burst. The beginning interrupt is triggered by the rising edge of the RDT bit, and the ending interrupt is triggered by RDT falling, which occurs when the RTO counter expires in the ring validation state machine. 2.5. Digital Hybrid 2.5.1. Overview The Si3056 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. This hybrid circuit is adjusted for each ac termination setting selected to achieve a minimum transhybrid balance of 20 dB. The Si3056 also offers a digital filter for additional near-end echo cancellation to compensate for any line impedance mismatch. For each ac termination setting, the eight programmable hybrid registers (Registers 45–52) can be programmed with coefficients to increase the cancellation under real-world line conditions. This digital filter can produce 10 dB or greater of near-end echo cancellation in addition to the 20 dB from the analog hybrid circuitry. Figure 18 describes the basic architecture of the digital hybrid. It is composed of an 8-tap FIR filter. "b0" through "b7" represent the filter coefficients in 2s complement form. The initial 4-sample bulk delay is used to compensate for the round trip delay through the line side device. This architecture is designed to delay and filter the transmit signal to match the portion not cancelled by the analog hybrid. b0 Z-4 Z-1 b1 + Z-1 Z-1 b7 Figure 18. Digital Hybrid Structure 18 Rev. 0.3 AN347 Figure 19 illustrates the basic signal flow of the DAA. The digital signal has been up-sampled to 16 kHz at the digital hybrid stage. The transmit signal goes through a digital filter, digital-to-analog converter, and analog filter before going out on the line or being used in the analog hybrid circuitry. After the analog hybrid, the receive signal passes through an analog filter, analog-to-digital converter, and digital filter before going back into the digital hybrid. The analog hybrid path adds approximately four samples of delay to the signal. The digital hybrid structure matches this filter delay by delaying the digital samples by the same amount. Digital Filters TX DAC AC Termination Line Driver Analog Filters Line RX Digital Hybrid @16kHz Digital Filters ADC Analog Filters Analog Hybrid Figure 19. Signal Flow Diagram A model of the DAA and the phone line is shown in Figure 20. In an ideal system, the analog hybrid yields perfect cancellation of the near-end echo from the transmit path. A mismatch between the ac termination and the load produces an echo that is not removed by the analog hybrid. To increase the near-end echo cancellation, the digital hybrid must equalize the disparity between the impedance mismatch of the ac termination and the line. DAC at 16 kHz TX HL() HT() HD(ej) at 16 kHz + RX + + ADC at 16 kHz HR() + + Figure 20. Model of DAA and Phone Line From the above model, the echo can be calculated as follows: Echo = H T     H L     H R    – H T     H R    = H T     H R     H L    – 1  HL(ω) consists of the DAA's ac termination in combination with the impedance of the twisted pair transmission line terminated at the central office (CO) by a reference impedance. Figure 21 shows the analog hybrid circuitry and the HL(ω) model expanded to include the ac termination and line. Rev. 0.3 19 AN347 ZACT 2 - + ZLINE + Figure 21. HL()–1 Model Substituting for HL(ω) in the equation results in: Z Line – Z ACT Z Line H L – 1 = 2  ---------------------------------- – 1 = ---------------------------------Z Line + Z ACT Z Line + Z ACT If ZLINE and ZACT are matched, the analog hybrid perfectly cancels the transmit signal. Substituting this result into the echo equation yields: Z Line – Z ACT echo = H T     H R    ---------------------------------Z Line + Z ACT The model for the HL(ω) and HR(ω) plays a critical role in this calculation. The models are quite complex, and sampled data of the models are necessary to calculate the hybrid coefficients. Contact Silicon Labs to acquire the sampled data of the HT(ω) and HR(ω?) models. A group delay, which was not illustrated in the model, must also be taken into consideration. Internal DSP and filters cause this delay. Taking the group delay into account, the echo is equal to: echo = H T     H R      H L    – 1 e j2  --------------  16000  gd where gd is the group delay. The digital hybrid must cancel the echo by intentionally adding the negative of the echo. The HD(?) should be: H D    = – H T     H R      H L    – 1 e 20 Rev. 0.3 j2  ---------------  gd  16000  AN347 2.5.2. Digital Hybrid Calculation Tool Silicon Labs has developed a useful graphical user interface tool (shown in Figure 22) that will assist in calculating the coefficients to use with the digital hybrid in the Si3056 DAA. The tool allows the user to enter the reference termination of the central office (in an R + R||C format) and the model for the phone line between the DAA and the central office. The line can be represented by one of the EIA models, shown in "2.5.6. EIA Line Models" on page 41, or as a specified length of wire. The software then executes the Matlab code found in "2.5.4. Sample MATLAB Code" on page 24, which graphically shows the expected trans-hybrid response of the digital hybrid and lists the best hybrid coefficients to use given the line characteristics. Figure 22. Digital Hybrid Three graphs are shown in Figure 23. An echo graph is created by intentionally mismatching the 600  ac termination with the TBR21 mode CO termination. The digital hybrid response is the 8-tap FIR filter response calculated using the sample code found in section 7.3. The cancelled graph is obtained by adding the echo and the digital hybrid response. The digital hybrid response looks very similar to an echo. Figure 24 shows the phase of the echo and the digital hybrid response. The phase of an echo and the digital hybrid have the opposite polarity. Figure 25 compares the rejection in dB with and without the digital hybrid. By properly using the digital hybrid, nearend echo cancellation has increased by approximately 20 dB. Rev. 0.3 21 AN347 Figure 23. Echo Figure 24. Echo Phase Figure 25. Rejection 22 Rev. 0.3 AN347 To use the Digital Hybrid Calculation Tool, simply enter the ACIM value recommended in Table 15 of the Si3056 datasheet into the ACIM control. This value determines the impedance presented by the DAA to the line. It is governed by the region in which the application will be deployed. Next, enter values for R1 and R2 in ohms and C in farads into the appropriate controls. These values will represent the impedance presented by the central office to the line. This value is also governed by the region in which the application will be deployed. Also, select the lineside device used in the application in the pull-down box. Finally, select the line model to be used that will most closely model the line connecting the DAA to the central office. This is done by either picking a specific EIA line model or by specifying a wire gauge and length. Once this is complete, hitting the “CALCULATE” button will generate the coefficients that provide the best performance. For example, if we assume that an application will be deployed within the U.S., we enter a 0 for the ACIM value. Also, the central office impedance in the US is 900  in series with 2.16 µF. To enter this information in the GUI, we enter 900 for R1 and a fairly large value for R2, since it is not present. For this example, a value of 100,000  was used. For the C value, we enter 2.16–6 since the expected units are farads. Also, for this example, we use an EIA model of 0. This means, essentially, no loop length, and the central office impedance is connected directly to the application. Now, the "CALCULATE" button is pressed, and the resulting coefficients, 0xF8, 0xF9, 0x03, 0xFE, 0xFE, 0x00, 0xFE, and 0x00, are generated. 2.5.3. Conclusion The Si3056 DAA is designed to increase the near-echo cancellation with an additional hybrid in the digital path operating at 16 kHz. Near-end echo is primarily caused by the mismatch between the ac termination and the CO termination. The transmit and receive signal paths also affect the echo to a lesser extent. By introducing a filter that models the near-end echo 180 degrees out-of-phase to the receive path echo, the hybrid response can be improved. This improvement in the hybrid response results in greater cancellation of the transmit signal when the near-end echo and digital hybrid response are added together at the digital hybrid stage. To generate the coefficients, the 8-tap FIR filter structure used in the digital hybrid must be taken into account. This digital filter structure requires the hybrid response to be represented in the z-domain. "2.5.4. Sample MATLAB Code" contains sample MATLAB code to calculate the hybrid coefficients. This code should help in understanding the process of calculating the hybrid coefficients. A hybrid coefficient lookup table can be found in "2.5.5. Hybrid Coefficient Lookup Tables" on page 27. These tables provide a set of coefficients to use for different line conditions. Rev. 0.3 23 AN347 2.5.4. Sample MATLAB Code A sample MATLAB program for use in setting the hybrid coefficients is shown below. The code takes the ACIM (Register 30) setting and line model as an input and outputs the best coefficient for the digital hybrid to match the line. function hdh = dig_hybrid(ACIM, R1line, R2line, Cline, HtMag, HtPhase, HrMag, HrPhase); % hdh = dig_hybrid(ACIM, R1line, R2line, Cline, HtMag, HtPhase, HrMag, HrPhase); % % This function calculates the coefficient values for the digital hybrid given a R1+R2||C model for the line. % % ACIM : register setting of the AC termination % R1line : line R1 % R2line : line R2 % Cline : line C % HtMag : Transmit path response % HtPhase : Transmit path response % HrMag : Receive path response % HrPhase : Receive path response % % hdh : digital hybrid coefficients Nact=ACIM+1; if(R1line==0), R1line=eps; end if(R2line==0), R2line=eps; end if(Cline==0), Cline=eps; end %eps is the smallest value after 0 % Set sample rate and frequency grid fs=16000; f=[eps:1:7999]; w=2*pi*f/fs; %%%%%% Transmit path (Ht) Ht = HtMag .* exp(j*HtPhase) 24 Rev. 0.3 AN347 %%%%%%% Receive path (Hr) Hr = HrMag .* exp(j*HrPhase) %%%%%%%%%% Near end echo (H2) % Calculate ZLINE Zcline=1./(j*2*pi*f*Cline); Zline=R1line + R2line.*Zcline./(R2line+Zcline); % Calculate Zref, assume perfect ACT R1ref=[eps eps 270 220 370 320 370 275 120 350 eps 600 900 900 600 270]; R2ref=[600 900 750 820 620 1050 820 780 820 1000 900 1e9 1e9 1e9 1e9 750]; Cref =[eps eps 150 117 310 230 110 132 110 210 30 2160 1000 2160 1000 150]*1e-9; Zcact=1./(j*2*pi*f*Cref(Nact)); Zact=R1ref(Nact) + R2ref(Nact).*Zcact./(R2ref(Nact)+Zcact); C9r=0*1e-9; Ycact2=(j*2*pi*f*C9r); Zact=1./(1./Zact + Ycact2); %%%%% HL=2*Zline./(Zact+Zline); HL(1)=0; % Add extra group delay to match measurements gde=-0.225; Hd=-Ht.*Hr.*(HL-1).*exp(j*2*pi/16000*gde*[0:length(Ht)-1]); Hd=[Hd conj(fliplr(Hd))]; % Estimate impulse response to match hd=real(ifft(Hd)); % Truncate coefficients and express in [0 255] hdh=round(hd(5:12)*64); ind=find(hdh<0); Rev. 0.3 25 AN347 hdh(ind)=hdh(ind)+256; echo = Ht.*Hr.*(HL-1).*exp(j*2*pi/16000*gde*[0:length(Ht)-1]); hyb_coef = [0 0 0 0 hd(5:12)]; dig_hyb = freqz(hyb_coef,1,w); figure plot(f,abs(echo),'-',f,abs(dig_hyb),'-.',f,abs(echo+dig_hyb),':') axis([0 4000 0 0.4]) legend('echo','digital hybrid response','cancelled signal') xlabel('frequency') ylabel('echo') figure plot(f,angle(echo),'-',f,angle(dig_hyb),'-.') axis([0 4000 -pi pi]) legend('echo','digital hybrid response') xlabel('frequency') ylabel('echo') figure plot(f,20*log10(abs(echo)),'-',f,20*log10(abs(echo+dig_hyb)),'-.') axis([0 4000 -42 0]) legend('echo','cancelled signal') xlabel('frequency') ylabel('rejection') 26 Rev. 0.3 AN347 2.5.5. Hybrid Coefficient Lookup Tables Tables 2–15 (for Rev C and prior versions of the Si3019) and Tables 16–29 (for Rev E and later versions of the Si3019) provide fixed digital hybrid coefficients to best match the line load with specific EIA line models. For this calculation, the EIA line model was incorporated into the HL(w) model. The first column shows which line type was used to calculate the hybrid coefficient. The remaining columns display the hybrid coefficients (Registers 45–52). Table 2. ACIM = 0000 and CO Termination = 900 Ω + 2.16 μF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 248 249 3 254 254 0 254 0 EIA 1 251 240 255 5 250 2 254 255 EIA 2 2 240 238 7 253 254 2 254 EIA 3 5 239 235 7 252 254 2 254 EIA 4 1 242 240 1 252 255 0 255 EIA 5 7 244 233 1 250 253 0 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 253 242 254 5 250 2 255 255 2000 ft. 24 awg 252 240 254 5 250 2 254 255 2000 ft. 26 awg 251 240 255 5 250 2 254 255 Table 3. ACIM = 0000 and CO Termination = 600 Ω Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 255 247 255 4 253 2 0 0 EIA 2 2 243 241 8 253 255 2 254 EIA 3 5 240 238 9 252 255 2 254 EIA 4 1 242 241 2 253 255 1 255 EIA 5 7 244 234 2 251 254 1 254 EIA 6 4 244 228 6 7 247 1 255 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 2 250 254 4 253 1 0 0 2000 ft. 24 awg 1 249 254 4 253 1 0 0 2000 ft. 26 awg 255 247 255 4 253 2 0 0 Rev. 0.3 27 AN347 Table 4. ACIM = 0000 and CO Termination = 1200 Ω + 376 Ω + 112 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 240 242 7 255 254 3 254 1 EIA 1 247 232 254 8 249 4 255 0 EIA 2 2 238 234 6 253 254 2 254 EIA 3 4 237 231 5 252 254 2 254 EIA 4 1 241 239 255 251 254 0 255 EIA 5 7 244 233 0 249 252 0 253 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 249 233 253 8 249 3 255 0 2000 ft. 24 awg 248 232 253 8 249 4 255 0 2000 ft. 26 awg 247 232 254 8 249 4 255 0 Table 5. ACIM = 0000 and CO Termination = 150 Ω + 510 Ω + 47 nF Line Type 28 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 3 249 252 5 253 1 0 255 EIA 1 2 246 249 7 252 1 1 255 EIA 2 3 244 240 5 254 255 2 255 EIA 3 5 241 238 6 252 255 1 255 EIA 4 1 242 241 2 252 255 1 255 EIA 5 7 244 234 2 251 253 1 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 4 248 246 7 253 0 1 255 2000 ft. 24 awg 3 247 247 8 253 0 1 255 2000 ft. 26 awg 2 246 249 7 252 1 1 255 Rev. 0.3 AN347 Table 6. ACIM = 0000 and CO Termination = 220 Ω + 820 Ω + 150 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 6 246 239 5 253 255 2 255 EIA 1 3 246 241 2 254 255 1 255 EIA 2 3 245 240 1 252 254 1 255 EIA 3 5 242 238 4 250 255 0 254 EIA 4 1 242 241 2 251 254 0 254 EIA 5 7 244 234 2 250 252 0 253 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 6 249 237 2 255 253 2 254 2000 ft. 24 awg 5 247 239 3 254 254 2 255 2000 ft. 26 awg 3 246 241 2 254 255 1 255 Table 7. ACIM = 0000 and CO Termination = 600 Ω + 1.5 μF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 255 254 254 254 254 254 254 254 EIA 1 255 246 253 3 251 0 254 254 EIA 2 2 242 241 7 252 254 1 253 EIA 3 5 240 237 8 252 254 1 253 EIA 4 1 242 241 2 252 255 0 254 EIA 5 7 244 234 1 251 253 1 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 1 249 251 2 251 255 254 254 2000 ft. 24 awg 0 247 252 3 251 0 254 254 2000 ft. 26 awg 255 246 253 3 251 0 254 254 Rev. 0.3 29 AN347 Table 8. ACIM = 0010 and CO Termination = 220 Ω + 120 Ω + 115 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 9 16 5 254 2 255 0 0 EIA 1 2 10 9 255 1 0 255 1 EIA 2 255 0 3 2 0 1 0 0 EIA 3 1 253 0 4 254 1 0 0 EIA 4 253 252 0 255 0 0 0 0 EIA 5 4 253 249 255 254 255 0 255 EIA 6 1 254 242 4 8 246 2 254 EIA 7 244 241 19 11 244 2 253 1 2000 ft. 22 awg 6 15 6 254 3 255 0 0 2000 ft. 24 awg 5 12 7 255 2 0 0 0 2000 ft. 26 awg 2 10 9 255 1 0 255 1 Table 9. ACIM = 0011 and CO Termination = 220 Ω + 820 Ω + 115 nF Line Type 30 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 255 0 255 254 1 255 0 0 EIA 2 255 0 253 252 255 254 255 0 EIA 3 1 254 252 253 253 255 255 255 EIA 4 253 255 255 251 254 254 254 255 EIA 5 4 0 249 252 253 253 254 254 EIA 6 1 1 242 2 9 245 3 253 EIA 7 245 243 18 10 245 0 253 1 2000 ft. 22 awg 1 2 252 255 1 254 1 255 2000 ft. 24 awg 0 1 253 255 1 255 0 0 2000 ft. 26 awg 255 0 255 254 1 255 0 0 Rev. 0.3 AN347 Table 10. ACIM = 0100 and CO Termination = 370 Ω + 620 Ω + 310 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 254 252 2 1 255 1 255 0 EIA 2 255 248 253 4 253 0 0 255 EIA 3 1 246 251 6 252 1 0 255 EIA 4 252 247 253 2 253 0 255 255 EIA 5 3 248 246 3 252 255 255 254 EIA 6 0 249 240 8 8 247 2 254 EIA 7 244 236 18 14 241 5 254 1 2000 ft. 22 awg 1 255 255 0 255 0 0 0 2000 ft. 24 awg 0 253 0 1 255 1 0 0 2000 ft. 26 awg 254 252 2 1 255 1 255 0 Table 11. ACIM = 0100 and CO Termination = 220 Ω + 820 Ω + 120 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 248 254 6 255 2 1 0 EIA 1 254 249 253 4 255 1 1 0 EIA 2 255 249 251 2 254 0 0 0 EIA 3 1 246 250 4 252 1 0 255 EIA 4 252 247 253 1 253 0 255 255 EIA 5 3 248 246 2 252 254 255 254 EIA 6 0 249 240 8 8 247 2 254 EIA 7 244 236 18 14 241 5 254 1 2000 ft. 22 awg 1 251 249 5 0 0 2 255 2000 ft. 24 awg 0 249 251 5 255 0 1 0 2000 ft. 26 awg 254 249 253 4 255 1 1 0 Rev. 0.3 31 AN347 Table 12. ACIM = 0101 and CO Termination = 300 Ω + 1000 Ω + 220 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 1 0 255 1 0 0 0 0 EIA 1 254 255 2 0 255 1 0 0 EIA 2 255 252 0 2 254 0 255 255 EIA 3 1 249 255 4 252 1 255 255 EIA 4 252 250 1 1 254 0 255 255 EIA 5 3 251 251 2 253 255 255 254 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 1 254 255 1 255 0 0 2000 ft. 24 awg 0 0 0 0 0 0 0 0 2000 ft. 26 awg 254 255 2 0 255 1 0 0 Table 13. ACIM = 0101 and CO Termination = 370 Ω + 620 Ω + 310 nF Line Type 32 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 4 4 0 1 1 0 1 EIA 1 254 0 6 1 0 2 255 1 EIA 2 255 252 1 3 254 1 0 0 EIA 3 1 249 255 5 253 1 0 255 EIA 4 252 250 1 2 255 0 255 0 EIA 5 3 251 250 3 254 255 255 255 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 3 3 0 1 0 0 0 2000 ft. 24 awg 0 1 4 1 0 1 0 0 2000 ft. 26 awg 254 0 6 1 0 2 255 1 Rev. 0.3 AN347 Table 14. ACIM = 0101 and CO Termination = 270 Ω + 750 Ω + 150 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 254 2 4 1 2 1 0 EIA 1 254 253 2 3 1 2 1 1 EIA 2 255 252 0 2 255 1 0 0 EIA 3 1 249 254 4 253 1 0 0 EIA 4 252 250 1 1 254 0 255 0 EIA 5 3 251 250 2 253 255 255 255 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 0 255 3 2 0 1 0 2000 ft. 24 awg 0 254 0 3 1 1 1 0 2000 ft. 26 awg 254 253 2 3 1 2 1 1 Table 15. ACIM = 0101 and CO Termination = 200 Ω + 560 Ω + 100 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 6 5 249 0 2 254 2 255 EIA 1 4 4 247 255 2 253 2 255 EIA 2 4 2 243 253 2 252 2 255 EIA 3 6 0 242 254 0 253 1 255 EIA 4 2 0 244 251 0 252 1 255 EIA 5 8 1 238 252 254 250 1 254 EIA 6 6 2 231 2 8 245 4 251 EIA 7 249 244 8 12 245 252 0 1 2000 ft. 22 awg 7 6 244 0 3 252 3 255 2000 ft. 24 awg 6 5 246 0 2 253 2 255 2000 ft. 26 awg 4 4 247 255 2 253 2 255 Rev. 0.3 33 AN347 Table 16. ACIM = 0000 and CO Termination = 900 Ω + 2.16 μF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 248 249 3 254 254 0 254 0 EIA 1 251 240 255 5 250 2 254 255 EIA 2 2 240 238 7 253 254 2 254 EIA 3 5 239 235 7 252 254 2 254 EIA 4 1 242 240 1 252 255 0 255 EIA 5 7 244 233 1 250 253 0 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 253 242 254 5 250 2 255 255 2000 ft. 24 awg 252 240 254 5 250 2 254 255 2000 ft. 26 awg 251 240 255 5 250 2 254 255 Table 17. ACIM = 0000 and CO Termination = 600 Ω Line Type 34 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 255 247 255 4 253 2 0 0 EIA 2 2 243 241 8 253 255 2 254 EIA 3 5 240 238 9 252 255 2 254 EIA 4 1 242 241 2 253 255 1 255 EIA 5 7 244 234 2 251 254 1 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 2 250 254 4 253 1 0 0 2000 ft. 24 awg 1 249 254 4 253 1 0 0 2000 ft. 26 awg 255 247 255 4 253 2 0 0 Rev. 0.3 AN347 Table 18. ACIM = 0000 and CO Termination = 1200 Ω + 376 Ω + 112 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 240 242 7 255 254 3 254 1 EIA 1 247 232 254 8 249 4 255 0 EIA 2 2 238 234 6 253 254 2 254 EIA 3 4 237 231 5 252 254 2 254 EIA 4 1 241 239 255 251 254 0 255 EIA 5 7 244 233 0 249 252 0 253 EIA 6 4 244 233 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 249 233 253 8 249 3 255 0 2000 ft. 24 awg 248 232 253 8 249 4 255 0 2000 ft. 26 awg 247 232 254 8 249 4 255 0 Table 19. ACIM = 0000 and CO Termination = 150 Ω + 510 Ω + 47 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 3 249 252 5 253 1 0 255 EIA 1 2 246 249 7 252 1 1 255 EIA 2 3 244 240 5 254 255 2 255 EIA 3 5 241 238 6 252 255 2 254 EIA 4 1 242 241 2 252 255 1 255 EIA 5 7 244 234 2 251 253 1 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 4 248 246 7 253 0 1 255 2000 ft. 24 awg 3 247 247 8 253 0 1 255 2000 ft. 26 awg 2 246 249 7 252 1 1 255 Rev. 0.3 35 AN347 Table 20. ACIM = 0000 and CO Termination = 220 Ω + 820 Ω + 150 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 6 246 239 5 253 255 2 255 EIA 1 3 246 241 2 254 255 1 255 EIA 2 3 245 240 1 252 254 1 255 EIA 3 5 242 238 4 250 255 0 254 EIA 4 1 242 241 2 251 254 0 254 EIA 5 7 244 234 2 250 252 0 253 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 6 249 237 2 255 253 2 254 2000 ft. 24 awg 5 247 239 3 254 254 2 255 2000 ft. 26 awg 3 246 241 2 254 255 1 255 Table 21. ACIM = 0000 and CO Termination = 600 Ω + 1.5 μF Line Type 36 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 255 254 254 254 254 254 254 254 EIA 1 255 246 253 3 251 0 254 254 EIA 2 2 242 241 7 252 254 1 253 EIA 3 5 240 237 8 252 254 1 253 EIA 4 1 242 241 2 252 255 0 254 EIA 5 7 244 234 1 251 253 1 254 EIA 6 4 244 228 6 7 247 1 253 EIA 7 248 230 8 18 234 2 1 255 2000 ft. 22 awg 1 249 251 2 251 255 254 254 2000 ft. 24 awg 0 247 252 3 251 0 254 254 2000 ft. 26 awg 255 246 253 3 251 0 254 254 Rev. 0.3 AN347 Table 22. ACIM = 0010 and CO Termination = 220 Ω + 120 Ω + 115 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 9 16 5 254 2 255 0 0 EIA 1 2 10 9 255 1 0 255 1 EIA 2 255 0 3 2 0 1 0 0 EIA 3 1 253 0 4 254 1 0 0 EIA 4 253 252 0 255 0 0 0 0 EIA 5 4 253 249 255 254 255 0 255 EIA 6 1 254 242 4 8 246 2 254 EIA 7 244 241 19 11 244 2 253 1 2000 ft. 22 awg 6 15 6 254 3 255 0 0 2000 ft. 24 awg 5 12 7 255 2 0 0 0 2000 ft. 26 awg 2 10 9 255 1 0 255 1 Table 23. ACIM = 0010 and CO Termination = 220 Ω + 820 Ω + 115 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 255 0 255 254 1 255 0 0 EIA 2 255 0 253 252 255 254 255 0 EIA 3 1 254 252 253 253 255 255 255 EIA 4 253 255 255 251 254 254 254 255 EIA 5 4 0 249 252 253 253 254 254 EIA 6 1 1 242 2 9 245 3 253 EIA 7 245 243 18 10 245 0 253 1 2000 ft. 22 awg 1 2 252 255 1 254 1 255 2000 ft. 24 awg 0 1 253 255 1 255 0 0 2000 ft. 26 awg 255 0 255 254 1 255 0 0 Rev. 0.3 37 AN347 Table 24. ACIM = 0100 and CO Termination = 370 Ω + 620 Ω + 310 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 0 0 0 0 0 0 0 EIA 1 254 252 2 1 255 1 255 0 EIA 2 255 248 253 4 253 0 0 255 EIA 3 1 246 251 6 252 1 0 255 EIA 4 252 247 253 2 253 0 255 255 EIA 5 3 248 246 3 252 255 255 254 EIA 6 0 249 240 8 8 247 2 254 EIA 7 244 236 18 14 241 5 254 1 2000 ft. 22 awg 1 255 255 0 255 0 0 0 2000 ft. 24 awg 0 253 0 1 255 1 0 0 2000 ft. 26 awg 254 252 2 1 255 1 255 0 Table 25. ACIM = 0100 and CO Termination = 220 Ω + 820 Ω + 120 nF Line Type 38 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 248 254 6 255 2 1 0 EIA 1 254 249 253 4 255 1 1 0 EIA 2 255 249 251 2 254 0 0 0 EIA 3 1 246 250 4 252 1 0 255 EIA 4 252 247 253 1 253 0 255 255 EIA 5 3 248 246 2 252 254 255 254 EIA 6 0 249 240 8 8 247 2 254 EIA 7 244 236 18 14 241 5 254 1 2000 ft. 22 awg 1 251 249 5 0 0 2 255 2000 ft. 24 awg 0 249 251 5 255 0 1 0 2000 ft. 26 awg 254 249 253 4 255 1 1 0 Rev. 0.3 AN347 Table 26. ACIM = 0101 and CO Termination = 300 Ω + 1000 Ω + 220 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 4 4 0 1 1 0 1 EIA 1 254 0 6 1 0 2 255 1 EIA 2 255 252 1 3 254 1 0 0 EIA 3 1 249 255 5 253 1 0 255 EIA 4 252 250 1 2 255 0 255 0 EIA 5 3 251 250 3 254 255 255 255 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 3 3 0 1 0 0 0 2000 ft. 24 awg 0 1 4 1 0 1 0 0 2000 ft. 26 awg 254 0 6 1 0 2 255 1 Table 27. ACIM = 0101 and CO Termination = 370 Ω + 620 Ω + 310 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 4 4 0 1 1 0 1 EIA 1 254 0 6 1 0 2 255 1 EIA 2 255 252 1 3 254 1 0 0 EIA 3 1 249 255 5 253 1 0 255 EIA 4 252 250 1 2 255 0 255 0 EIA 5 3 251 250 3 254 255 255 255 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 3 3 0 1 0 0 0 2000 ft. 24 awg 0 1 4 1 0 1 0 0 2000 ft. 26 awg 254 0 6 1 0 2 255 1 Rev. 0.3 39 AN347 Table 28. ACIM = 0101 and CO Termination = 270 Ω + 750 Ω + 150 nF Line Type Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 0 254 2 4 1 2 1 0 EIA 1 254 253 2 3 1 2 1 1 EIA 2 255 252 0 2 255 1 0 0 EIA 3 1 249 254 4 253 1 0 0 EIA 4 252 250 1 1 254 0 255 0 EIA 5 3 251 250 2 253 255 255 255 EIA 6 0 252 244 8 9 247 3 254 EIA 7 244 239 21 14 244 5 254 1 2000 ft. 22 awg 1 0 255 3 2 0 1 0 2000 ft. 24 awg 0 254 0 3 1 1 1 0 2000 ft. 26 awg 254 253 2 3 1 2 1 1 Table 29. ACIM = 1010 and CO Termination = 200 Ω + 560 Ω + 100 nF Line Type 40 Hybrid Coefficient # 1 2 3 4 5 6 7 8 EIA 0 1 2 1 0 0 0 0 0 EIA 1 255 1 0 255 1 255 0 0 EIA 2 255 255 252 252 0 255 0 0 EIA 3 1 253 250 254 254 255 0 0 EIA 4 253 253 253 251 255 254 255 0 EIA 5 3 254 246 252 253 253 255 254 EIA 6 1 255 239 1 8 245 3 253 EIA 7 244 242 16 9 245 0 254 1 2000 ft. 22 awg 2 4 253 255 2 254 1 0 2000 ft. 24 awg 1 2 254 255 1 255 1 0 2000 ft. 26 awg 255 1 0 255 1 255 0 0 Rev. 0.3 AN347 2.5.6. EIA Line Models EIA1 EO EIA2 EO 2 kft 26 AWG 4 kft 26 AWG 3 kft 24 AWG EIA3 EO 7 kft 26 AWG EIA4 EO 12 kft 26 AWG EIA5 EO EIA6 EO EIA7 EO NI 1.5 kft 26 AWG 3 kft 24 AWG 88 88 6 kft 24 AWG 6 kft 24 AWG 88 88 1.5 kft 26 AWG 6 kft 24 AWG 6 kft 24 AWG 6 kft 24 AWG 88 88 NI NI 9 kft 24 AWG 3 kft 24 AWG NI 6 kft 22 AWG 6 kft 22 AWG 88 88 9 kft 22 AWG 6 kft 22 AWG 88 NI NI 3 kft 22 AWG NI Figure 26. EIA Line Models Rev. 0.3 41 AN347 2.6. Recommended Off Hook Procedure Power Up RST Low Pulse // SCLK = MCLK/16 Write Register 8 Write Register 9 // Programs PLL M // SCLK = MCLK N x20 Write Register 7 // Set sample rate Set OHE bit in Register 5 // Enables OFHK pin Write Register 6 (00h) // Enables ISOcap™ // Enables AOUT Drive OFHK low // Takes Si3056 off-hook Figure 27. Si3056 DAA Off Hook Routine with the Configuration from Figure 1 42 Rev. 0.3 AN347 3. Certification Topics 3.1. Brazil Overcurrent Recommendation 3.1.1. Overview This section provides a suggested algorithm to assist the softmodem provider in meeting the requirement described in Article 13, Paragraph 3 of Resolution 237. This article describes the EMC emissions and immunity requirements for Brazil. This resolution describes a simulated power fault test of 600 VRMS, 1 A, which is applied for a 0.2 second period. This test voltage is applied in both the common-mode and differential configurations and while the EUT is in all operating modes, both on-hook and off-hook. 3.1.2. The Algorithm for Si3018 Line Side Solution Confirm anode of Z1 is connected to the QE pin of the line-side IC. OPD Count = 0 Go off-hook OPE = 1 OPD count > 4 // Leave all other bits unmodified YES Go on-hook NO // R43.0 OPD == YES NO OPD Count ++ Wait 4 ms OPE = 0 // Clears OPD OPE = 1 Notes: 1. OPDCount > 4 is necessary due to open switch intervals which may cause one trigger for the first off hook, one for the opening and one for the closing. 2. It is assumed that polling of OPD can occur at least once every 4 ms and not faster than once every 1 ms. 3. It may be desirable to implement a timer that resets “OPD Count“ if more than 1 second elapses without a new OPD event. Figure 28. Algorithm for Si3018/19 Line Side Devices Rev. 0.3 43 AN347 3.1.3. Overvoltage Protection Algorithm Pseudocode GO Off Hook WAIT 10e-3 seconds SET counter to 0 CLEAR LCSI (DAA reg 0x34 bit2) WHILE counter < 4 WAIT 5e-3 seconds READ LCSI IF LCSI==1 THEN INCREMENT counter IF counter < 4 THEN CLEAR LCSI (DAA reg 0x34 bit2) END IF END IF END WHILE GO ON Hook OUTPUT ERROR Message 3.2. Other Country Requirements South Africa and Korea may need an additional ringer impedance. Mexico may optionally require an additional on hook impedance, depending on the compliance test house interpretation and the OEM’s declared product usage. Contact Silicon Labs for more information. South Africa may require additional metallic surge components, depending on interpretation of certification body testing the product. Contact Silicon Laboratories for more information. 3.3. Safety 3.3.1. Isolation Barrier In all modem designs, there is a portion of the modem that is isolated from the local ground. These isolated components are part of an IEC 60950 classification type called the TNV-3 (Telecommunications Network Voltage) Circuit. TNV-3 circuits are subject to ringing voltages and lightning surges and not considered safe to touch by the user and, thus, must be isolated from the rest of the system by a high-voltage barrier. This barrier is commonly called the Isolation Barrier, referring to the function of performing high-voltage isolation. Circuits powered by low-voltage dc supplies in which no hazardous voltages are generated are called SELV (Safety Extra Low Voltage) circuits. SELV circuits are safe to touch by the user and include the local ground. All components from Tip/Ring to the line side device are considered to be in the TNV-3 Circuit area. The digital side device is considered to be on the SELV Circuit area. The isolation barrier is the boundary between the TNV-3 and SELV circuit area. Figure 29 shows the SELV and TNV areas. 44 Rev. 0.3 AN347 SELV C1 C2 Bridge Diode Line Side Device Discretes Digital Side Device TIP RING TNV3 Isolation Barrier C8 C9 Figure 29. SELV, TNV-3 and Isolation Barrier The IEC 60950 term for a separation between the SELV and TNV-3 is the application of "Insulation" between these two circuit types. There are many classifications for insulation between the TNV-3 and SELV. The most common requirement is that of "Basic Insulation". "Basic Insulation" defines the required distance across the Isolation barrier. The separation between the TNV-3 and the SELV portion of the circuit is also a function of the normal working voltage expected between the TNV-3 and the SELV, as well as the expected conductive dust conditions that may accumulate on the Isolation Barrier. For an international modem, under the worst-case conditions of ringing voltages and conductive dust particle pollution, the required minimum distance is 2.5 mm. This 2.5 mm distance is to be applied from any PCB trace between the TNV-3 area to SELV circuit and from any PCB trace between TNV-3 and local ground. This distance is measured by skimming the surface of the PCB and is called "creepage" in IEC 60950 terminology. Creepage distance is applied to prevent electrical arcing across conductors as a result of dust particle accumulation over a surface. Dust particle accumulation, over time, can degrade the isolation between conductors. Distance through air, called "clearance", does not have this dust particle accumulation problem. Hence, creepage distance is always larger than clearance. In the case of TNV-3 to SELV separation, the required minimum clearance is 2.0 mm. Since both clearance and creepage distance requirements need to be met, the larger value of creepage distance is used. Figure 30 shows an example of creepage distance and clearance. Conductor Creepage Figure 30. Clearance and Creepage Rev. 0.3 45 AN347 3.3.1.1. TNV Cover The IEC 60950 states that TNV-3 circuits must not be accessible to a casual user. The casual user is referred to as the "operator" in the IEC 60950. As mentioned previously, TNV-3 circuits are not considered touchable by operators. In the example of a PCI Modem inside a personal computer (PC), some countries consider operating a PC without the enclosure as a normal operating environment. As such, these countries will require a cover around the TNV-3 area. The TNV cover is intended to prevent an operator from touching live TNV-3 circuits when the PC is used without its primary enclosure. If the cover is made of plastic, there are no distance requirements between any exposed TNV-3 conductor and the plastic cover. If the cover is made of a conductive material, then the minimum distance of 2.5 mm "creepage" applies to the base of the metallic TNV cover and any TNV-3 trace. This 2.5 mm creepage distance is measured along the surface of the PCB. As indicated previously, the air-distance called "clearance" is required to be 2.0 mm, not 2.5 mm. Hence, the height of a metallic TNV cover is determined by the tallest conductive component on the TNV-3 Circuit area plus 2.0 mm. To build an international modem, it is best to make provisions for the TNV Cover. However, for cost purposes, ship the TNV cover only to countries that require them. The Professional Testing Agency should be knowledgeable as to which countries require a TNV cover. For instance, North America does not require the TNV cover as long as the documentation warns the user or operator to unplug the phone cord while installing the modem. 3.3.1.2. Isolation Barrier Capacitors In many designs, capacitors are used to bridge the Isolation Barrier. Silicon Laboratories' DAA solutions utilize a capacitive isolation barrier to perform the function of high-voltage isolation. High-voltage safety-rated capacitors are permitted to cross this barrier due to their construction and high-voltage rating. For our DAA circuit, these are C1, C2, C8, and C9. The IEC 60950 requires that this Isolation Barrier be suitable for "Basic Insulation". Figure 1 on page 4 shows an overview of how the isolation capacitors are used. Essentially, a capacitor that is able to reach across the 2.5 mm Isolation Barrier is considered to be "Basic Insulation." Conceptually, a capacitor is constructed so that two metal plates are separated by a suitable dielectric material. The dielectric acts as an insulator between the two metal plates. As long as the capacitor is able to withstand the "Dielectric Strength Tests," it qualifies as "Basic Insulation." In the process of having your product tested, the capacitors will be subjected to these electrical tests. High-voltage capacitors (2000 V) and Y2-class capacitors are able to withstand these tests. When submitting the product for testing, it is recommended that alternate sources for the Isolation Barrier capacitors be identified and tested. Not doing so may result in the need for re-testing and re-qualification of the system if a capacitor supplier is unable to meet delivery. Another item to consider are the footnotes in the IEC 60950 that require the isolation be upgraded to "Supplementary Insulation" for Nordic Countries. These footnotes are referred to as the "Nordic Exclusions". The Nordic Countries are Norway, Sweden, Finland, and Denmark. "Supplementary Insulation" has all the requirements of "Basic Insulation." In addition, the thickness of the dielectric material between the poles of the capacitor is governed by a "Minimum Distance Through Insulation" of 0.4 mm. Figure 31 illustrates "distance through insulation." 46 Rev. 0.3 AN347 Insulator or Dielectric Conductor Conductor Distance through Insulation Figure 31. Distance through Insulation Given this design constraint, the capacitor becomes physically larger. The IEC384-14 is the standard that governs the construction and certification of a capacitor suitable for applications that can be used to bridge "Supplementary Insulation." The capacitor suited for "Supplementary Insulation" is defined as a Y2 capacitor. Besides the minimum distance through insulation, a further design constraint of the Y2 capacitor is a 4 mm creepage distance between opposite poles of the capacitor. This design constraint requires a surface mount capacitor to be of size EIA 22xx or larger. For applications that do not have significant height constraints, it is recommended that ceramic disk packaging be used in lieu of a surface mount. The ceramic disk packaging requires two holes separated by 7.5 mm. There are many manufacturers who build Y2 capacitors that use the same 7.5 mm footprint. Among them are Panasonic, Murata, and Samsung. An inexpensive solution is to use all through-hole. A surface mount Y2 capacitor of size EIA 2220 is manufactured by Murata. Another option is to create dual footprint pad sites that can host either an EIA 2220 or an EIA 1808 capacitor. The resulting pad sites are "T" shaped. In this way, Y2 capacitors are used only for the Nordic countries and standard EIA 1808 capacitors for the rest of the world. It is recommended that an embedded modem or Si3056 chipsets design incorporate 5.0 mm of creepage from the TNV-3 traces in order to meet the 2.5 mm minimum requirements of IEC 60950 with an additional 2.5 mm of margin for improved surge performance. 3.3.2. CB Scheme The IEC System for Conformity Testing and Certification of Electrical and Electronic Components, Equipment and Products (IECEE) Certification Bodies (CB) Scheme is the worldwide system for mutual recognition of test reports and certificates dealing with the safety of electrical and electronic components, equipment, and products. It is a multilateral agreement among participating countries and certification organizations. A manufacturer utilizing a CB test certificate issued by one of the accepted National Certification Bodies (NCB) can obtain certification marks of the latter, within their scope of adherence, in the countries where the accepted NCBs are located. The Scheme is essentially based on the use of international (IEC) Standards. The CB Scheme utilizes CB Test Certificates to attest that product samples have successfully passed the test conditions and are in compliance with the requirements of the relevant IEC Standard(s). When applicable, the CB Test Certificate and its associated test report can also include declared national differences, Special National Conditions (SNC), and regulatory requirements of various member countries. The operators of the CB Scheme are the NCBs. An application for obtaining a CB Test Certificate may be made by an applicant to any Issuing and Recognizing NCB accepted for the relevant standard. The application shall be made and dealt with according to the rules of the Issuing and Recognizing NCB to which it is submitted. That NCB shall inform the applicant about the relevant rules and procedures and specimens needed for the testing. Upon receipt of an application for a CB Test Certificate, the relevant Issuing and Recognizing NCB shall arrange for testing of the relevant equipment. If the result of the tests is favorable, the NCB shall sign and issue a CB Test Rev. 0.3 47 AN347 Certificate to the applicant. The applicant may also request testing to cover national differences in countries in which the CB Test Certificate is to be used. If additional tests have been carried out, a report of the results may be attached to, and considered to be a part of, the Test Report. When an applicant applies to a Recognizing or to an Issuing and Recognizing NCB for national certification or approval of a product on the basis of a CB Test Certificate, the application shall be accompanied by a copy of the CB Test Certificate with the attached Test Report and, if relevant, attached reports covering national differences and, if required by the NCB, a specimen of the product. Also, an applicant shall follow the rules of procedure applicable in the country concerned and shall confirm readiness to comply with all the relevant national provisions regarding as if the equipment had been tested in accordance with the procedures valid in that country. The NCB shall examine the submitted CB Test Certificate and any required specimen to the extent considered necessary for the identification of the relevant equipment and for the recognition of the CB Test Certificate. If the result of this examination is favorable, national certification or approval shall be granted by the NCB without additional testing following its own statutes and rules of procedure. Currently, there are 50 countries represented by Member Bodies and NCBs participating in the CB Scheme for one or more standards. Please visit CB Scheme website (http://www.cbscheme.org) for a list of countries and more information about the CB Scheme. The relevant standard for Telecommunications (IT) and Information Technology (ITE) equipment under the CB Scheme is the IEC 60950. Each country may have requirements beyond IEC 60950. These national differences, called National Deviations, are covered by CB Bulletins. Many countries use the IEC 60950 document plus CB Bulletins as adequate specification for compliance. Occasionally, there are enough differences to warrant a separate standards document based on the IEC 60950. An example is the UL 60950 standard. The EN 60950 is a CENELEC (Comité Européen de Normalisation Electrotechnique) standard based on the IEC 60950. It covers the National Deviations applicable to the countries of the European Union (EU). There are 27 member countries currently joined in the EU: Austria, Belgium, Bulgaria, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, and the United Kingdom. The EN 60950 is also applicable to the following countries: Iceland, Norway, Switzerland, and Turkey. The UL 60950-1/CSA-C22.2 No. 60950-1-07 is a bi-national standard based on the IEC 60950. UL 60950 applies to the United States and Canada. 3.3.3. CE Marking The letters "CE" are the abbreviation of French phrase "Conformité Européene" which literally means "European Conformity". The CE Marking symbolizes the conformity of the product with the applicable European Directives. The CE Marking affixed to a product is a declaration by the manufacturer responsible that the product conforms to all applicable provisions and the appropriate conformity assessment procedures have been completed. The CE Marking is mandatory and must be affixed before any product subject to it is placed on the European Economic Area market (EEA, includes the EU countries plus Iceland, Liechtenstein, and Norway). The CE Marking is often referred to as the "Trade Passport to Europe". It is important to note that the CE Marking is not a certification mark issued by an NCB under the CB Scheme. Depending upon a product and the nature of the risks it presents, the typical process for CE Marking begins with the determination of any directives applied to the product, and more than one directive can apply to a single product. Generally, the directives that apply to IT and ITE equipment are as follows: Low Voltage Directive (LVD), Electromagnetic Emissions Directive (EMC), and the Radio and Telecommunications Terminal Equipment Directive (R&TTE). Then, determine the extent to which the product complies with the essential requirements for design and manufacturing in the applicable directive(s). Choose the conformity assessment procedure from the modules called out by the directive for the product. 48 Rev. 0.3 AN347 The directives often use a series of questions about the nature of the product to classify the level of risk. The products with minimal risk are allowed Self Certification where the manufacturer prepares a Declaration of Conformity along with Technical File and affixes the CE Marking to the product. Many directives require product with greater risks to be independently certified. This must be done by a "Notified Body". This is an organization that has been nominated by a Member Government and has been notified by the European Commission. Notified bodies serve as independent test labs and perform the steps called out by directives. They must have the necessary qualifications to meet the testing requirements set forth in the directives. Notified bodies may be a private sector organization or a government agency. Manufacturers may choose a notified body in any member state of the European Union. The list of the directives providing for CE Marking could be found at European Commision's website (http://ec.europa.eu/enterprise/newapproach/standardization/harmstds/reflist.html). Also, here is another website with useful CE Marking information at http://www.ce-marking.org. The Low Voltage Directive (CE Marking Directive 73/23/EEC as amended by 93/68/EEC) applies to product safety related to electrically operated devices. The EN60950 is used to show conformity to Annex I (Essential Requirements) of the LVD. 3.3.4. UL 60950 Over Voltage Testing UL60950-1 is the UL Standard for Safety for Information Technology Equipment. The current edition is the second edition and based on IEC 60950-1, second edition. The overvoltage tests are required only for United States and Canada. The tests simulate a crossing of power and telephone lines. This is due to the co-location of phone lines and power lines on the same utility pole network. In the event of a failure, such as a tree falling over utility lines, it is possible that the lines could cross, sending hazardous voltages across the phone line. This is not the case in Europe because the phone lines and power lines are on separate utility poles, or the utility lines are buried. The UL60950-1 overvoltage tests are defined in Subclause 6.4 and Annex NAC. When designing a product, it is important to obtain copies of the relevant standards for your reference. Assuming that the system is subjected to overvoltage tests, voltage is applied to the system as a "differential mode" or a "common mode." For the "differential" mode, also known as "metallic," voltage is applied between Tip and Ring, while other accessible conductors are grounded. For the "common mode" tests, Tip and Ring are tied together, and all other conductors are tied to ground. A voltage is then applied to both Tip and Ring. Another item of consideration is whether or not the modem is placed "on-hook" or "off-hook." For Silicon Labs DAA-based design, the loop current is actively controlled through Q3. However, this can be controlled only when the system is powered on. When the system is powered off, the system is always on-hook. During safety testing, the system is not powered on. To simulate an off-hook condition, the emitter and collector of Q3 are shorted together. This shorting of the collector and emitter of Q3 represents an artificial worst-case condition that will not happen in a real system. If the system were powered on as it needs to be to go off hook, excessive loop currents would be detected, and the system would be placed in the on-hook position before any damage could be inflicted on the modem. Even with the artificial condition of a shorted Q3, the submitted Silicon Labs DAA-based design passed. Figure 32 shows the devices most affected by the off-hook condition. Rev. 0.3 49 AN347 FB1 TIP Line Side Device 2 Q1 Q2 1 + D1 _ 4 FB2 3 Z1 RING Q3 Figure 32. Devices Most Affected by Overvoltages and Overcurrents (Off-Hook Case) In all of the overvoltage tests, two layers of cheesecloth are tightly wrapped around the system, or subassembly. To pass the tests, the cheesecloth must not ignite. The key concept to remember is that the manufacturer has the choice of where the cheesecloth is applied by defining the assembly, or sub-assembly. For instance, for a PCI Modem, it is possible to test the PCI Modem sub-assembly separate from the PC. If the PCI Modem sub-assembly is tested outside the PC system, the cheesecloth is wrapped around the PCI modem subassembly. The PC manufacturer may choose to test the entire PC system with the modem already installed. It is up to the manufacturer to define the boundary of the system. The goal is to show compliance to the UL60950-1 standard. It will be shown later how overvoltage testing can be minimized. To pass the overvoltage tests, the cheesecloth around the system or sub-assembly should not ignite or char. After each of the overvoltage tests, the system is subject to a dielectric strength test to ensure that the Isolation Barrier is intact. UL60950-1 defines five overvoltage tests. Test 1 and Test 5 are not discussed. It will be shown later that it is simple to bypass Test 1. It will also be shown later that Test 5 is usually unnecessary. Test 2 subjects the system to 600 V at 7 A for 5 seconds. It is important to note that this is the only test conducted that has a maximum current of 7 A (assuming Test 1 is omitted). Test 3 subjects the system to 600 V at 2.2 A per Test Duration. An additional test, Test 3A, is done only if an open circuit results from Test 3. For Test 3A, the fuse is shorted and the system is subjected to 600 V at 135% of the fuse rating per Test Duration. Test 4 subjects the system to a voltage just below the tripping voltage of a voltage protection device (Sidactor). For example, 200 V at 2.2 A per Test Duration. When overvoltage tests are performed, a passing mark means the cheesecloth did not char or catch fire, the wiring simulator did not open (Test 1 and 5 only), and the dielectric strength test (conducted after each overvoltage test) shows the isolation barrier is not damaged. 50 Rev. 0.3 AN347 3.3.4.1. Minimizing UL 60950-1 Overvoltage Tests This paper presents Figure 6C of the UL60950-1 specification in a slightly different way. This method of presentation is designed to highlight the effect of system elements on the required overvoltage tests. Table 30 shows a simplified matrix to determine if overvoltage Tests 1 and 5 are required. Test 1 and the requirement of 26 AWG wire are directly linked. Test 5 and the requirement of passing Subclause 6.1.2.1 of the UL 60950-1 are directly linked. Subclause 6.1.2.1 defines the requirements for separation of the telecommunications network from earth ground. Table 30. System Element vs. Overvoltage Tests System Element Overvoltage Tests 26 AWG Test 1 No Required Yes Skip Pass 6.1.2.1 Test 5 No Required Yes Skip It is important to remember that the goal of the overvoltage tests is to reduce the risk of fire. As such, there are nonelectrical system elements, such as fire enclosures and spacings, to consider. In most cases, the system will not have to be subjected to Test 1. To remove the requirement for Test 1, there must be a warning in the documentation or on the product. An example is shown below. Caution:To reduce the risk of fire, use only No. 26 AWG or larger telecommunication line cord. Another method of skipping Test 1 is to supply a phone cord (AWG 26) with the product as well as sufficient instructions to indicate that the product must be used with the enclosed phone cord, or an equivalent phone cord, to reduce the risk of fire. The manufacturer only needs to guarantee that the wire from the modem to the phone jack on the wall uses 26 AWG cord. The wire within the building is not included in the safety assessment because it is the builder's responsibility to use 26 AWG phone wires throughout the building. Test 5 can be skipped if the product complies with the testing of Subclause 6.1.2.1 of the UL 60950-1. Table 31 shows the remaining overvoltage test (Tests 2, 3, 3A, and 4) required for different system configurations. Table 31. System Element vs. Overvoltage Tests System Elements Overvoltage Tests Fuse Fire Enclosure Spacing Test 2 Test 3, 3A, 4 No No Don’t Care Required Required Yes No Don’t Care Skip Required No Yes No Required Required No Yes Yes Skip Skip Yes Yes Don’t Care Skip Skip Rev. 0.3 51 AN347 If a fuse is used, the fuse must be 100 A2-s limiting and have a 1.3 A maximum steady state current. Typically, a fuse or PTC manufacturer will state in their literature that the product is compliant with UL60950 power cross tests. Surface mount fuses are available. In choosing a fuse or PTC, consult with a UL engineer to ensure that it is suitable for this application. A fire enclosure is used to prevent the spread of a fire originating from the equipment. The precise characteristics that make a fire enclosure are beyond the scope of this paper. The important thing to remember is that the system element of a fire enclosure is the key to eliminate the overvoltage tests. A good example for a fire enclosure is a PC Chassis. The system element “spacing” in Table 31 refers to an air distance of 25 mm between the TNV-3 circuit and materials of flammability V-2 or greater. No spacing is required if the TNV-3 circuit is next to materials of class V-1 or better. In addition, if the TNV-3 circuit is adjacent to an opening on the fire enclosure, then there are restrictions on the size of the openings on the enclosure. If the material adjacent to the TNV-3 circuit is unknown or unspecified, it is assumed to be of flammability V-2 or worse. Table 31 illustrates that it is possible to skip all of the overvoltage tests under certain conditions. It also shows that inclusion of a fuse in the system has limited value. A fuse without a fire enclosure makes it possible to skip Test 2. But, since Tests 3 and Tests 4 are required anyway, it may make sense to simply not have a fuse and subject the system to Tests 2, 3 and 4. The only value in skipping Test 2 is that Test 2 is a 7 A test, while the other tests are 2.2 A tests. A fuse in a system with a fire enclosure, provides a slight advantage by eliminating the requirement of spacing between the TNV-3 circuit and adjacent materials. A PCI Modem being tested by a PC manufacturer is a good example. A PCI Modem is mounted into a PCI slot. Perhaps the card is facing the rear of a Video Card. As long as there are no tall components mounted on the rear of the Video Card, the minimum spacing of 25 mm is met simply because the PCI slots are separated by slightly more than 25 mm by design. The PC chassis is considered a fire enclosure. Assuming that the user instructions include directions that indicate the phone cord must be of 26 AWG or better, no overvoltage tests are needed. If the phone cord of 26 AWG is supplied, the system will not require overvoltage tests. Consider the scenario in which this system is subjected to an actual power cross. The cord from the wall to the PC will not overheat and present a fire hazard because the phone cord is 26 AWG or better. The worst-case scenario is that the PCI modem ignites. If the PCI modem ignites, it is separated from the video card by 25 mm. At the very worst, it will expel carbon debris to the back of the video card. The PC chassis is in a fire enclosure and thus provides another level of protection. Consequently, the sample system above passes the requirements of UL60950-1 without subjecting the system to overvoltage tests or the addition of a fuse. The system passes the UL60950-1 simply by documentation and fire enclosure construction. Now consider a laptop with an integrated modem on the motherboard. Depending on the enclosure material used, the laptop may not be considered a fire enclosure. In this case, a metal enclosure around the TNV-3 circuit may need to be designed so that overvoltage testing can be bypassed. Another option is to omit any fire enclosure and subject the laptop to overvoltage testing. There are many options available for compliance to the UL60950-1. As mentioned earlier, construction of the system has a large effect on the number and severity of the overvoltage tests required. It is important to remember that compliance to UL60950-1 does not always require overvoltage tests. It is best to plan ahead and know which overvoltage tests will apply to your system. System-level elements in the construction need to be considered during the design stages. Consult with your Professional Testing Agency during the design of the product to determine which tests apply to your system. 52 Rev. 0.3 AN347 3.3.5. UL1950 3rd Edition Although designs using the Si3056 comply with the UL1950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 33 shows two designs that can pass the UL1950 overvoltage tests and electromagnetic emissions. The top schematic shows the configuration in which the ferrite beads (FB1 and FB2) are on the unprotected side of the sidactor (RV1). For this configuration, the current rating of the ferrite beads needs to be 6 A. However, the higher current ferrite beads are less effective in reducing electromagnetic emissions. The bottom schematic of Figure 33 shows the configuration in which the ferrite beads (FB1 and FB2) are on the protected side of the sidactor (RV1). For this design, the ferrite beads can be rated at 200 mA. In a cost-optimized design, compliance to UL1950 does not always require overvoltage tests. Plan ahead to know which overvoltage tests apply to the system. System-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. Consult with a professional testing agency during the design of the product to determine which tests apply to the system. C8 75 at 100 MHz, 6 A FB1 1.25 A TIP RV1 75 at 100 MHz, 6 A FB2 RING C9 C8 600 at 100 MHz, 200 mA FB1 1.25 A TIP RV1 600 at 100 MHz, 200 mA FB2 RING C9 Figure 33. Circuits that Pass all UL1950 Overvoltage Tests Rev. 0.3 53 AN347 3.3.6. Steps to Safety Compliance A Professional Testing Agency is a privately or publicly owned consultation company that can act in the capacity of a CB Test Laboratory, an agent to an NCB, an NCB, a CE Notified Body, an agent to a Certification Agency, a safety consultant, and other capacities. The Professional Testing Agency is in the business of providing services for compliance testing. When looking for a Professional Testing Agency, a good place to start is the list of Certification Agencies. Many of these Certification Agencies are also CB Test Laboratories, NCBs, and CE Notified Bodies. The general steps in getting CE Marking, CB Test Report and Certificate, and other Certification Marks are as follows: 1. Product Development Engineering should assess the product for safety-related issues. If UL1950 compliance is required, there are system-level construction issues that need to be considered at this time. 2. Assign a Compliance Test Engineer who is familiar with the product to be tested. The Compliance Test Engineer will work with the Professional Testing Agencies. There may be more than one agency involved, depending on the services provided by the Testing Agency. 3. Select a Professional Testing Agency. The following is a checklist for choosing a testing agency: Has Test Setups required for IEC 60950 electrical testing. Receives CB Bulletins on a regular basis.  Has Knowledge of National Deviations pertaining to the countries you want to enter. At the very least, must be familiar with EN 60950.  Has UL60950-1 Overvoltage Test Setup if North America is included in the target countries.  Has a good understanding of how to achieve UL60950-1 compliance.  Can act as an agent on your behalf, for submission of CB Test Report and Certificate to obtain Certification Marks required.  Has experience writing CB Test Reports and Certificates for ITE/TE appliances.  Has experience preparing Declaration of Conformance and Test Files for CE Marking. 4. Submit samples of your product to the chosen Professional Testing Agency to perform the actual electrical test and measurement of creepage and clearance. If UL 3rd Edition Overvoltage Testing is involved, it is important to plan ahead as to the number of overvoltage tests that will be done. The overvoltage tests may render the product inoperable after the tests.   5. The Professional Testing Agency writes the CB Test Report when the product meets the requirements for safety. 6. The Professional Testing Agency submits the CB Test Report to the NCB to obtain the CB Certificate. 7. Typically, the first Certification Mark is obtained from the NCB issuing the CB Certificate. 8. The CB Test Report can be used to show conformance to the LVD Directive. The Professional Testing Agency compiles the CE Test File, which contains a copy of the CB Test Report. 9. The Professional Testing Agency compiles the Declaration of Conformity for the LVD Directive. An officer of the company will sign the Declaration of Conformity for the LVD Directive. Assuming that the other CE directives are met (e.g., EMC Directive) and all documents are in order, the product may be shipped with the CE Marking. 10. Work with the Professional Testing Agency to submit a sample of the product, CB Test Report and Certificate, and Signed Application Forms (supplied by Certification Agency) to other Certification Agencies for obtaining their Certification Marks. 54 Rev. 0.3 AN347 3.4. Emissions The Si3056 reference designs incorporate population options for resistors or ferrite beads that provide suppression of radiated emissions. This section is intended to help the system designer understand the purpose and selection criteria of these components. The reference designators for the required ferrite beads are FB1/FB2. There are also placeholders in the application circuit for optional components at R12/R13 and R15/R16. Some systems may require the optional components at the R12/R13 and/or R15/R16 positions to provide the necessary suppression for radiated emissions requirements. Some system designs may require optional components at all six locations. Because each system is unique from an EMC perspective, some may require the recommended population options at the other sites in order to meet all necessary regulatory requirements. If a modem is designed for multiple systems, a conservative approach would be to adopt all the recommended population options listed in Table 32. This configuration is particularly useful in applications where the modem will be tested in only one system but deployed into numerous other systems over the product's lifetime. Because changes made to the modem design to combat EMC issues could cause a re-homologation of the design, this approach may allow future systems to pass without component changes at these reference designator locations. It is important to note that Silicon Laboratories has performed extensive testing to verify that the R12/R13 population option effectively reduces emissions without impacting other aspects of the design's performance. Installation of any other component and/or value could cause the modem to fail other compliance requirements. Do not populate ferrite beads at the R12/R13 location. The recommended device (required if additional suppression is needed) for R12/R13 is a 56 , 1% resistor. After the final radiated emissions suppression configuration has been developed, the modem should be tested against all other relevant EMC specifications, including conducted immunity and conducted emissions. Table 32 outlines the recommended part numbers and component values for the EMC population options in the design. Table 32. Recommended Si3056 Population Options to Reduce Radiated Emissions Reference Designator Required Part #/Mfgr Component Value FB1/FB2 Yes Murata BLM18AG601SN1* Ferrite Bead, 200 mA, DCR<2.5 Ω R12/R13 System Dependent Recommended R15/R16 System Dependent Recommended Any 1% tolerance resistor Resistor, 56 Ω, 1/16 W, 1% Murata BLM18AG601SN1* Ferrite Bead, 200 mA, DCR<2.5 Ω *Note: Various 200 mA ferrite beads have been used for FB1/FB2 R15/R16, and these devices should be selected depending upon the radiated noise and conducted immunity performance of a particular modem and system combination. Rev. 0.3 55 AN347 4. Layout Guidelines 4.1. Placement Guidelines The key to a good layout is the proper placement of components. It is best to copy the placement shown on our evaluation boards. Figure 34 depicts typical placement of the chipset, discrete components, and the RJ11 connector for the Silicon Labs DAA. Note the placement of U1 (the digital side chip) and U2 (the line side chip). U1, U2, R12, R13, C1, and C2 should be placed and grouped so that the traces from U1 to U2 through the C1 and C2 capacitors are direct and short as well as physically separated from traces connected to C8/R15/FB1 and C9/R16/FB2. Place R12 and R13 near the C1A and C2A pins on the digital side chip. Use at least 15 mil thick traces for this connection. Aligning the digital side chip so that the C1A/C2A pins face pins 1–8 of the line side chip makes some of the other specific layout guidelines easier to implement. Figure 34. Typical Placement for DAA Circuit 4.2. Isolation Barrier Creepage Spacing Considerations All traces, open pad sites, and vias connected to the components inside the area surrounded by the rectangle in the typical schematic are considered to be in the DAA section (TNV). The isolation capacitors C1, C2, C8, and C9 are the only components permitted to straddle between the DAA section and non-DAA section components and traces. This means that, for each of these capacitors, one of the terminals is on the DAA-side, and the other is not. Maximize the spacing between the terminals (between pin 1 and pin 2) of each of these capacitors. If possible, use through-hole Y2 class capacitors for the C1, C2, C8, and C9 components, and ensure at least a 5 mm wide isolation barrier from TNV (DAA section) to SELV (non-DAA circuits). A properly-implemented design using these guidelines should provide a minimum of 5 kV of longitudinal surge immunity. 4.2.1. Power Supply Bypass Capacitor Layout Requirements On the Si3056, one of the main layout considerations for the digital side chip (U1) is the placement of the bypass capacitors (C50 and C51). Capacitors C50 and C51 are the bypass capacitors for VA and VD, respectively. Figure 35 shows a typical placement of C50 and C51. The designer should focus on minimizing the length of the C50 connection between the VA and GND pins and the length of the C51 connection between the VD and GND pins on U1. 56 Rev. 0.3 AN347 Figure 35. Si3056 Placement and Routing of C50 and C51 4.3. Line Side Chip Layout Recommendations FB1, FB2, RV1, R15, R16, C8, and C9 should be placed and grouped as close as possible to the RJ11 as shown in Figure 36. The metallic surge protection device (RV1) should be located close to the RJ11 connector. It is important for the routing from the RJ11 connector through the ferrite beads FB1 and FB2 and the resistors R15 and R16 to be well matched. C8 and C9 should be placed so there is minimal distance between the nodes where they connect to digital ground. The traces from the TIP and RING connections on the RJ11 through EMC capacitors C8 and C9 to digital ground should be kept as short as possible and should be well matched. Keep C8 and C9 away from C1 and C2. If possible, make sure that C1/C2 are oriented perpendicularly relative to C8/C9. Use 20 mil width traces on this grouping to minimize impedance. Figure 36. Typical Placement and Routing of FB1, FB2, RV1, C8, C9, R15, and R16 After the system side device (U1), the line side device (U2), C1, and C2 have been placed, and after the isolation barrier has been defined according to the recommendations described previously in this document, the designer should place and group R9, C5, C6, R7, and R8 (R19, R20, R21, C5, C11, C12, R7, and R8 for Si3009-based DAA) around U2. These components should form the critical "inner circle" of components around U2. Capacitors C5/C6 provide regulation of the supplies powering U2. Rev. 0.3 57 AN347 The loops formed by the capacitors to pins VREG and IGND of U2 should be made as small as possible. The traces back to pin IGND are thicker because multiple loops use this path. Place U2, transistors, and the high-power dissipating resistors, R1, R3, R4, R10, and R11, away from each other for optimal thermal performance. Make the size of the transistor collector pads sufficiently large to safely dissipate 0.15 W under worst-case conditions. See the transistor data sheet for thermal resistance and maximum operating temperature information. Implement collector pads on both the compound and solder side, and use vias between them to improve heat transfer for best performance. Place the capacitor, C3, across the diode bridge, and route the accompanying traces from the line side device through the capacitor to the IGND pin. The area of the loop formed from the line side device through the capacitor to the diode bridge and back to IGND should be minimized. IGND is the ground return path for many of the discrete components and requires special mention. Route traces associated with IGND using 20 mil traces. The area underneath U2 should be ground-filled and connected to IGND. Ground fill both the solder side and the component side, and stitch together using vias. The capacitors, C5 and C6, IGND return path should be direct. The IGND plane must not extend past the diode bridge. The traces from R7 to FB1 and from R8 to FB2 should be well matched. This can be achieved by routing these traces next to each other if possible. Ensure that these traces are not routed close to the traces connected to C1 or C2. For Si3018-based DAA, once these components have been placed, the designer can continue with the layout by adding Q4, Q5, R2, and R9. All traces connecting these components should be 15 mil in thickness. Place Q4 so that the area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the emitter of Q4 is minimized. Place Q5 so that the loop from pin 16 through R2 to the base of Q5 and through the emitter to pin 14 is short. The loop formed from U2 pin 4 to R9 to U2 pin 15 should also be made as small as possible. The IGND traces are those traces that connect directly from a capacitor or resistor to pin 15 of the line-side device. They should be routed on the PCB using 15 mil width traces. Example layout of these critical traces and components around the line side device are shown in Figure 37. Figure 37. Typical Placement and Routing of C3, Diode Bridge, Q4, Q5, R9, R2, C5, and C6 Finally, the layout can be completed by the addition of the remainder of the components in the line side region and routing of the remainder of the signals. Although the layout considerations for these traces are not as stringent as the previous components and traces, it is recommended that the PCB designer follow these example placements and layouts as closely as possible. Example layout is shown in Figure 38. 58 Rev. 0.3 AN347 Figure 38. Finished Layout Line Side Portion 4.4. Assembly Considerations There are several steps that can be taken in layout to ensure that the assembly process is successful. An example of an assembly-related error is the installation of a polarized capacitor with the polarity backwards. Stenciling the board with a plus sign on the correct side of C4 if a polarized capacitor is used to indicate the proper orientation for that capacitor can prevent this. Also, indicating pin 1 on the board with a stencil marking improves the chances that the integrated circuits will be installed correctly. The silkscreen for Z1 should also have a marking to indicate the cathode placement. The designer should use several footprints for a given component to allow for multiple vendor choices. Popular components using multiple footprints are C1, C2, C8, C9, and Z1. Finally, all 3-pin device orientation should be carefully checked to ensure that it matches the schematic symbol and routing implementation. Taking these steps will assist in the assembly process and ease future troubleshooting and substitutions. 4.5. Embedded DAA Layout Guidelines 4.5.1. Tip/Ring Motherboard Routing and Safety Regulatory Considerations The IEC 60950 requirements for creepage and clearance from TNV to SELV circuitry must be maintained for the connector Tip/Ring signal terminations. Tip and ring signals should be a minimum of 15 mils wide with sufficient copper weight (e.g. 1.0 oz/sq. ft. before plating) to meet all applicable safety and regulatory surge requirements. With this configuration, the tip and ring traces should be routed on the top/component layer only, with no vias, directly to the RJ11 connector terminations. There must be a minimum 2.5 mm of creepage separation from the Tip/Ring traces to any adjacent SELV components, traces, or pads on the same layer. SELV signals may only be routed on layers underneath Tip/Ring if there is greater than 2.5 mm of creepage distance between the TNV and SELV traces. In all areas of the board, 5 mm of creepage distance is recommended from TNV to SELV. No digital or SELV traces can be routed underneath the tip/ring traces. Thus, in this configuration, most implementations require that the line-side IC layout be placed very close to the RJ11 connector to minimize the length of the additional Tip/Ring traces on the motherboard. Rev. 0.3 59 AN347 4.5.2. Routing Considerations of Traces from the Embedded DAA to Line Side Circuit The following guidelines describe the considerations for the C1A/C2A to C1B/C2B traces or the signals between the ASIC and the line side circuit. Typically, the line side circuit layout can be placed up to maximum of 15 cm away from the system-side module integrated into the host ASIC. This distance is affected by the amount of parasitic capacitance that the C1A/C2A to C1B/C2B traces add to the impedance of these signals. Use C1A/C2A to C1B/C2B board traces that are routed directly from the ASIC to the line-side circuit, as short as possible, with 6 mil to 10 mil wide, well-matched trace lengths, 20 mils apart, up to a maximum length of 6 inches (15 cm) and an optimal trace capacitance of 8 pF for each trace. Routing these traces as short as possible should be the primary concern when placing devices on the board and routing the signals. If possible, route them on the same layer as the ICs to minimize or eliminate the number of vias in this route. Avoid routing the C1A/C2A to C1B/C2B traces on the layer next to a ground plane on the layer immediately below or above these signals. It may be acceptable to void the ground plane in a "channel" on the layer immediately below the C1A/C2A to C1B/C2B traces. If it is necessary to route them over a ground plane, ensure that the traces are on a PCB layer as far away from the ground plane as possible. Ideally, these traces should be on the component side, with minimal vias, routed using a straight, direct path from the host processor ASIC/DAA systemside device to the line-side circuit. A small number of turns in this signal routing has proven robust, but the number of turns in this route should be minimized. Separate adjacent ground or other traces on the same layer as the C1A/C2A to C1B/C2B traces at least twice the distance from these traces as they are separated from each other. For example, if the C1A/C2A and C1B/C2B traces are 10 mils apart, ensure that there is a minimum spacing of at least 20 mils from either of the C1A/C2A to C1B/C2B traces to adjacent ground plane or traces on the same layer. See Figure 39 for an example layout. Do not route other signals in the area directly between the C1A/C2A and C1B/C2B traces. These signals are a differential pair, and should be of matched length, routed close together, with no signals or ground fill between them. After the traces have been placed, estimate the trace parasitic capacitance (Co) based on trace length, trace width, pcb stack-up dimensions, and relative permittivity of the pcb dielectric, r. If necessary, adjust the layout to ensure that each trace does not exceed 6 inches (15 cm) in length. An optimal design goal for Co is 8 pF or less. ASIC including Embedded DAA Place R15/R16 (56.2 1%) resistors close to the ASIC. C1A C2A Ground plane on same layer Route traces close together, wellmatched in length, on the component side if possible, or with minimal vias. Ground plane on same layer 20 mil minimum 20 mil 6 mil C1B C2B Line-Side IC + BOM 20 mil minimum RJ11 Figure 39. Example Layout of the Routing of C1A/C2A to C1B/C2B Traces between the ASIC and Line Side DAA 60 Rev. 0.3 AN347 4.6. Layout Checklist Table 33. Layout Checklist  # Layout Items 1 U1 and U2 are placed so that pins 11–20 of U1 are facing pins 1–8 of U2. C1 and C2 are placed directly between U1 and U2. Keep R12 and R13 close to U1. 2 Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for the target application is implemented. 3 C1 and C2 should be placed directly between U1 and U2. Short, direct traces should be used to connect C1 and C2 to U1 and U2. These traces should never be longer than two inches and should be minimized in length. Place C2 such that its accompanying trace to the C2B pin (pin 6) on the Si3018/19/10 is not close to the trace from R31 to the RNG1 pin on the Si3018/19/10 (pin 8). 4 Place R30–R33, and C30–C31 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9), ensuring a minimum trace length from the RNG1 or RNG2 pin to the R31 or R33 resistor. In order to space the R31 component further from the trace from C2 to the C2B pin, it is acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8). 5 The area of the loop from C50 to U1 pin 17 and from C51 to pin 16 back to pin 18 (DGND) should be minimized. The return traces to U1 pin 18 (DGND) should be on the component side. 6 The digital ground plane is made as small as possible, and the ground plane has rounded corners. 7 Use a minimum of 15 mil width traces in DAA section, use a minimum of 20 mil width traces for IGND. 8 C3 should be placed across the diode bridge, and the area of the loop formed from Si3018/19/10 pin 11 through C3 to the diode bridge and back to Si3018/19/10 pin 15 should be minimized. 9 FB1, FB2, R15, R16, and RV1 should be placed as close as possible to the RJ11. Required 10 C8 and C9 should be placed so that there is a minimal distance between the nodes where they connect to digital ground. 11 Use a minimum of 20 mil wide trace from RJ11 to FB1, FB2, R15, R16, RV1, C8, C9, and F1. 12 The routing from TIP and RING of the RJ11 through the ferrite beads should be well matched. 13 The traces from the RJ11 through the Ringer Network to U2 pin 8 and pin 9 should be well matched. These traces may be up to 10 cm long. 14 Distance from TIP and RING through EMC capacitors C8 and C9 to digital ground is short. 15 There should be no digital ground plane in the DAA Section. 16 Minimize the area of the loop from U2 pin 7 and pin 10 to C5 and C6 and from those components to U2 pin 15 (IGND). 17 R2 should be placed next to the base of Q5, and the trace from R2 to U2 pin16 should be less than 20 mm. Rev. 0.3 61 AN347 Table 33. Layout Checklist (Continued) 18 Place C4 close to U2 and connect C4 to U2 using a short, direct trace. 19 The area of the loop formed from U2 pin 13 to the base of Q4 and from U2 pin 12 to the emitter of Q4 should be minimized. 20 The trace from C7 to U2 pin 15 should be short and direct. 21 The trace from C3 to the D1/D2 node should be short and direct. 22 Provide a minimum of 5 mm creepage (or use the capacitor terminal plating spacing as a guideline for small form factor applications) from any TNV component, pad or trace to any SELV component, pad or trace. 23 Do not use printed spark gaps. 24 Minimize the area of the loop formed from U2 pin 4 to R9 to U2 pin 15. 25 Cathode marking for Z1. 26 Pin 1 marking for U1 and U2. 27 Space and mounting holes to accommodate for fire enclosure if necessary. 62 Rev. 0.3 AN347 5. DAA Trouble Shooting Guidelines This section provides tips for the debugging of initial prototypes. Although most Si3056 prototype designs function as expected, there is the potential for layout errors, omitted or incorrect components used in the initial assembly run, and host software problems. If the prototype modem does not function correctly, the techniques outlined in this guide will help to quickly isolate the problem and get the prototype functioning correctly. A functional Si3056/3018EVB and data sheet and a computer with HyperTerm are required for some of the troubleshooting steps. It is assumed that the designer has read the data sheet, used the reference design and recommended bill of materials, and carefully followed the layout guidelines presented in the last section. The troubleshooting steps begin with system-level checks and proceed to the component level. 5.1. Visual Inspection Before troubleshooting, be certain that the circuit boards and components are clean. Carefully wash the boards to remove all solder flux and solder flakes. Inspect the modem circuitry to ensure all components are installed, and inspect all solder joints for incomplete connections, cold solder joints, and solder bridges. Check all polarized components, such as diodes, Zener diodes, and capacitors for correct orientation. Thoroughly clean the circuit board after replacing a component or soldering any connections. 5.2. Basic Troubleshooting      Check Power With power off, use an ohmmeter to verify that the system ground is connected to Si3056 pin 12. Turn on system power, and measure the voltage between pin 4 and pin 12 on the Si3056. The voltage should be 3.3 V. If this is not the case, check the power routing. If power is present, go to the next step. Check Phone Line Check the phone line with a manual telephone to be sure that there is a dial tone and that dialing is possible. The dc voltage across TIP and RING should read approximately 40–52 V with the phone on-hook. Reset Modem Be sure the modem is properly reset after power is applied and stable, or do a manual reset on the modem by holding Si3056 pin 8 (RESET) low. Check Modem Configuration Read back the modem register settings and correct any inconsistencies. Check AT Command The modem should respond with an "OK" to the command "AT<cr>." This indicates that the host processor/software is communicating with the modem digital side chip, Si3056. 5.3. Validation If the modem does not go off-hook and draw loop current as a result of giving the off hook command (ATH1) with receiving an "OK" message, check all solder joints on the isolation capacitors, the line side chip, and associated external components. If no problems are found, a known good Si3056 evaluation board can be substituted for debug. Substituting a known operational modem can help to quickly isolate problems. Before the substitution, connect the evaluation board to a PC and a phone line or telephone line simulator. Using a program, such as HyperTerminal, make a data connection between the evaluation board and a remote modem. This procedure verifies the evaluation board functionality. Disconnect the line-side device with associated components from both evaluation board and the prototype modem by lifting one end of the isolation capacitors, C1/C2. The end of C1/C2 that is connected to the line side device should be lifted. Then, solder a short jumper wire from the unconnected end of C1/C2 on the evaluation board to the unconnected pad of C1/C2 on the prototype system. This connection is illustrated in Figure 40. Connect the phone line to the prototype system RJ-11 jack. Rev. 0.3 63 AN347 Prototype Modem Si3056 Line Side Devices Discretes Line Side Devices Discretes Line EVB Modem Si3056 Line Figure 40. EVB Substitution Connection 1 Power up and manually reset the evaluation board; then, power up the prototype system. Attempt to make a connection using the prototype system. If this connection is successful, the problem lies with the PCB layout, the external components associated with the Si3056 or the Si3056 device itself. If the connection attempt is not successful, the problem lies with the line side device and/or associated components. Proceed to the next section. This diagnosis can be validated by connection as shown in Figure 41. Prototype Modem Si3056 Line Side Devices Discretes Line Side Devices Discretes Line EVB Modem Si3056 Figure 41. EVB Substitution Connection 2 64 Rev. 0.3 Line AN347 5.4. DAA Troubleshooting Start by measuring the on-hook and off-hook voltages at the line side device pins with respect to IGND. Compare these voltages to those in Figure 42. The voltages you measure should be close to (although not exactly the same as) those in the figure. On-Hook Off-Hook 0V QE DCT2 0V DCT IGND 0V RX DCT3 0V 0V IB 0.5 V 0.9 V 0V 1.6 V QE DCT2 2.2 V 3.4 V DCT IGND 0V 2.5 V RX DCT3 1.6 V QB 0V 0V FB QB 2.8 V C1B QE2 0V 0.5 V CIB QE2 2.1 V C2B S2 0V 0.9 V C2B SC 0V 2.3 V VREG VREG2 1.8 V ~1.0 V 1.0 V RNG1 RNG2 0.9 V ~2.3 V VREG VREG2 ~1.0 V RNG1 RNG2 0V Voltages measured with respect to IGND (Si3018 pin 15) Figure 42. Si3018 Typical Pin Voltage If any of the on-hook and off-hook line side device pin voltages are grossly different than those in the figures and nothing seems wrong with the external circuitry after using the component troubleshooting techniques described below, replace the line side device. A digital multimeter is a valuable tool for verifying resistances across components, diode directions, transistor polarities, and node voltages. During this component troubleshooting phase, it is very useful to have a known, good evaluation board to compare against measurements taken from the prototype system. The resistance values and voltages listed in Tables 34–36 will generally be sufficient to troubleshoot all but the most unusual problems. Start with power off and the phone line disconnected. Measure the resistance of all line side device pins with respect to IGND. Compare these measurements with the values in Table 34. Next, measure the resistance across the components listed in Table 35 and compare the readings to the values listed in the table. Finally, using the diode checker function on the multimeter, check the polarities of the transistors and diodes as described in Table 36. The combination of these measurements should indicate the faulty component or connection. If none of the measurements appears unusual and the prototype modem is not working, replace the line side device. Rev. 0.3 65 AN347 Table 34. Measured Si3018 Pin Resistance Pin # Resistance 1 >6 M 2 >5 M 3 >2 M 4 1 M 5 >5 M 6 >5 M 7 >1 M 8 >2 M 9 >2 M 10 >1 M 11 0 12 >2 MΩ 13 >5 M 14 >14 M 16 >5 M Table 35. Resistance across Components (Si3018-Based DAA) 66 Component Resistance FB1/FB2 <1 RV1 >20 M R1 1.07 k R2 150  R3 3.65 k R4 2.49 k R5/R6 100 k R7/R8 4.5 or 16 M R9 >800 k R10 536  R11 73  R12/R13 56.2  R15/R16 <1  C1/C2 >20 M C3 >3 M C4 3.5 or 9.7 M C7 2 or 5 M C8/C9 >20 M Rev. 0.3 AN347 Table 36. Voltage across Components with Diode Checker (Si3018-Based DAA) Component Voltage Q1, Q3, Q4, Q5 Base to Emitter 0.6 V Base to Collector 0.6 V Verify transistors are NPN Q2 Emitter to Base 0.6 V Collector to Base 0.6 V Verify transistors are PNP Q2 collector to Si3018 pin 1 If test fails, Z1 is reversed Rev. 0.3 >1 V 67 AN347 6. Previous Application Notes Replaced by AN347 The following application notes have been incorporated into this application note.          68 AN13: Silicon DAA Software Guidelines AN16: Multiple Device Support for the Si3034/35/44/56 AN17: Designing for International Safety Compliance AN67: Si3050/52/54/56 Layout Guidelines AN69: The Brazil Overvoltage Algorithm AN72: Ring Detection/Validation with the Si305x DAAs AN81: Si305x-Based Modem Emissions Design Considerations AN84: Digital Hybid with the Si305x DAAs AN297: Embedded Silicon DAA Layout Guidelines Rev. 0.3 AN347 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2  Updated "1. Introduction" on page 1. Added new DAA information. Added " Functional Block Diagram" on page 1.  Corrected Figure 9 on page 10.  Updated figure from Si3021 to Si3056. Revision 0.2 to Revision 0.3 Added "3.2. Other Country Requirements" on page 44.  Updated "3.3. Safety" on page 44.  Added “UL1950 3rd Edition”. Rev. 0.3 69 Smart. Connected. Energy-Friendly Products Quality Support and Community www.silabs.com/products www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Trademark Information Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com

DAA Design Guide -- AN347

Related documents

Add this document to collection(s)

Add this document to saved

Suggest us how to improve StudyLib