This on board power system controller provides a flexible, cost
effective, and high performance solution for controlling, monitoring,
and sequencing multiple Point of Load (PoL) converters on a system
board. The controller uses a digital signal processor (DSP) engine and
Bel’s firmware to implement a portfolio of board level control features
typically required in a multiple voltage power system. This device can
monitor and control (with active trim) up to eight PoL converters and
monitor up to four analog inputs and supports two independent zones.
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Digital Signal Processor (DSP) Based with Bel Firmware
Provides Power Up and Power Down Sequencing Logic
Stand Alone or Command Based
Fault Detection and Reporting
64-Pin 10mm x 10mm TQFP package
I2C, SMBus, or PMBus compatible serial interface options
Configurable through serial interface, Customizable through software
3V3 logic levels
Voltage set point control and Margining via Closed Loop Trim
Analog Input Monitoring
Programmed parameters saved in non-volatile memory
Intelligent configuration capability
Power-down data log for identifying fault conditions
Boot loader for in-system upgrading
GUI for defining board configuration parameters and board monitoring



Data Storage Servers
Networking
Telecommunications
This part is one in a family of the Bel Power System Controllers. Refer to Bel for additional controllers with different capabilities.
PART NUMBER
NUMBER OF PINS
NUMBER OF
TRIMMED RAILS
NUMBER OF
ADDITIONAL
MONITORED RAILS
NUMBER OF
POWER ZONES
TRKF-64D84SR
64
8
4
2
TRKF-64D84SR
2
Figure 1 provides a Functional Block Diagram of the Power System Controller.
Digital Inputs (from System CPU)
/2
/2
Enable (Zone A-B)
External Fault (Zone A-B)
Reset In
Mfg Mode
Margin High
Margin Low
Digital Outputs (to System CPU)
/2
Power Good (Zone A-B)
Reset Output A
Reset Output B
External Reference (+/-)
/2
Monitor Vin
Analog
Voltage
Monitoring
Monitor Analog Voltages (A-D)
/4
Digital I/O
Control
Monitor PoL Vout (1-8)
/8
Voltage Attenuation Resistors
(if required)
PMBus/I2C
Communications
Trim
PoL
PWM
Output
(with System CPU)
Clock
Data
PMBus /
I2C Engine
Main Engine
Active Trim
Control
Vin
/8
Trim
PWM Trim
Circuit
PoL Converters
1 of 8
Internal
Flash
(board
configuration
data,
fault log)
Power System
Controller
Vout
Enable PoL (1-8)
/8
Enable
GND
Sequence
Up/Down
Control
Enable Analog (A-D)
/4
PoL Input Power Enable (Zone A-B)
/2
Figure 1. Functional Block Diagram
A Configuration GUI is used to define the various board specific parameters (such as turn on and turn off input voltage thresholds,
output voltage set points and limits, digital I/O logic polarity, and sequencing requirements). See Section 2, Configurable Parameters
for a complete list. These parameters are sent to the part and saved in its non-volatile on-board flash memory during the board
development or manufacturing processes.
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While in operation, the controller manages the voltage rails as follows:
A. Sequence Up Operation
The controller performs the power up sequence when the monitored input voltage is greater than the configured turn-on
threshold and the enable input is asserted. It goes through each sequence step and enables the desired outputs and delays
for the desired amount of time. It then checks that the enabled outputs are within their configured power good limits. If they
are, it continues to the next sequence step. If not, it sequences down from this step back to the first.
After the sequence up operation completes, it then delays for the configured power good delay value and then asserts the
power good output signal.
B.
Active Trim
The part performs an active trim of the PoLs by comparing the measured PoL output voltages with the desired set points and
then adjusts the duty cycle of the trim PWMs. This provides for an accurate set point over time and temperature requiring only
one precision voltage reference for the entire power system. If margin testing is desired, the set points are set to the configured
margin high or low values and the output is trimmed to that value.
C.
Fault Detection
Upper and lower warning and power good limits are defined for each voltage and warning and power good masks are used to
indicate which rails cause warning conditions or power good faults. Fault logs containing the running time, voltages, and status
flags are stored in non-volatile memory for board diagnosis.
D.
Sequence Down Operation
The controller performs the power down sequence when the monitored input voltage is less than the configured turn-off
threshold, the enable input is de-asserted, or if there is a power good fault. It goes through each sequence step from last to
the first and disables the outputs.
This part supports dual zones which allows for two sets of PoLs to be independently enabled and monitored. The zone assignment
is configurable along with the standard board specific configurable parameters.
The two zones are sequenced up or down independent of each other. A fault on one zone does not cause the other zone to power
down.
Zone A
The PoLs included in the Zone A sequence mask are sequenced up if Enable Zone A is asserted AND the Zone A input monitor is
valid. They are sequenced down if Enable Zone A is de-asserted OR the Zone A input monitor is invalid. The Zone A PoLs are also
sequenced down if any of the monitored PoLs or Analog Input voltages in the Zone A power good mask are outside of the power
good limits. This will result in a latching fault that can be cleared by toggling the Enable Zone A input or issuing PMBus commands.
Zone A power up logic:
SIGNAL
STATE
LOGIC
Zone A Enable
Asserted
AND
Zone A input monitor
1
Valid (>Vin Start)
1
The actual analog input used for this monitor function is configurable.
After the enable delay, Input Power Enable Zone A is asserted. Next, the PoLs listed in the Zone A sequence masks are sequenced
up in the specified order with the specified delays. If the PoL voltages specified in the Zone A power good mask are within the power
good limits, the Power Good Zone A output is asserted after the specified power good delay.
Zone A power down logic:
SIGNAL
STATE
LOGIC
Zone A Enable
De-asserted
OR
Zone A input monitor1
Invalid (< Vin Off)
OR
Zone A Power Good Mask
any monitored voltage outside of power
good limits
Zone B
The PoLs included in the Zone B sequence mask are sequenced up if Enable Zone B is asserted AND Zone B input monitor is valid.
They are sequenced down if Enable Zone B is de-asserted OR Zone B input monitor is invalid. The Zone B PoLs are also sequenced
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down if any of the monitored PoL or Analog Input voltages in the Zone B power good mask are outside of the power good limits.
This will result in a latching fault that can be cleared by toggling the Enable Zone B input or issuing PMBus commands.
Zone B power up logic:
SIGNAL
STATE
LOGIC
Enable Zone B
Asserted
AND
Zone B input monitor
1
Valid (>Vin Start)
After the enable delay, Input Power Enable Zone B is asserted. Next, the PoLs listed in the Zone B sequence masks are sequenced
up in the specified order with the specified delays. If the PoL voltages specified in the Zone B power good mask are within the power
good limits, the Power Good Zone B output is asserted after the specified delay.
Zone B power down logic:
SIGNAL
STATE
LOGIC
Enable Zone B
De-asserted
OR
Invalid (< Vin Off)
OR
Zone B input monitor
1
any monitored voltage outside of power
good limits
Zone B Power Good Mask
Note that a sequence up operation for a zone will complete before starting the sequence up operation of the other zone if the
enabling condition of the other zone occurs while the first zone is still sequencing up. Zone A is sequenced up first if the enabling
conditions occur simultaneously.
The Bel Configurator is a PC-based graphical user interface application that is used to define the various board parameters. This
application is used to program the board settings into the part and may also be used interface with the part for board development
or diagnosis.
CATEGORY
Operating Settings
PoL and Analog Voltage
Monitor
Delay and Sequences
Power Good and Warning1
Reset Outputs2
Digital Inputs
Digital Outputs
Notes:
1.
2.
PARAMETERS
I2C slave address
ADC external reference voltage
Trim PWM frequency
Input voltage monitor attenuation resistor values
Zone input source
Turn-on voltage thresholds
Turn-off voltage thresholds
Input over voltage thresholds
Voltage monitor attenuation resistor values
Voltage set points
Margin percentages (low/high)
Warning limit percentages (low/high)
Power good limit percentages (low/high)
Default PWM duty cycle
PoL trim logic
Sequence enable masks (8 steps for each zone)
Sequence delays (9 values for each zone)
Power good mask (each zone)
Power good delay (each zone)
Warning mask (each zone)
Warning delay (each zone)
Reset A mask
Reset A delay
Reset B mask
Reset B delay
Input polarity (active high/low)
Output polarity (active high/low)
Output open drain option
The Warning indication is a flag only, there is no digital output signal.
The Reset Output signals are not defined by zone, but the masks may be defined so that the signals are controlled by rails
enabled by a particular zone.
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I/O TYPE
QUANTITY
Analog Input
13
SIGNALS
Digital Input
8
Monitor PoLs (8), Monitor Analogs (4), Monitor Vin
External Fault Inputs (2), Zone Enables (2), Mfg Mode, Margin High, Margin Low, Reset In
Digital Output
18
Enable PoLs (8), Enable Analogs (4), Input Power Enables (2), Power Good (2), Reset Outputs (2)
External Reference
2
VREF-, VREF+
I2C Communications1
2
I2C Data, I2C Clock
Power
10
VDD, VSS, AVDD, AVSS, VCAP/VDDCORE
Programming2
3
/MCLR, ICSP Data, ICSP Clock
PWM Trim
8
Trim PoLs (8)
Notes:
Notes:
1.
2.
PIN NO.
The I2C communication signals (I2C Clock, I2C Data, VDD, and VSS) must be brought to an interface header to initially load
the board specific configuration data and optionally communicate with the device during board development. These signals
may also be connected to a host microprocessor for system integration.
It is suggested that the /MCLR, VDD, VSS, ICSP Data, and ICSP Clock signals be brought to a programming header on the
board in case it becomes necessary to reprogram the part using an in-circuit serial programmer.
SIGNAL DESCRIPTION
I/O TYPE OR FUNCTION
1
Enable PoL 7
Digital Output
5V TOLERANT
N
2
Enable PoL 8
Digital Output
N
3
External Fault Zone A
Digital Input
N
4
Input Power Enable Zone A
Digital Output
Y
5
Margin Low
Digital Input
Y
6
Margin High
Digital Input
Y
7
/MCLR
Programming
Y
8
Enable Zone B
Digital Input
Y
9
VSS
Power
N
10
VDD
Power
N
11
Monitor PoL 4
Analog Input
N
12
Monitor PoL 3
Analog Input
N
13
Monitor PoL 2
Analog Input
N
14
Monitor PoL 1
Analog Input
N
15
VREF-
External Reference
N
16
VREF+
External Reference
N
17
Monitor PoL 5
Analog Input
N
18
Monitor PoL 6
Analog Input
N
19
AVDD
Power
N
20
AVSS
Power
N
21
Monitor PoL 7
Analog Input
N
22
Monitor PoL 8
Analog Input
N
23
Enable Zone A
Digital Input
N
24
Monitor Analog A
Analog Input
N
25
VSS
Power
N
26
VDD
Power
N
27
Monitor Analog B
Analog Input
N
28
Monitor Vin
Analog Input
N
29
Monitor Analog C
Analog Input
N
30
Monitor Analog D
Analog Input
N
31
Enable Analog D
Digital Output
Y
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PIN NO.
SIGNAL DESCRIPTION
I/O TYPE OR FUNCTION
32
External Fault Zone B
Digital Input
5V TOLERANT
Y
33
Enable Analog C
Digital Output
Y
34
Enable Analog B
Digital Output
Y
35
Reset Output B
Digital Output
Y
36
I2C Data
I2C Communication
Y
37
I2C Clock
I2C Communication
Y
38
VDD
Power
N
39
Power Good Zone A
Digital Output
N
40
Enable PoL 1
Digital Output
N
41
VSS
Power
N
42
Power Good Zone B
Digital Output
Y
43
Mfg Mode
Digital Input
Y
44
Reset Output A
Digital Output
Y
45
Reset In
Digital Input
Y
46
Trim PoL 1
PWM Trim
Y
47
ICSP Data
Programming
N
48
ICSP Clock
Programming
N
49
Trim PoL 2
PWM Trim
Y
50
Trim PoL 3
PWM Trim
Y
51
Trim PoL 4
PWM Trim
Y
52
Trim PoL 5
PWM Trim
Y
53
Trim PoL 6
PWM Trim
Y
54
Trim PoL 7
PWM Trim
Y
55
Trim PoL 8
PWM Trim
Y
56
VCAP/VDDCORE
Power
N
57
VDD
Power
N
58
Input Power Enable Zone B
Digital Output
Y
59
Enable Analog A
Digital Output
Y
60
Enable PoL 2
Digital Output
N
61
Enable PoL 3
Digital Output
N
62
Enable PoL 4
Digital Output
N
63
Enable PoL 5
Digital Output
N
64
Enable PoL 6
Digital Output
N
The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output
pins can be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors.
The maximum open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications.
SIGNAL
TYPE
AVDD
Power
AVSS
Power
Enable (Zone A, Zone B)
Digital Input
Enable Analog (A-D)
Digital Output
Enable PoLs (1-8)
Digital Output
External Fault (Zone A, Zone B)
Digital Input
DEFINITION
Positive supply (filtered VDD) for powering the ICs analog circuitry. See Section 6,
Powering the Controller.
Analog ground reference. See Section 6, Powering the Controller.
When asserted and if the input voltage is above the turn on threshold, the board is
sequenced up. When de-asserted, the board is sequenced down. This function can be
overridden as defined in the separate interface document.
Optional enable signals if Analog A-D are controlled converters, such as LDOs, VRMs, or
PoLs that do not require active trim or margining. Asserted during sequence up and deasserted during sequence down.
Enable signal for the PoL converters. Asserted during sequence up and de-asserted during
sequence down.
Optional input to induce a fault to the indicated zone. For example, this signal may be
used for indicating a thermal trip event. When asserted, the zone will fault off. If not used,
this pin must be pulled to ground and configured as active high.
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I2C Clock
I2C Communications
I2C Data
I2C Communications
Synchronous serial clock input/output for I2C communication. Since this is an I2C slave
device, the master drives the clock. Clock stretching may occur if necessary according to
the I2C specification.
Synchronous serial bi-directional data line for I2C communication.
ICSP Clock
Programming
Clock input pin for in-circuit serial programming.
ICSP Data
Programming
Input Power Enable (Zone A,
Zone B)
Digital Output
Margin High
Digital Input
Margin Low
Digital Input
/MCLR
Programming
Mfg Mode
Digital Input
Monitor Analog (A-D)
Analog Input
Monitor PoLs (1-8)
Analog Input
Monitor Vin
Analog Input
Power Good (Zones A, Zone B)
Digital Output
Reset Input
Digital Input
Reset Outputs (A, B)
Digital Output
Trim PoLs (1-8)
PWM Trim
VCAP/VDDCORE
Power
VDD
Power
VREF-
External Reference
Data I/O pin for in-circuit serial programming.
These signals are the enable signals for the optional power input circuit that is used to
power the PoL converters. Asserted during sequence up and de-asserted during sequence
down. If an OVP fault is detected (any monitored output voltage is greater than the power
good upper limit), the Input Power Enable output is de-asserted first at power down. If no
OVP fault occurs, the Input Power Enable output is de-asserted last at power down.
When asserted (and if the Mfg Mode input is also asserted), then the PoLs will be margined
to their configured high margin values.
When asserted (and if the Mfg Mode input is also asserted), then the PoLs will be margined
to their configured low margin values.
Master Clear (Reset) input. This pin is an active-low reset to the device. This signal must
be pulled-up to VDD with a 10k resistor.
Enable signal for the hardware margin signals. When asserted, the margin high/low inputs
will cause the PoLs to be margined to their configured high/low margin values.
Voltage monitor of Analog A-D inputs (must be scaled using attenuating resistors if voltage
exceeds reference voltage).
PoL output voltage monitor (must be scaled using attenuating resistors if voltage exceeds
reference voltage).
System input voltage monitor (must be scaled using attenuating resistors if voltage
exceeds reference voltage).
Asserted after the configured power good delay after all of the outputs have been
sequenced up and are operating within their configured power good limits. De-asserted
prior to sequencing down due to a fault or commanded to do so.
When asserted, causes Reset outputs to assert.
Asserted when Reset In is asserted. De-asserted when any outputs in configured reset
masks are outside of power good limits. Reset outputs can also be controlled by PMBus
commands.
PWM outputs for actively trimming the analog PoLs to their desired set points. See
Section 7, Using the PWM Trim Outputs.
Core decoupling capacitor. See Section 6, Powering the Controller.
Positive supply (3.3V) for peripheral logic and I/O pins. See Section 6, Powering the
Controller.
ADC voltage reference (low) input.
VREF+
External Reference
ADC voltage reference (high) input.
VSS
Power
Ground reference for logic and I/O pins. See Section 6, Powering the Controller.
Any unused digital inputs should be pulled to ground (VSS) with a 10k resistor.
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Figure 2. Power Interface
Figure 2 is a schematic of the typical 3.3V VDD interface to the Power System Controller IC using a Microchip LDO, P/N MCP1702T3302I/MB. This device is in a SOT89 package and in most applications will be sufficient in size to handle the power dissipation
when powering the circuit from a 12V source. Capacitor C7 (0.1uF ceramic) is one of the decoupling capacitors and should be
located directly across each pair of VDD and VSS pins on the IC. The part has a VCAP/VDD CORE pin which is used to decouple the
internally generated core voltage. Capacitor C8 is the decoupling capacitor for the core. This decoupling capacitor should be a low
ESR ceramic or tantalum capacitor with a value of 4.7 to 10uF. Capacitor C6 is the decoupling capacitor for the analog VDD (AVDD)
and it should be located directly across the AVDD and AVSS pins on the IC. Resistor R2 in combination with C6 provides a filter for
the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and
it should be connected directly across the LDO’s input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose
is to hold up the supply voltage to the LDO and maintain a stable VDD for the DSP for a short period after the +12Vin source is
removed. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1
during the inrush event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54 diode
is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible
to eliminate R1. Assuming a 40mA current draw, C1 will provide approximately 188us of hold up time per uF of capacitance.
The 3.0V reference IC provides an accurate external voltage reference for the analog-to-digital converter.
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The diagrams in Figure 3 show the three most common trim methods used in PoL converters. In all of these schemes a power
conversion stage contains a PWM device that receives a control voltage from an error amplifier. The error amplifier (E/A) compares a
scaled version of the output voltage to a reference. The output voltage of the converter module is simply the reciprocal of the scaling
factor multiplied by the reference value. The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying
the reference (Figures 3B and 3C).
+Sense
+Vin
Zf
Ry
TRIM
-
Zi
Rx
+Vout
Rz
PWM
E/A
+
Reference
Figure 3A
+Sense
+Vin
Zf
-
Zi
+Vout
PWM
E/A
+
TRIM
Rx
Ry
Reference
Figure 3B
+Sense
+Vin
Zf
-
Zi
+Vout
E/A
Reference
TRIM
PWM
+
uController
or Equivalent
Figure 3C
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The most common trim method is shown in Figure 3A. The popularity of this method stems from the fact that most highly integrated
PWM control IC’s have an internal reference that is not accessible and cannot be controlled externally. In this scheme the output is
scaled by adding a resistor from the trim pin to ground. This modifies the feedback divider and moves the output voltage to a higher
value. The output can also be modified by superimposing an offset voltage on the feedback divider by connecting a voltage source
to the trim pin through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher output voltage or a
larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in Figure 3B. With this method the feedback ratio is kept constant and
the reference value is modified to move the output voltage. The common characteristic of modules with this trim scheme is that a
lower value trim resistor to ground will cause a lower output voltage and a larger voltage superimposed on the trim pin will cause
Vout to increase.
The method shown in Figure 3C is occasionally used. This is similar to the method in Figure 3B except the modification of the
reference is mapped through a device such as a microcontroller. This is the least common of the three methods and requires the
vendor’s data sheet to determine the trim characteristic because the microcontroller can map the reference in many different ways.
The power controller has the ability to do independent closed loop trim and closed loop margining of the output voltage for each
PoL controlled by the device. Each PoL’s output voltage is monitored and by an analog to digital converter (ADC) in a continuous
loop. In firmware the most recent measured output voltage is compared against the desired value and the PoL’s output is
adjusted by delivering a trim value to the corresponding PoL’s trim pin. This trim voltage is created from a digital PWM output and
an external low pass filter. Each digital PWM is labeled <PoL “n” Trim> where n indicates a specific converter which corresponds
to the monitoring channel labeled with the same “n” value. The external low pass filter creates a DC value from the PWM signal
which is then delivered to each PoL converter through a range limiting resistor.
Figure 4 shows a typical circuit used to interface the controller’s trim PWM signals to PoL converters. In this circuit, Ra and Ca
construct a low pass filter while Rb is used to limit the trim range. The effective trim voltage is equal to the PWM duty cycle multiplied
by VDD (3.3V) and is controllable in 1024 steps from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are
chosen to reduce the trim voltage ripple. Typical values for Ra and Ca are 1k for Ra and 0.22uF to 1uF for Ca. Rb is used to limit
the control range and should be selected based on the desired control range and the trim equation for the PoL. This trim equation
is usually available from the PoL manufactures data sheet. The trim direction or logic is configurable for each PoL. The accuracy
of the active trim is a function of the ADC accuracy which is mostly controlled by the accuracy of the applied reference to the Vref
pins. The Trim PoL PWMs are set to the configured default values before power up begins so that the trim voltage is stable before
the PoLs are enabled.
Figure 4
The internal ADC channels are converted as 12-bit results with full scale equal to a chosen reference. The device is intended to be
powered from a 3V3 source and can be configured to use this source as the ADC reference or to use an externally provided
reference. Closed loop margining and set point adjustments always use the entire 12-bit result to trim the output voltages to
configured values. Monitored voltages are reported via I2C communication using PMBus data formats as defined in the separate
communication manual. The voltage range reported is determined by the entered set points. Any of the monitored voltages that
are greater than the ADC reference or that can be margined above this reference are required to have a voltage divider to limit the
maximum input to the corresponding ADC channel to a value less than or equal to the ADC reference. Monitored voltages below
the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the ADC results. In
most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value less than the
maximum value of the ADC reference.
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The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring signal, and
trim control signal. The enable signals are labeled <Enable PoL “n”>, the Monitoring signals are labeled <Monitor PoL “n”>, and
the trim signals are labeled <Trim PoL “n”>. Each n’th PoL converter is required to use the corresponding enable, monitor, and
trim signals. For example the first PoL converter attached to the controller is PoL 1. PoL 1 should use Enable PoL 1, Monitor PoL
1, and Trim PoL 1. The firmware assumes that the connections are made this way when controlling the system.
Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command set and is
defined in a separate communications manual. The communications manual also defines the protocol for device programming via
embedded boot loader software.
The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page mode as
described in the communications manual. The page assignment is defined in Figure 5.
Page 0
Not Used
Page 1
PoL1
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 2
PoL 2
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page3
PoL 3
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
I2C Address
(configurable)
Page 4
PoL 4
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
I2C Bus
Communication
Engine
Page
Control
Page 5
PoL 5
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 6
PoL 6
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 7
PoL 7
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page 8
PoL 8
Set Point
Scaling
Margin Limits
PGD/Warning Limits
Voltage Reads
Page_9
Analog A
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Page_10
Analog B
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Page_11
Analog C
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Page 12
Analog D
No Set Point Control
Scaling
PGD/Warning Limits
Voltage Reads
Figure 5. Page Assignment
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North America
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BCD.00842_AA
Asia-Pacific
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TRKF-64D84SR
12
PARAMETER
MIN
MAX
UNITS
Ambient temperature under bias
-40
TYP
85
°C
Storage temperature
-65
150
°C
Voltage on VDD with respect to VSS
-0.3
4.0
V
Voltage on any pin that is not 5V tolerant with respect to VSS
-0.3
VDD+0.3
V
Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V
-0.3
5.6
V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V
-0.3
3.6
V
Voltage on VDDCORE with respect to VSS
2.25
2.75
V
Maximum current out of VSS pin
300
mA
Maximum current into VDD pin
250
mA
4
mA
Maximum output current sunk by any I/O pin
Maximum output current sourced by any I/O pin
4
mA
Maximum current sunk by all ports
200
mA
Maximum current sourced by all ports
200
mA
PARAMETER
Input Voltage Range
SYMBOL
NOTES
VDD
Input Current
IDD
Logic Low Input Level
VIL
Logic High Input Level
VIH
MIN
TYP
MAX
UNITS
3.0
3.30
3.6
VDC
46
55
mA
0.2*VDD
VDC
Typical is at 3.3V, 25C, 20 MIPS.
Max is at 3.3V, 85C, 20 MIPS
VSS
Non 5V tolerant pins
VDD
0.7*VDD
VDC
5V tolerant pins
5.5
Logic Low Output Level
VOL
VDD = 3.3V
Logic High Output Level
VOH
VDD = 3.3V, IOH = -3.0mA
2.4
VDD Rise Rate
SVDD
0 to 3V in 100ms
0.03
Capacitance I/O Pin to GND
0.4
V/ms
50
CB
PWM Series Resistor
RPWM
Margin PWM Frequency
FPWM
Reference Input
VREF
AVSS + 1.7
EP
10,000
Flash Memory Cell Endurance
VDC
CIO
I2C Bus Capacitance
SCL and SDA
External Series Resistor
VDC
400
1
pF
pF
k
15
kHz
AVDD
VDC
E/W cycles
tech.support@psbel.com
TRKF-64D84SR
13
Figure 6. Bel 64-pin 10x10x1mm TQFP Controller
Number of Leads
Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
64-LEAD PLASTIC THIN-QUAD FLATPACK, 10 x 10 x 1 MM BODY
DIMENSION
MIN
NOM
N
64
e
0.50 BSC
A
A2
0.95
1.00
A1
0.05
L
0.45
0.60
L1
1.00 REF
0˚
3.5˚

E
12.00 BSC
D
12.00 BSC
E1
10.00 BSC
D1
10.00 BSC
c
0.09
b
0.17
0.22
11˚
12˚

11˚
12˚

MAX
1.20
1.05
0.15
0.75
7˚
0.20
0.27
13˚
13˚
Notes:
All dimensional units are in millimeters unless otherwise specified.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Champers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Europe, Middle East
+353 61 225 977
North America
+1 408 785 5200
© 2016 Bel Power Solutions & Protection
BCD.00842_AA
Asia-Pacific
+86 755 298 85888
TRKF-64D84SR
14
DATE
REVISION
2016-06-15
AA
CHANGE DETAIL
First release.
Refer to the errata document for additional information specific to each code release.
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on
the date manufactured. Specifications are subject to change without notice.
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