Physical Design of Digital Integrated Circuits
(EN0291 S40)
Sherief Reda
Division of Engineering, Brown University
Fall 2006
1
Lecture 04: Timing Analysis
•
•
•
•
Static timing analysis
STA for sequential circuits
Delay modeling: devices and interconnects
Statistical static timing analysis
2
Propagation delay definition
voltage
a
y
Logic block
Vmax
(10)%
50%
propagation delay
time
10% 90%
Definitions:
• rise/fall propagation delay
transition
time
• rise/fall transition delay (slew (slope): ΔV/transition delay)
3
Problem: Given a circuit, find the path(s)
with the largest delay (critical paths)
• Solution: run SPICE and report the results of the
simulation
• Problem: SPICE is computationally expensive to
run except for small-size circuits
• WANTED: We need a fast method that produces
relatively accurate timing results compared to
SPICE
4
Static timing analysis
simplified
analysis
C17 from ISCAS’85 benchmarks
I1
I2
I3
I4
I5
I6
1/2
2/4
1/2
1/2
2/3
2/4
3/5
1/2
1/2
O1 9/10
7/7
2/4
6/4
¾ All inputs are arrive at time 0
O2 9/11
critical
path
In reality, each input pin
has its own rise/fall delay
and wires have delays
¾ Assuming all interconnects have 0 delay
¾ Each gate has rise/fall delay
¾ slack = arrival time – required arrival time
⇒ paths with negative slacks need to be eliminated!
5
Finding the critical path through breadth first
search
I1
I2
2/1
I3
4/2
I4
I5
I6
•
•
•
•
3/2
3/2
O1
4/3
O2
1/1
2/2
Initialize queue Q to empty
for all vertices i in V: nvisit[i]=0;
Add all primary input vertices to queue Q
While (Q ≠ 0)
– i = top of Q; remove i from Q; computer delay of i
– for every edge (i, j):
• nvisit[j]++;
• if(nvisit[j] == fanin[j]) add j to Q
6
STA can lead to false critical paths
¾ STA assumes a signal would propagate from a gate input to its
output regardless of the values of other inputs
a
delay
=5
0
delay
=5
2×1
MUX
b
delay
=3
1
0
2×1
MUX
delay
=3
out
1
• What is critical path delay according to STA?
• Is this path realizable?
No, actual delay is less than estimated by STA
7
Lecture 04: Timing Analysis
•
•
•
•
Static timing analysis
STA for sequential circuits
Delay modeling: devices and interconnects
Statistical static timing analysis
8
Timing analysis of sequential circuits
[dmin .. dmax]
Δ
input
FF
clock
combinational
circuit
Δ
cycle time P
hold
time Th
output
FF
clock
setup
time Ts
9
Timing analysis of sequential circuits under
presence of clock skew
T=0
[dmin .. dmax]
Δ
input
FFi
combinational
circuit
Δ
output
cycle time P
si
FFj
sj
clock
clock
10
Sometimes introducing skew can be helpful
FFk
dmax
=8ns
FFi
dmax
=10ns
FFj
si
sj
¾ Zero clock skew (si =0 & sj = 0) ⇒ clock period = 10ns, fmax = 100MHz
¾ Si = -1 sj = 0 ⇒ clock period = 9ns, fmax = 111MHz (no timing violations)
¾ Si = -2 sj = 0 ⇒ clock period = 8ns, fmax = 125MHz (no timing violations)
¾ Introducing skew also helps minimize the simultaneous
switching of FFs → less load on the P/G network
¾ STA is relatively easy once we figure out how to
calculate gate and interconnect delay
11
Lecture 04: Timing Analysis
•
•
•
•
Static timing analysis
STA for sequential circuits
Delay modeling: devices and interconnects
Statistical static timing analysis
12
Elmore delay model: An upper bound to actual
delay in RC trees
any tree structure
R1
step
input
R2
R3
C1
C2
RN
C3
CN
¾ Sum the result of multiplying each resistance by the
capacitance down stream from it
¾ What is the runtime complexity?
[see Gupta/Pileggi’97 for more info]
13
Switch-level device RC delay models
NMOS model
PMOS model
[source: Weste/Harris]
14
Modeling the delay of an inverter
loading affects
gate delay
Holes have half the mobility of electrons
→ PMOS width = 2× of the NMOS device to get the same current
(or resistance) during output rise
→ equal rise and fall delays for CMOS inverter
15
Gate delay: rise delay
step
input
2
2
A
2
B
2x
R
6C
2C
Y
4hC
A
B
Y
h copies
rise propagation delay
Y
(6+4h)C
t pdr = ( 6 + 4h ) RC
Assumption: interconnect delay is ignored (for the moment)
16
Gate delay: fall delay
step
input
2
2
2
(1) A
2x
B
x
R/2
R/2
2C
6C
Y
4hC
A
B
Y
2C
Y
(6+4h)C
h copies
fall propagation delay
t pdf = ( 2C ) ( R2 ) + ⎡⎣( 6 + 4h ) C ⎤⎦ ( R2 + R2 )
= ( 7 + 4h ) RC
fall delay is worse than rise delay in this case
17
Gate delay is input pattern dependant
step
input
A
(1) B
2
2
2
2x
6C
2C
Y
4hC
A
B
Y
h copies
fall propagation delay
⇒ Connect the latest arriving signal closest to the output node
whenever feasible
18
Impact of transition time on gate delay
Input
gate
Output
Δ
time
τi
Δ’
time
In addition to capacitive load, input transition time affects
• delay: τi > 0 → Δ’ > Δ
• output transition time:
19
Why does transition time affect delay?
During transition, gate current < saturation current
→ higher effective output resistance → larger delay
∴ Input transition time affects gate delay (and output transition time too!)
stored in a lookup
table for fast
calculation
ti
τi
Gate
Δr/f(C, τi)
Ti+Δr/f
τo
total capacitance
(intrinsic + loading + interconnects)
20
Interconnect delay: the lumped case
Vm
Vout
0V
Upper bound on
delays in RC
trees [Pileggi’97]
21
Interconnect delay: lumped vs. distributed
R1
R2
R3
C1
C2
RN
C3
r = resistance per unit length
CN
c = capacitance per unit length
lumped
overestimates
delay
22
Carryout STA after annotating your circuit
with gate/interconnect delays
• Annotate your circuit with gate/interconnect delay, and
carry out STA
• Don’t ignore interconnect delay because it is currently
responsible for ~80% of total path delays!
23
Lecture 04: Timing Analysis
•
•
•
•
Static timing analysis
STA for sequential circuits
Delay modeling: devices and interconnects
Statistical static timing analysis
24
In Statistical STA (SSTA), delay is no longer
deterministic
I3
I4
I5
?
z
delay
delay
O1
pdf
I2
pdf
I1
pdf
x
y
delay
O2
I6
¾ Replace deterministic gate delay by a random delay variable that
has a normal pdf
¾ What is the pdf of z = max(x, y), where x and y are two random
normal variables?
¾ z is not normal, but can be approximated reasonable using
random variables [Jacobs/Berkelaar’00]
25
Gate variations impact critical path(s) delay
leading to an increase in the average delay
• Intra-chip (within-die) variations: arises within devices in the same die
• Inter-chip (die-to-die) variations: arises between different chips
26
Assignments for next lecture
Reading assignments:
•
•
•
Statistical Timing Analysis for Intra-Die Process Variations with
Spatial Correlations, ICCAD'03 (Kundan + (Yiwen) (judge))
Incremental timing analysis, US Patent 5508937 (Cesare)
Industrial products:
– Cadence SignalStorm (Elif)
– Synopsys PrimeTime (Brendan)
Projects overview:
• 10-15 mins presentation on previous work + proposal
• 1½ → 2 page report
27