2276
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 11, NOVEMBER 1998
Small-Scaled InGaP/GaAs HBT’s with
WSi/Ti Base Electrode and Buried SiO
Tohru Oka, Member, IEEE, Koji Hirata, Kiyoshi Ouchi, Hiroyuki Uchiyama,
Kazuhiro Mochizuki, and Tohru Nakamura, Senior Member, IEEE
Abstract—This paper describes the fabrication and characteristics of small-scaled InGaP/GaAs HBT’s with high-speed as well
as low-current operation. To reduce both the emitter size SE and
the base–collector capacitance CBC simultaneously, the HBT’s
are fabricated by using WSi/Ti as the base electrode and by
burying SiO2 in the extrinsic base–collector region under the base
electrode. WSi/Ti simplifies and facilitates processing to fabricate
a small base electrode, and makes it possible to reduce the width
of the base contact to less than 0.4 m without the large increase
in the base resistance. The DC current gain of 20 is obtained for
an HBT with SE of 0.3 2 1.6 m2 due to the suppression of
emitter size effect by using InGaP as the emitter material. An
HBT with SE of 0.6 2 4.6 m2 exhibited fT of 138 GHz and
fmax of 275 GHz at IC of 4 mA; and an HBT with SE of 0.3 2
1.6 m2 exhibited fT of 96 GHz and fmax of 197 GHz at IC of 1
mA. These results indicate the great potential of these HBT’s for
high-speed and low-power circuit applications.
Index Terms—Gallium materials, heterojunction bipolar transistors.
I. INTRODUCTION
G
aAs-BASED heterojunction bipolar transistors (HBT’s)
are more attractive for high-speed applications than
Si bipolar-junction transistors (BJT’s) due to their superior
carrier transport properties [1]. To date, GaAs-based HBT’s
over 100 GHz [2] and high
with high cutoff frequency
over 200 GHz [3], [4]
maximum oscillation frequency
have been reported. However, these HBT’s have considerably
large device dimensions compared to self-aligned and highspeed Si BJT’s [5]–[7]. This causes large power dissipation
and thermal-management problems when they are applied in
integrated circuits. On the other hand, small-scaled GaAsbased HBT’s whose emitter sizes were equal to or smaller
than 1 m have been reported [8]–[10]. However, their highfrequency characteristics were degraded in decreasing emitter
size. The main reason of this is the large base–collector capacitance resulting from the large base–collector junction area.
To achieve high-speed and low-power operation in HBT’s,
therefore, it is essential to reduce both the emitter size and the
parasitic capacitance simultaneously.
The conventional method to reduce the parasitic capacitance
of the base–collector junction is proton- or oxygen-ion implantation into the region under the extrinsic base [11], [12].
Manuscript received March 17, 1998; revised June 15, 1998. The review
of this paper was arranged by Editor M. F. Chang.
T. Oka, K. Ouchi, H. Uchiyama, K. Mochizuki, and T. Nakamura are with
the Central Research Laboratory, Hitachi, Ltd., Tokyo 185-8601, Japan.
K. Hirata is with Hitachi ULSI Systems Coompany, Tokyo 185-8601, Japan.
Publisher Item Identifier S 0018-9383(98)07993-3.
Fig. 1. Schematic cross section of the HBT with a WSi/Ti base electrode
and buried SiO2 :
This compensates the relatively low doping of the collector
and thus fully depletes the extrinsic collector. However, the
dielectric constant of the implanted regions are still as large as
that of GaAs, and this limits the reduction of the parasitic
capacitance. Ion implantation also induces the increase of
the base resistance [13], which also degrades high-frequency
characteristics.
In this paper, we describe high-performance InGaP/GaAs
HBT’s capable of high-speed as well as low-current operation.
In the HBT’s, simultaneous reduction of emitter area and
base–collector capacitance were achieved by using WSi/Ti
as the base electrode and by burying SiO in the extrinsic base–collector region under the base electrode. Excellent
high-frequency characteristics at low collector currents are
demonstrated in small-scaled HBT’s.
II. DEVICE STRUCTURE
The schematic cross section of the device structure is
illustrated in Fig. 1. The structure has two main features. First,
the width of the base contact is reduced to 0.3 m by using
a self-aligning process, and the extrinsic base–collector region
is buried by SiO The buried SiO reduces the parasitic
capacitance under the base electrode because the dielectric
constant of SiO is about 1/3 of that of GaAs [14]. Narrowing
the width of the base contact decreases the base–collector
junction area and thus reduces the base–collector capacitance.
Second, WSi/Ti is used as the base electrode. These materials
have definite advantages over the conventional gold-based
electrode metals. Both WSi and Ti can be deposited by a
sputtering method with good step coverage and selectively
patterned on GaAs and SiO by using reactive ion etching
(RIE). This simplifies and facilitates processing to fabricate
a small base electrode. In addition, a thin Ti film inserted
between WSi and p-type GaAs effectively reduces the contact
0018–9383/98$10.00  1998 IEEE
OKA et al.: SMALL-SCALED InGaP/GaAs HBT’S
2277
Fig. 3. Calculated results of the product of base resistance RB and
base–collector capacitance CBC as a function of base–contact width WBC :
B. Optimization of Contact Width
Fig. 2. Specific contact resistance for WSi and WSi/Ti as a function of
carrier concentration in p-GaAs layers.
resistance compared to using WSi only. This suppresses the
large increase in the base resistance that occurs when reducing
the width of the base contact, and therefore, makes it possible
to achieve much higher frequency performance than in our
earlier work [15].
III. CHARACTERISTICS AND OPTIMIZATION OF BASE CONTACT
In advance of the device fabrication, we investigated the
influence of Ti insertion on the contact resistance for the base.
We also estimated the optimum width of the base contact for
and high
designing HBT’s with both high cutoff frequency
maximum oscillation frequency
A. Influence of Ti Insertion
between
We evaluated the specific contact resistance
GaAs and the ohmic metals of WSi or WSi/Ti by using transmission line model (TLM) measurement [16], [17]. WSi(300
nm)/Ti(5 nm) or WSi(300 nm) films were deposited by sputtering method on 30-nm-thick p-GaAs actual HBT base layers.
These were not alloyed after deposition. The composition ratio
of WSi was 0.3 and the sheet resistance of the 300-nm-thick
WSi was about 7
The specific contact resistance
as a function of the base
carrier concentration is shown in Fig. 2. The dashed lines are
the calculated theoretical curves based on a tunneling model
[18]. These calculations were carried out for various potential
assuming that the effective tunneling hole
barrier heights
where
is the free electron mass. The
of
mass is
of 0.8 eV at lower carrier
WSi fits the theoretical curve for
concentration and it deviates as the carrier concentration
of WSi/Ti, in contrast, agrees well with the
increases. The
of 0.6 eV at any carrier concentration. The value
curve for
is about one order of magnitude lower than that of WSi. At
10 cm
for example,
a carrier concentration of 1
was reduced from 2
10
cm to 3
10
cm .
This result indicates that an inserted thin Ti film effectively
decreases the potential barrier height and thus dramatically
reduces the contact resistance.
decreases
Narrowing the width of the base contact
and thus increases both
the base–collector capacitance
and maximum oscillation frequency
cutoff frequency
However, it simultaneously increases base resistance
which degrades
This means that
has an optimum
and
Thus, we estimated
value for both high
dependence of the product of
and
In this estimation,
the dependence was calculated by assuming that the device
structure was the same as described in the next section.
Fig. 3 shows the calculated results for the device with
of 0.5
5 m and a base doping
an emitter size
The product of
and
concentration of 1 10 cm
for the WSi base electrode reaches its minimum at
of
is below 0.4 m.
0.55 m and rapidly increases when
On the other hand, the product for the WSi/Ti electrode is
about 1/2 to 1/3 smaller than that for WSi and the remarkable
is less than 0.4 m.
increase is not shown even when
of 0.25 m. The
The product shows the minimum at
of WSi/Ti and suggests
result is due to the extremely low
can be reduced to less than 0.4 m without the large
that
increase in the base resistance. Although the optimum value
is slightly changed by the emitter size, the highest
of
and
for the HBT would be obtained by reducing
to
around 0.2–0.3 m when using WSi/Ti as the base electrode.
IV. DEVICE FABRICATION
The epitaxial layers of the HBT’s were grown on a semiinsulating GaAs(100) substrate by gas-source molecular beam
epitaxy (MBE) [19]. The group III sources were elemental Ga
and In, and the group V sources were cracked arsine (AsH )
and phosphine (PH ). The n- and p-type dopant sources were
solid Si and carbontertabromide (CBr ), respectively.
The parameters of the epitaxial layer structure are listed
in Table I. The emitter-cap layers consist of highly doped cm ), -GaAs (100 nm,
InGaAs (50 nm,
cm ), and n-InGaP (50 nm,
cm ) to reduce emitter resistance. The emitter layer is 10010 cm
The p-GaAs base layer
nm InGaP doped to 5
10 cm
to reduce the contact
is highly doped to 1.3
resistance with the WSi/Ti base electrode, and the thickness
is 30 nm to obtain appropriate current gain at the high base
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 11, NOVEMBER 1998
(a)
(d)
(b)
(e)
(c)
(f)
Fig. 4. Fabrication steps for the HBT with a WSi/Ti base electrode and buried SiO2 :
TABLE I
EPITAXIAL LAYER STRUCTURE PARAMETERS OF FABRICATED HBT’S
doping level. The -GaAs collector layer is 200 nm thick and
10 cm
The relatively thick subcollector
doped to 2
layer was used in order to bury the thick SiO in the extrinsic
collector. The -GaAs subcollector layer is 800 nm thick and
10 cm
doped to 8
The main steps in the fabrication process are schematically
shown in Fig. 4. Device fabrication starts with W/WSi deposition on the InGaAs emitter-cap layer by RF sputtering. These
metals are formed into a nonalloyed emitter electrode by RIE
using CHF and SF By using this electrode as a mask, the
InGaAs and GaAs layers are etched by using Cl /CH electron
cyclotron resonance (ECR) plasma [Fig. 4(a)].
This is followed by a thick SiO sidewall formation around
the emitter electrode. By using this sidewall as a masking
layer, the self-aligned base and collector mesas are formed by
ECR plasma etching. After F ions are implanted to isolate
each device, the outsides of the base and collector mesas are
buried by SiO by using planarization and an etchback process
[Fig. 4(b)].
The InGaP layers are etched by the ECR plasma, leaving
at least 50 nm unetched so that the plasma does not damage
the base surface. The remaining InGaP layer is removed by
selective wet-chemical etching using a solution of dilute HCl.
During this etching, the side of the emitter layer is hardly
etched due to the orientation dependence of the etching rate. A
thin sidewall of SiO is then formed to avoid a short between
the emitter and the base [Fig. 4(c)]. According to the result
discussed in the previous section, the proper width of the base
contact is 0.3 m. Thus, the thickness of this sidewall was
chosen as 0.1 m and the thickness of the sidewall for the
base and collector mesa-etching was chosen as 0.4 m.
WSi/Ti is deposited by RF sputtering and etched
by RIE to define the base electrode [Fig. 4(d)]. Then,
AuGe/W/Ni/Au/Mo is deposited on the subcollector as a
collector electrode, and alloyed. Subsequently, the WSi on
the emitter electrode is selectively etched by RIE with CF
by using a photoresist mask, and the Ti on the emitter
electrode is removed by dilute HF [Fig. 4(e)]. Finally, a
metallization process follows and the device structure is
completed [Fig. 4(f)].
A cross-sectional SEM photograph of the fabricated HBT
with a WSi/Ti base electrode and a buried SiO structure is
shown in Fig. 5. The base–contact width is 0.3 m and the
OKA et al.: SMALL-SCALED InGaP/GaAs HBT’S
Fig. 5. SEM cross section of the fabricated HBT with a WSi/Ti base
electrode and buried SiO2 :
Fig. 6. Common-emitter IC
with emitter size SE of 0.3
0 VCE characteristics for the fabricated HBT
2 1.6 m2 .
sidewall thickness is 0.1 m. The final thickness of the buried
SiO is about 0.4 m. The WSi/Ti base electrode covers both
the narrow base–contact surface and the buried SiO outside
the base–collector junction. This indicates that WSi and Ti are
useful materials in fabricating small base electrodes for our
HBT’s.
V. DEVICE PERFORMANCE
A. DC Characteristics
We evaluated dc characteristics of the fabricated HBT’s with
various emitter sizes by using an HP4145B semiconductor
parameter analyzer.
characteristics for an HBT
The common-emitter
of 0.3
1.6 m are shown in
with an emitter size
Fig. 6. The offset voltage is about 0.25 V and the collectoris 10–11 V. Fig. 7 shows
emitter breakdown voltage
of 0.3
1.6 m . The
a Gummel plot for an HBT with
of 20 is achieved at a collector current
DC current gain
10 A/cm and decreases for current density
density of 1
10 A/cm due to the base push-out effect at
above 2
high current. The ideality factors of the collector and the base
currents are 1.0 and 1.6, respectively.
In AlGaAs/GaAs HBT’s, the current gain is decreased when
scaling down the emitter size, which is known as the emitter
size effect on current gain [20]. We investigate the emitter
2279
Fig. 7. Gummel plot for the fabricated HBT with emitter size
1.6 m2 .
2
SE
of 0.3
Fig. 8. Dependence of 1=hFE on LE =SE for fabricated HBT’s with
various emitter sizes at collector current density JC of 5
104 A/cm2 :
2
size effect in our InGaP/GaAs HBT’s. The current gain
and the emitter size
have the relationship approximately
expressed as [21]
(1)
where
intrinsic bulk current gain;
base current density due to surface recombination;
collector current density;
length of the emitter periphery.
on
for the fabFig. 8 shows the dependence of
ricated HBT’s at a collector current density of 5 10 A/cm
The current gain is slightly decreased when the emitter size is
scaled down. From the slope of the line in Fig. 8, the peripheral
component of the base current was estimated to be
A/ m. Although our HBT’s do not have a thin emitter layer on
the extrinsic base regions for surface passivation, the leakage
current is comparable to that of AlGaAs/GaAs HBT’s with
an AlGaAs surface passivation layer [9]. This suggests that
the low surface recombination velocity of InGaP effectively
suppresses the degradation of the current gain. The relatively
large ideality factor of the base current is, therefore, primarily
attributed to the recombination in the intrinsic base region
caused by the high doping concentration of the base layer.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 11, NOVEMBER 1998
j j
Fig. 9. Frequency dependence of small-signal current gain h21 2 ; unilateral
power gain UG; and maximum stable gain MSG for the fabricated HBT with
SE of 0.6 4.6 m2 at VCE = 1:6 V and IC = 4 mA. The dashed lines
are extrapolations of h21 2 and UG with a 20 dB/decade slope.
2
j j
(a)
0
B. Microwave Characteristics
We investigated the high-frequency characteristics of the
fabricated HBT’s by using on-wafer -parameter measurements with an HP85107A network analyzer system and cascade microwave probes. The measurements were carried out in
the frequency range of 100 MHz to 40 GHz. The pad parasitics
were de-embedded using the method presented by Costa et al.
[22].
Fig. 9 shows the frequency dependence of the small-signal
unilateral power gain
and maximum
current gain
of 0.6
stable gain MSG for an HBT with an emitter size
4.6 m . The collector-emitter bias voltage
was 1.6
was 4 mA. The
and
V and the collector current
as estimated with 20 dB/decade extrapolations from
and
were 138 and 275 GHz, respectively. These are the
highest values ever reported for a GaAs-based HBT operating
at such a low collector current.
and
Fig. 10 shows the collector current dependence of
for the fabricated HBT with
of 0.6
4.6 m at
of 1.6 V. The HBT exhibits the peak
of 138 GHz
of 275 GHz at the same
of 4 mA.
and the peak
The figure also shows the results for our conventional HBT
m without using buried SiO [23]. The
and
for
fabricated HBT operates at much higher
lower collector currents than the conventional HBT. This
much more than
performance was achieved by reducing
Several characteristics of the fabricated HBT and the
of
conventional HBT are summarized in Table II. The
the fabricated HBT was reduced to 7.6 fF, which is about
of
one-third of that of the conventional HBT, while the
the fabricated HBT is about 2/3 of that of the conventional
by
HBT. In Fig. 10, it is also shown that the increase of
implementing the buried SiO structure is less than that of
This is ascribed to the increase of the parasitic resistance
and
resulting from the reduction of the device size,
which increases the parasitic delay time and thus interferes
the increase of
Fig. 11 shows the collector current dependence of
and
for the HBT with
of 0.3
1.6 m at
of
1.6 V. The high frequency performance is degraded compared
to the larger device because the capacitance is not reduced in
proportion to the device size due to the fringe capacitance.
(b)
Fig. 10. Collector current dependence of (a) fT and (b) fmax for the
fabricated HBT with SE of 0.6
4.6 m2 and our conventional HBT
(SE = 1:2
3:4 m2 ) without using buried SiO2 [23] at VCE of 1.6 V.
2
2
TABLE II
DEVICE PARAMETERS OF THE FABRICATED HBT
AND THE
CONVENTIONAL HBT
However, a peak
of 96 GHz and a peak
of 197 GHz
of 1 mA. Furthermore, the device operates
are achieved at
as high as 40 GHz and
as high as 100 GHz at
with
as low as 0.1 mA. To our knowledge, these values are the
highest of previously reported GaAs-based HBT’s operating
at submilliampere collector currents.
In Fig. 11, our results are compared with the results for a Si
of 0.2 2.0 m which exhibited high-frequency
BJT with
operation at a low collector current [24]. At any range of
and the
for the fabricated small
collector currents, the
HBT are higher than those for the Si BJT. This excellent highfrequency performance for low corrector currents is due to the
simultaneous reduction of the emitter size and base–collector
capacitance. This result indicates that our HBT’s will enable
OKA et al.: SMALL-SCALED InGaP/GaAs HBT’S
2281
ACKNOWLEDGMENT
The authors would like to thank Dr. Y. Imamura and his
process staff for their contribution to the device fabrication.
They also wish to thank Dr. O. Kanehisa for his encouragement and support throughout this work.
REFERENCES
(a)
(b)
Fig. 11. Collector current dependence of (a) fT and (b) fmax for the
fabricated HBT with SE of 0.3 1.6 m2 at VCE of 1.6 V. Also shown are
results for a Si BJT with SE of 0.2
2.0 m2 [24].
2
2
the fabrication of integrated circuits with higher speed and
lower power than Si BJT’s.
VI. CONCLUSION
We have demonstrated high-speed and low-current operation
of small-scaled InGaP/GaAs HBT’s. The simultaneous reduction of the emitter size and the base–collector capacitance were
achieved in the HBT’s by using WSi/Ti as the base electrode
and by burying SiO in the extrinsic base–collector region
under the base electrode. Inserting a thin Ti film between WSi
and p-type GaAs dramatically reduced the contact resistance to
cm at a carrier concentration of 1 10 cm
3 10
and made it possible to reduce the width of the base contact
to less than 0.4 m without the large increase in the base
resistance. The dc current gain of 20 is achieved for an HBT
of 0.3 1.6 m . The emitter size effect on current
with
gain was suppressed by using InGaP as the emitter material.
The base leakage current for the fabricated HBT’s without
a thin emitter layer for surface passivation was comparable
to that of AlGaAs/GaAs HBT’s with an AlGaAs surface
passivation layer. Excellent high-frequency characteristics at
low collector currents were achieved: an HBT with an emitter
of 0.6 4.6 m provided
of 138 GHz and
size
of 275 GHz at
of 4 mA; and an HBT with
of 0.3
1.6 m provided
of 96 GHz and
of 197 GHz at
of 1 mA. These HBT’s will enable us to fabricate integrated
circuits with higher speed and lower power than currently
possible with Si BJT’s.
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Tohru Oka (M’98), for a photograph and biography, see this issue, p. 2275.
Koji Hirata, for a photograph and biography, see this issue, p. 2274.
Kiyoshi Ouchi, for a photograph and biography, see this issue, p. 2274.
Hiroyuki Uchiyama was born in Chiba, Japan, in
1962. He received the B.S. and M.S. degrees in
chemistry from Chiba University in 1987 and 1989,
respectively.
In 1989, he joined the Central Research Laboratory, Hitachi Ltd., Tokyo, Japan, where he has
been engaged in the research and development of
dry etching processes for III–V compound semiconductor devices. Since 1996, he has been working on
the development of MMIC’s operating at 77GHz.
Mr. Uchiyama is a member of the Japan Society
of Applied Physics.
Kazuhiro Mochizuki, for a photograph and biography, see this issue, p. 2274.
Tohru Nakamura (M’79–SM’90) received the
M.S. and Ph.D. degrees in electrical engineering
from Waseda University, Tokyo, Japan, in 1971 and
1979, respectively.
In 1975, he joined the Central Research
Laboratory, Hitachi Ltd., Tokyo. He has worked
in the areas of integrated injection logic circuits,
self-aligned bipolar device technologies and high
speed silicon bipolar integrated circuit technology.
His key emphasis was directed to development on
new self-aligned bipolar device, SICOS (sidewall
base contact structure), technologies and their application for high speed
bipolar memory LSI’s. He has also worked in the area of high speed HEMT’s
and HBT’s for telecommunication and mobile communication use, as a
Chief Researcher in the Central Research Laboratory, Hitachi Ltd., Tokyo.
During 1992–1993, he was a Visiting Professor at University of California,
San Diego, where he taught a course on the high speed bipolar device
and circuit technologies. He has authored or co-authored over 100 research
papers on Si bipolar and compound semiconductor devices, circuits, process
and technologies. He has been working at Department of Electronics and
Electrical Engineering, Hosei University, Koganei, Tokyo, since 1998.
Dr. Nakamura served as a IEDM subcommittee member of IC from 1989
to 1991. He has also been serving as a BCTM subcommittee member of
process/technology since 1994 and an editor for the IEEE TRANSACTIONS ON
ELECTRON DEVICES since 1993. He is a member of the Institute of Electronics,
Information and Communication Engineers of Japan and the Japan Society
of Applied Physics.