Applying Power MOSFETs in an
Unclamped Inductive Switching
Environment
Understanding the Importance of
Unclamped Inductive Switching
• The vast number of loads driven today are inductive in nature such as
solenoids, transformers, inductors, etc.
• Power MOSFET failure due to Unclamped Inductive Switching conditions is one
of the most prevalent failure modes encountered
• Proper MOSFET specification and proper application of the MOSFET within the
circuit is one of the easiest ways a designer can improve the reliability of their
power MOSFET components
• This tutorial will discuss the UIS failure mechanism and explore how a designer
can properly specify a MOSFET component to avoid UIS failures
2
1
Terminology and Definitions
• “Avalanche” – A condition when the drain-source voltage exceeds the bulk
break down of the Power MOSFET
• “Ruggedness” – A term that signifies that a Power MOSFET has the ability to
withstand energy dissipation in the breakdown mode of operation
• “UIS” – Unclamped Inductive Switching; A context sensitive term used to
describe a Power MOSFET’s ability to sustain energy in the avalanche mode of
operation or it can be used to describe a circuit which is driving an inductive load
without a drain clamp
3
Terminology and Definitions
• “IAS” – Current (I) Avalanche Single Pulse; The magnitude of IDS that a part can
sustain in the avalanche mode for a single non-repetitive pulse
• “EAS” – Energy Avalanche Single Pulse; the level of energy that a part can
dissipate in the avalanche mode for a single non-repetitive pulse
• “tAV” – Time in Avalanche; A term used in specifying UIS capability that signifies
the amount of time that the device is in the avalanche mode of operation
4
2
Terminology and Definitions
• “EAR” – Energy Avalanche Repetitive Pulse; same as a single pulse but for a
repetitive pulse sequence
• “IAR” – Current (I) Avalanche Repetitive Pulse; same as a single pulse but for a
repetitive pulse sequence
VBR ≅ (1.3 * BVDSS)
BVDSS
EAR
VDD
IAR
tAV
5
Power MOSFET Structure
SOURCE
GATE
N+
RBE2
N+
P+
2 μm
RBE1
CCB
2 μm
N-
N+
288 μm
N+
DRAIN
Power MOSFET Chip Structure
Power MOSFET Structure
With Parasitic Transistor
6
3
The Parasitic Bipolar Transistor
D
IC (IDS)
Body-Drain
PN Junction
CCB
VCEO
VCBO (BVDSS)
RBE1
G
Decreasing RBE
VCER
RBE2
VCEO(SUS)
S
VCE (VDS)
Breakdown Characteristics of the
Parasitic Bipolar Transistor
Schematic of the MOSFET with
the Parasitic Bipolar Transistor
7
UIS Test Circuit and Idealized
Waveforms
L
Current Measuring
Transformer
E = 10% BVDSS
UIS Test Circuit
DC
RGS
Single Pulse
VDS / IDS
VBR ≅ (1.3 * BVDSS)
W = ½ * I DS(PEAK) 2 * (1.3 * BVDSS/(1.3 * BVDSS-E))
BVDSS
tAV = L * IDS(PEAK) / (1.3 * BVDSS-E)
Idealized UIS Test
Waveforms
t = L * IDS(PEAK) / E
IDS(PEAK)
E (VDS)
VGS
t
tAV
8
4
UIS Testing – Actual Waveforms
A few points of observation
1. The observed BVDSS is higher then the
datasheet rated value
2. At low avalanche currents the BVDSS is
nearly flat indicating a low temperature rise
3. At higher avalanche currents the BVDSS
rises to higher levels due to the effects of
the bulk resistance and the increase in the
PN junction bulk breakdown caused by the
Typical IDS & VDS UIS waveforms
10us/div., 10V/div., 10A/div.
Curve I1 IDS(PK)=14A
Curve I2 IDS(PK)=42A
Curve I3 IDS(PK)=48A
substantial increase in the junction
temperature
4. Failure of the device occurs roughly at 1/3
to 1/2 of the expected tAV
9
Actual Measured HUFA76645P3 UIS
Capability
o
S t a r t in g T J = 2 5 C
o
S t a r t in g T J = 1 0 0 C
S t a r t in g T J = 1 7 5 o C
S ta r tin g T J = 2 0 0 o C
10
S t a r t in g T J = 2 2 5 o C
AS
I , Avalanche Current - Amps
100
1
0 .0 1
0 .1
T
AV
1
10
, T im e in A v a la n c h e - m s e c
This graph is meant to depict the device capability and the failure due to IAS as a consequence of different starting junction temperatures.
The user must adhere to design principles that ensures the maximum operating junction temperature is kept within the data sheet limits.
10
5
UIS Capability vs Starting Junction
Temperature for the HUFA76645P3
Across Varying Values of Inductance
140
Ias, Avalanche Current - Amps
120
100
80
Intrinsic Temperature
TJ(FAILURE)
60
40
20
0
0
100
200
300
T J , In itia l J u n c tio n T e m p e r a tu re - o C
This graph is meant to depict the device capability and the failure due to IAS as a consequence of different starting junction temperatures.
The user must adhere to design principles that ensures the maximum operating junction temperature is kept within the data sheet limits.
11
Intrinsic carrier concentration for
Si as a function of (T)
ni = 3.88E16(T1.5)exp(-7000/T) cm-3 (T is in Kelvin)
From experimental data on the HUFA76645P3 a 100V 75A MOSFET Fails when
the Tj = 320oC = 593oK
From the above equation ni(593(K))=4.19E15 cm-3@ T=593K
Examples of some doping concentrations for some different MOSFET
designed for different breakdown voltages. Nd
30V~2.7E16 cm-3
75V~6.5E15 cm-3
100V~4E15 cm-3
150V~2.2E15 cm-3
When ni = Nd the intrinsic temperature is reached. Blocking capability is
compromised and you get high leakage caused by thermally generated
carriers. If an electric field in present the this causes “Hot electrons” to smash
into lattice atoms. This causes a higher lattice temperature which in turn
causes more thermally generated carriers. This is “second break down”.
12
6
Only one relationship is true
KENERGY=LI2 or KUIS=tAV*I2
Failure Loci for 25 HUF76645P3 MOSFETs at 25oC
The graph shows
that
KENERGY=LI2 Is not
true and that
KUIS=tAV*I2 is.
1000
Slope ~-1/3
I Fail
(A)
25C
100
Slope ~-1/2
IAS
10
I Fail
(A)
25C
1
0.1
0.01
0.1
1
L in mH,
10
100
tav in ms
13
Observations on the UIS Capability
Tests Results
• When the starting junction temperature exceeds the rated TJ(MAX) a
significant avalanche current capability exists
That is IAS α TJ(FAILURE) – TJ(START)
• The avalanche capability as a function of L shows the following
relationship: IAS3.2 α 1/L
This result does not agree with the concept of constant
energy which would have the relationship - IAS2 α 1/L
• The results obtained on Power MOSFETs, once the parasitic bipolar
turn-on mechanism is suppressed, are similar to those obtained on
rectifiers
That is the Power MOSFET capability is the capability of a single
PN junction device, that is the drain body PN diode
14
7
Fairchild Standard UIS Rating Curve
H U F A 7 5 3 4 4 P 3 _ S 3 U IS C a p a b ility
400
IAS, Avalanche Current (A)
200
4000
3000
2000
100
1000
90
80
900
800
70
700
60
600
50
500
40
400
30
300
20
200
S ta rtin g T J = 1 5 0 o C
10
0 .0 1
0 .1 0
EAS, Avalanche Energy (mj)
300
If R = 0
t A V = (L *I A S )/(1 .3 *R a te d B V D S S -V D D )
If R > 0
t A V = (L /R )ln [(I A S *R )/(1 .3 *R a te d B V D S S -V D D )+ 1 ]
S ta rtin g T J = 2 5 o C
100
1 0 .0 0
1 .0 0
t A V , T im e in A v a la n c h e (m s e c )
H U F A 7 5 3 4 4 P 3 _ S 3 _ Ia s -ta v .jn b
15
The UIS Rating Graph
The UIS Rating Graph shows:
1.IAS α 1/tAV1/2
2.Two starting junction temperature ratings are given. Ratings at other TJ(START) levels
can be calculated using a linear curve fit
The rating curve as published is guard banded from the measured capability
Criteria to Safe Use
If the circuit’s peak load current and tAV is plotted on the graph and it is below and
to the left of the appropriate TJ(START) line the part is being used within its rating
The tAV equations are given to assist the circuit designer in determining the tAV from
known circuit and device information. The equations use the effective device
breakdown voltage during the avalanche condition and is listed as 1.3 x Rated BVDSS
16
8
Calculating TJ(AVG)
TJ(AVG) = TA + PD * RΘJ-A
RΘJ-A = RΘJ-C + RΘC-S + RΘS-A
Where
TA is the highest operating ambient temperature expected
RΘJ-A = The junction-to-ambient thermal resistance
RΘJ-C = The junction-to-case thermal resistance
RΘC-S = The case-to-sink thermal resistance
RΘS-A = The sink-to-ambient thermal resistance
PD = PCOND + PAV
Where
PCOND= on-state conduction losses taking into account the worst case RDS(ON) and its
value at TJ(AVG)
PAV is the avalanche losses and is equal to EAS * frequency
If the avalanche energy cannot be obtained from direct observation, the EAS can be
estimated by the following equation: EAS = ½ * 1.3 * Rated BVDSS * IAS * tAV
17
Single Pulse UIS Design Example
Problem:
A circuit contains a HUFA75344P3 MOSFET which drives a solenoid (inductive
load) load of 1.7mh with a dc resistance of 2.1Ω from a supply voltage of 24V. A
gate signal of VGS = 10V is applied to the MOSFET gate and the solenoid is
energized for the first time. After some considerable time (greater than 5 L/R time
constants). The gate voltage is returned to zero volts, VGS = 0V
The system uses as heat sink and interface material described as follows:
Heat sink data and interface material from Aavid Thermalloy:
Heat sink part number 6109PBG
o
RΘJ-A = 17.0 C / W
Interface isolation material In-Sil-8:
Isolation material part number 1898
o
RΘC-S = 1.25 C / W
18
Determine if the HUFA75344P3 avalanche energy rating is exceeded and
determine if this device can be used reliably in the application. Calculate the
energy absorbed during the avalanche pulse
9
Single Pulse UIS Design Example
(con’t)
Step 1
Calculate TJ(START)
TJ or TJ(START) = TA + (PD x RΘJ-A)
RΘJ-A = RΘJ-C + RΘC-S + RΘS-A
Given in the problem:
TA = 80oC
RL = 2.1Ω
L = 1.7mh
VDD = 24V
o
TJ(MAX) = 175 C
Rated BVDSS = 55V
(HUFA75344P3 data sheet)
RθJ-C = 0.52oC / W (HUFA75344P3 data sheet)
RθC-S = 1.25oC /W (Aavidthermalloy data sheet)
RθS-A = 17.0oC / W (Aavidthermalloy data sheet)
rDS(on) @ 25oC = 0.008Ω (HUFA75344P3 data
sheet)
rDS(on) @ 80oC = 0.008Ω * 1.25 [est HUFA75344P3
data sheet] = 0.010Ω (Actually the rDS(on)
temperature multiplier is a function of TJ, but we
will use TA for our first iteration)
19
Single Pulse UIS Design Example
(con’t)
Calculating RΘJ-A:
o
o
o
o
RΘJ-A = 0.52 C / W + 17.0 C / W + 1.25 C / W = 18.77 C / W
Determining PD:
PD = I AS2 * rDS(on)
Determining RTotal:
RTotal = RL + rDS(on) @ 80oC = 2.1Ω + 0.010Ω = 2.11Ω
Calculating the peak avalanche current:
Since the on-time of the MOSFET is > 5 * L/R (99.3+% of its peak value), we can
approximate IAS(PEAK) to be 100% of V/R to simplify our calculations
IAS(PEAK) = VDD / RTotal = 24V / 2.11Ω = 11.37A
Applying the rDS(on) value and peak current value to calculate power:
PD = I AS2 * rDS(on) = (11.37A)2 * 0.010Ω = 1.29W
o
o
o
TJ or TJ(START) = TA + (PD x RΘJ-A) = 80 C + (1.29W * 18.77 C / W) = 104.2 C
20
10
Single Pulse UIS Design Example
(con’t)
Re-calculating the rDS(on) based upon the 104.2oC calculated junction temperature:
rDS(on) @ 104.2oC = 0.008Ω * 1.375 [est HUFA75344P3 data sheet]
= 0.011Ω (This results in a 3 mΩ change)
Re-calculating the temperature based upon the new rDS(on) value results in a
junction temperature that is ≅ 2.5oC higher
Several iterations can be made to drive the solution closer to its final value
Each successive iteration will result in a smaller delta to the previously
attained value
We will use the rDS(on) value calculated at 80oC to simplify our calculations
21
Single Pulse UIS Design Example
(con’t)
Using the time in avalanche equation contained on our Single Pulse
UIS curve:
tAV = (L/RTotal) * ln[(IAS * RTotal)/(1.3 * Rated BVDSS – VDD) + 1]
= (0.0017H / 2.11Ω) * ln[(11.37A * 2.11Ω) / (71.5V – 24V) + 1]
= 0.00081 * ln[(24) / (47.5) + 1]
= 0.00081 * ln[0.505 + 1]
= 0.00081 * ln[1.505] = 0.00081 * 0.409 = 331μs
tAV = 331μs
Calculate the Energy Absorbed by the MOSFET during Avalanche:
EAS = ½ * 1.3 * Rated BVDSS * IAS * tAV
= (1.3 * 55V * 11.37A * 0.000331) / 2 = 135mJ
22
11
Single Pulse UIS Design Example
(con’t)
HUFA75344P3_S3 UIS Capability
400
IAS, Avalanche Current (A)
200
4000
3000
2000
100
1000
90
80
900
800
70
700
60
50
40
30
20
EAS, Avalanche Energy (mj)
300
If R=0
tAV=(L*IAS)/(1.3*Rated BVDSS-VDD)
If R>0
tAV=(L/R)ln[(IAS*R)/(1.3*Rated BVDSS-VDD)+1]
Starting TJ=25oC
600
500
The calculated data point
resides below the IAS
curve, therefore this
product is acceptable to
use in this application
10
0.01
400
300
200
Starting TJ=150oC
0.10
1.00
tAV, Time in Avalanche (msec)
100
10.00
HUFA75344P3_S3_Ias-tav.jnb
23
7 different ~60V MOSFETs with relatively close
RDS(ON) compared on a UIS perspective.
100
UIS comparison of similar
RDS(ON) and BVDSS devices
IAS
10
45mohm 60V comp A
32mohm 60V comp B
39mohm 60V comp C
39mohm 60V comp A
60mohm 60V comp A
43mohm 55V comp A
1
1.00E-05
24
37mohm 55V comp A
1.00E-04
1.00E-03
1.00E-02
tAV
12
Repetitive Pulse UIS Scenario
Start-up
Increase / Decrease
in rDS(on) Due to Die
Temperature Resulting
in an increase /
decrease in rDS(on)
Losses in the Next
Cycle
•
•
•
•
rDS(on) Losses
PAV Losses
PSWITCH Losses
Body Diode Losses
MOSFET TJ reaches
steady state
TJ(START)
•
•
•
•
Starting TA
MOSFET RΘJC
System’s RΘCA
Airflow
Losses = Power
Dissipation =
HEAT
25
Multiple or Repetitive UIS Usage
The Single Pulse UIS rating graph can be used for Repetitive Pulse with
the following considerations:
1) By using the technique of superposition in which each UIS pulse is considered
a separate event and the resulting TJ is evaluated as if no other pulse existed
2) Determine the IAS, tAV, & TJ(START) just as in the single pulse case
3) Usually the last pulse in a series occurs at the highest junction temperature
and is therefore the severest stress. If the stress for the last pulse is within the
rating then any previous pulse is also since it occurred at a lower temperature
4) Usually the junction temperature variation of a device over the full repetitive
period is small. The device’s thermal capacitance does not permit an
instantaneous change in the average junction temperature. Therefore using the
average junction temperature for TJ(START) does not result in appreciable error
5) In the majority of applications the tAV is typically < 5% of the repetition period
26
13
Repetitive Pulse UIS Design Example
Problem: A circuit contains a HUFA75344P3 MOSFET which drives a solenoid
(inductive load) load of 1.7mh with a dc resistance of 2.1Ω from a supply voltage of
24V. A gate signal of VGS = 10V is applied to the MOSFET gate and the solenoid is
energized at frequency of 50HZ with a 75% duty cycle
The system uses as heat sink and interface material described as follows:
Heat sink data and interface material from Aavidthermalloy:
Heat sink part number 6109PBG
o
RΘJ-A = 17.0 C / W
Interface isolation material In-Sil-8: Isolation material part number 1898
o
RΘC-S = 1.25 C / W
Determine if the HUFA75344P3 avalanche energy rating is exceeded and determine if
this device can be used reliably in the application
Calculate TJ(START)
27
TJ or TJ(START) = TA + (PD x RΘJ-A)
RΘJ-A = RΘJ-C + RΘC-S + RΘS-A
Repetitive Pulse UIS Design
Example (con’t)
Given in the problem:
Frequency = 50Hz
(new operating condition)
Duty Cycle = 75%
(new operating condition)
TA = 80oC
RL = 2.1Ω
L = 1.7mh
VDD = 24V
TJ(MAX) = 175oC
Rated BVDSS = 55V
(HUFA75344P3 data sheet)
(HUFA75344P3 data sheet)
RθJ-C = 0.52oC / W
(Aavid Thermalloy data sheet)
RθC-S = 1.25oC / W
(Aavid Thermalloy data sheet)
RθS-A = 17.0oC / W
o
rDS(on) @ 25 C = 0.008Ω (HUFA75344P3 data sheet)
rDS(on) @ 80oC = 0.008Ω * 1.25[est HUFA75344P3 data sheet] = 0.010Ω. Actually
the rDS(on) temperature multiplier is a function of TJ, but we will use TA for our
first iteration)
RθJ-A = 18.77oC / W (calculated in the single pulse example)
28
14
Repetitive Pulse UIS Design Example
(con’t)
Determining PD:
PD = PCOND + PAV
PD = IAS2 * rDS(on) * Duty Cycle + EAS * Frequency
PCOND
PAV
Determine IAS(PEAK):
L/R = 0.0017H/2.11Ω = 0.000806s
On time = (1/Frequency) * Duty Cycle = (1/50Hz) * 0. 75 = 0.015s
0.015s / 0.000806s > 18
Since the on-time of the MOSFET is > 18 * L/R (99.9+% of its peak value), we can
approximate IAS(PEAK) to be 100% of V/R to simplify our calculations
IAS(PEAK) = 11.37A (Calculated in the single pulse example)
Calculating PCOND:
PCOND = IAS2 * rDS(on) * Duty Cycle
= (11.37A)2 * 0.010Ω * 0.75 = 0.97W
29
Repetitive Pulse UIS Design Example
(con’t)
EAS = 135mj (Calculated in the single pulse example)
Calculating PAV:
PAV = EAS * Frequency = 135mj * 50Hz = 6.75W
Calculating PTOTAL
PTOTAL = PCOND + PAV = 0.97W + 6.73W =7.7W
TJ or TJ(START) = TA + (PD x RΘJ-A) = 80oC + (7.7*18.77oC/W) = 80oC+144.5oC = 224oC
TJ(START) > 175oC
This part cannot be used in this application since TJ(START) exceeds TJ(MAX) of 175oC
Since PCOND is a small percentage, ≅ 12%, of PTOTAL, it is recommended to choose a
heat sink with an RθS-A such that: TA + (PD x RΘJ-A) ≤175oC
30
15
Repetitive Pulse UIS Design Example
(con’t)
Recalculating TJ(START) with a more efficient heat sink:
Recalculating the rDS(on) @ 175oC:
o
rDS(on) @ 175 C = 0.008Ω *2.0 [est HUFA75344P3 data sheet ] = 0.016Ω
This results in a 8 milliohm change
PCOND = IAS2 * rDS(on) * Duty Cycle = (11.37A)2 * 0. 016Ω * 0.75 = 1.55W
Recalculating PTOTAL:
PTOTAL = PCOND + PAV = 1.55W + 6.75W =8.3W
RΘJ-A = RΘJ-C + RΘC-S + RΘS-A = 0.52oC + 1.25oC + 8oC = 9.77oC / W
TJ or TJ(START) = TA + (PD x RθJ-A) = 80oC + (8.3 * 9.77oC / W) = 80oC + 81.1oC =
161.1oC
o
The TJ of the MOSFET now resides below the 175 C maximum operating
temperature
31
Conclusions
• A Power MOSFET’s UIS capability has a IAS2 * tAV = constant relationship
• A Power MOSFET’s avalanche energy is not a constant, but varies as a
function of the time in avalanche
• A simple single pulse UIS Rating system has been defined. By plotting
the device’s operating point of IAS and tAV on the rating graph, one can
easily determine if the device is being operated safely
• A simple rating system for repetitive pulses has been presented. Using
the single pulse information and TJ(AVG) the repetitive pulse operation can
be quickly analyzed
• Significant, usable avalanche energy capability exists in a Power
MOSFET as long as TJ(START) ≤ TJ(MAX)
32
16
Articles on Unclamped Inductive
Switching
1. “Single Pulse Unclamped Inductive Switching: A Rating System”,
Fairchild Application Note AN-7514
2. “A combined Single Pulse and Repetitive UIS Rating System”, Fairchild
Application Note AN-7515
3. “Boundary of Power MOSFET Unclamped Inductive (UIS) Avalanche
Current Capability”, Rodney R. Stoltenburg, Proc. 1989 Applied Power
Electronics Conference, pp 359-364, March 1989
4. “Rating System Compares Single Pulse Unclamped Inductive
Switching for MOSFETs”, Harold Ronan, PCIM magazine, pp 32-40,
Sept. 1991
5. “Power Rectifier UIS Capability”, Harold Ronan, John Worman
33
Related Links
The pdf version of the Power Seminar presentations are available on the our external
website. To access or download the pdfs, please visit
www.fairchildsemi.com/power/pwrsem2006.html
To access the Power Seminar 2004 archived webcasts, please visit
www.fairchildsemi.com/onlineseminars
For product datasheets, please visit www.fairchildsemi.com
For application notes, please visit www.fairchildsemi.com/apnotes
For application block diagrams, please visit www.fairchildsemi.com/markets
For design tools, please visit the design center at www.fairchildsemi.com
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