LMH6503
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SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
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FEATURES
DESCRIPTION
•
The LMH™6503 is a wideband, DC coupled,
differential input, voltage controlled gain stage
followed by a high-speed current feedback Op Amp
which can directly drive a low impedance load. Gain
adjustment range is more than 70dB for up to 10MHz.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
VS = ±5V, TA = 25°C, RF = 1kΩ, RG = 174Ω, RL =
100Ω, AV = AV(MAX) = 10, Typical Values Unless
Specified.
-3dB BW 135MHz
Gain Control BW 100MHz
Adjustment Range (Typical Over Temp) 70dB
Gain Matching (Limit) ±0.7dB
Slew Rate 1800V/µs
Supply Current (No Load) 37mA
Linear Output Current ±75mA
Output Voltage (RL = 100Ω) ±3.2V
Input Voltage Noise 6.6nV/√Hz
Input Current Noise 2.4pA/√Hz
THD (20MHz, RL = 100Ω, VO = 2VPP) −57dBc
Replacement for CLC522
APPLICATIONS
•
•
•
•
Variable Attenuator
AGC
Voltage Controller Filter
Multiplier
Maximum gain is set by external components and the
gain can be reduced all the way to cut-off. Power
consumption is 370mW with a speed of 135MHz .
Output referred DC offset voltage is less than 350mV
over the entire gain control voltage range. Device-todevice Gain matching is within 0.7dB at maximum
gain. Furthermore, gain at any VG is tested and the
tolerance is ensured. The output current feedback Op
Amp allows high frequency large signals (Slew Rate
= 1800V/μs) and can also drive heavy load current
(75mA). Differential inputs allow common mode
rejection in low level amplification or in applications
where signals are carried over relatively long wires.
For single ended operation, the unused input can
easily be tied to ground (or to a virtual half-supply in
single supply application). Inverting or non-inverting
gains could be obtained by choosing one input
polarity or the other.
To further increase versatility when used in a single
supply application, gain control range is set to be
from −1V to +1V relative to pin 11 potential (ground
pin). In single supply operation, this ground pin is tied
to a "virtual" half supply. Gain control pin has high
input impedance to simplify its drive requirement.
Gain control is linear in V/V throughout the gain
adjustment range. Maximum gain can be set to be
anywhere between 1V/V to 100V/V or higher. For
linear in dB gain control applications, see LMH6502
datasheet.
The LMH6503 is available in the SOIC-14 and
TSSOP-14 package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6503
SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
www.ti.com
30
11
dB
20
9
85°C
-40°C
0
25°C
-10
GAIN (dB)
-40°C
8
7
85°C
-20
6
25°C
-30
5
-40
4
-50
GAIN (V/V)
10
10
3
V/V
-60
2
-70
1
VIN_DIFF = ±0.1V
-80
0
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
VG (V)
Figure 1. Gain vs. VG for Various Temperature
Typical Application
+5V
+VIN
3
R1
50:
RF
1k:
NC
1
14
12
4
13
RG
170:
VOUT
LMH6503
10
5
-VIN
6
2
8 7
R2
50:
9
RL
100:
11
-5V
VG
Figure 2. AVMAX = 10V/V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
ESD Tolerance: (3)
Human Body
2KV
Machine Model
200V
Input Current
±10mA
±(V+ −V−)
VIN Differential
120mA (4)
Output Current
+
−
Supply Voltages (V - V )
12.6V
V+ +0.8V,V− - 0.8V
Voltage at Input/ Output pins
Soldering Information:
Infrared or Convection (20 sec)
235°C
Wave Soldering (10 sec)
260°C
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(1)
(2)
(3)
(4)
+150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.
The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Operating Ratings (1)
Supply Voltages (V+ - V−)
5V to 12V
−40°C to +85°C
Temperature Range
θJA
θJC
14-Pin SOIC
138°C/W
45°C/W
14-Pin TSSOP
160°C/W
51°C/W
Thermal Resistance:
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
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Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min (2)
Typ (2)
Max (2)
Units
Frequency Domain Response
BW
-3dB Bandwidth
VOUT < 0.5PP
135
VOUT < 0.5PP, AV(MAX) = 100
50
40
MHz
GF
Gain Flatness
VOUT < 0.5VPP,
−1V < VG < 1V, ±0.2dB
MHz
Att Range
Flat Band (Relative to Max Gain)
Attenuation Range (3)
±0.2dB Flatness, f < 30MHZ
20
±0.1dB, f < 30MHZ
6.6
BW
Control
Gain Control Bandwidth
VG = 0V (4)
100
MHz
PL
Linear Phase Deviation
DC to 60MHz
1.6
deg
G Delay
Group Delay
DC to 130MHz
2.6
ns
CT (dB)
Feed-through
VG = −1.2V, 30MHz (Output
Referred)
−48
dB
GR
Gain Adjustment Range
f < 10MHz
79
f < 30MHz
68
MHz
dB
Time Domain Response
tr , tf
Rise and Fall Time
0.5V Step
2.2
ns
OS%
Overshoot
0.5V Step
10
%
SR
Slew Rate
4V Step
(5)
1800
V/µs
ΔG Rate
Gain Change Rate
VIN = 0.3V, 10%−90% of final
output
4.6
dB/ns
Distortion & Noise performance
HD2
2nd Harmonic Distortion
2VPP, 20MHz
−60
dBc
HD3
3rdHarmonic Distortion
2VPP, 20MHz
−61
dBc
THD
Total Harmonic Distortion
2VPP, 20MHz
−57
dBc
En tot
Total Equivalent Input Noise
1MHz to 150MHz
6.6
nV/√Hz
In
Input Noise Current
1MHz to 150MHz
2.4
pA/√Hz
DG
Differential Gain
f = 4.43MHz, RL = 150Ω, Neg.
Sync
0.15
%
DP
Differential Phase
f = 4.43MHz, RL = 150Ω, Neg.
Sync
0.22
deg
(1)
(2)
(3)
(4)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.
Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB), relative to AVMAX gain. For example, for f<30MHz, here are the Flat Band Attenuation
ranges:±0.2dB:
10V/V down to 1V/V=20dB range±0.1dB:
10V/V down to 4.7V/V=6.5dB range
Gain Control Frequency Response Schematic:
RF
910:
+0.2VDC
+VIN
ROUT
50:
+
R1
50:
RG
820:
-VIN
R2
50:
PORT 1
RT
50:
RL
50:
2
VG
+5V
C1
0.01PF
RF IN
PORT 2
LMH6503
RP1
10k:
0V
DC
-5V
(5)
4
Slew Rate is the average of the rising and falling rates.
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Typ (2)
Max (2)
VG =1.0V
+0.25
+0.9/−0.4
0V < VG < 1V
±0.3
+1.3/−1.5
−0.7V < VG < 1V
±0.4
+4.4/−4.3
Parameter
Test Conditions
Min (2)
Units
DC & Miscellaneous Performance
GACCU
G Match
Gain Accuracy (see Application
Information)
Gain Matching (see Application
Information)
VG = 1.0
–
±0.7
0 < VG < 1V
–
+1.7/−1.1
−0.7V < VG < 1V
–
+4.0/−4.7
1.58
1.58
1.72
1.87
1.91
K
Gain Multiplier (see Application
Information)
VCM
Input Voltage Range
Pin 3 & 6 Common Mode,
|CMRR| > 50dB (6)
±2.0
±1.80
±2.2
Differential Input Voltage
Across pins 3 & 6
±0.34
±0.28
±0.37
RG Current
Pins 4 & 5
±1.70
±1.60
±2.30
Bias Current
Pins 3 & 6 (7)
11
18
20
Pins 3 & 6 (7),
VS= ±2.5V
3
10
13
VIN_
IRG
DIFF
MAX
IBIAS
dB
dB
V/V
V
V
mA
µA
TCBIAS
Bias Current Drift
Pin 3 & 6 (8)
100
I OFF
Offset Current
Pin 3 & 6
0.01
TC IOFF
Offset Current Drift
See (8)
5
nA/°C
RIN
Input Resistance
Pin 3 & 6
750
kΩ
CIN
Input Capacitance
Pin 3 & 6
5
pF
IVG
VG Bias Current
Pin 2, VG = 1.4V (7)
45
µA
TC IVG
VG Bias Drift
Pin 2 (8)
20
nA/°C
R VG
VG Input Resistance
Pin 2
70
KΩ
C VG
VG Input Capacitance
Pin 2
1.3
pF
VOUT
Output Voltage Range
RL = 100Ω
±3.00
±2.97
±3.20
RL Open
±3.95
±3.90
±4.05
0.1
Ω
±75
±70
±90
mA
nA/°C
2.0
2.5
µA
V
ROUT
Output Impedance
DC
IOUT
Output Current
VOUT ±4V from Rails
VO
Output Offset Voltage
−1V < VG < 1V
±80
±350
±380
mV
+PSRR
+Power Supply Rejection Ratio
(See (9))
Input Referred, 1V change,
VG = 1.4V
−80
−58
−56
dB
−PSRR
−Power Supply Rejection Ratio
(See (9))
Input Referred, 1V change,
VG = 1.4V
−67
−57
−51
dB
CMRR
Common Mode Rejection Ratio
(See (10))
Input Referred, VG = 1V
−1.8V < VCM < 1.8V
−67
OFFSET
dB
CMRR definition: [|ΔVOUT/ΔVCM|/AV] with 0.1V differential input voltage. ΔVOUT is the change in output voltage with offset shift
subtracted out.
(7) Positive current correspondes to current flowing in the device.
(8) Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
(9) +PSRR definition: [|ΔVOUT/ΔV+| /AV], -PSRR definition: [|ΔVOUT/ΔV−| /AV] with 0.1V differential input voltage. ΔVOUT is the change in
output voltage with offset shift subtracted out.
(10) CMRR definition: [|ΔVOUT/ΔVCM|/AV] with 0.1V differential input voltage. ΔVOUT is the change in output voltage with offset shift
subtracted out.
(6)
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VS = ±5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF
= ±0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Parameter
IS
Min (2)
Typ (2)
Max (2)
RL = Open
37
50
53
RL = Open, VS = ±2.5V
12
20
23
Test Conditions
Supply Current
Units
mA
Connection Diagram
Top View
V
+
14
1
13
2
NC
VG
3
12
+VIN
+RG
I
4
11
5
10
-VIN
-
-
GND
VOUT
-RG
V
+
V
9
6
VREF
7
8
-
V
Figure 3. 14-Pin SOIC AND TSSOP Packages
See Package Numbers D0014A and PW0014A
6
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Typical Performance Charateristics
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Small Signal Frequency Response (AV = 2)
Large Signal Frequency Response (AV = 2)
5
5
90
RF = 920:, RG = 820:
3
GAIN
45
0
0
-5
0
-3
GAIN (dB)
RF = 2.4k:, RG = 2.1k:
-18
-15
-90
-20
-13
-15
-45
-25
VOUT = 0.5VPP
1M
10M
100M
1G
-225
RG = 2.15k:
-35
100k
-20
-180
AVMAX = 2
RF = 2.4k:
-30
AVMAX = 2
-135
VOUT = 5VPP
-270
1M
10M
Figure 4.
Figure 5.
Frequency Response over Temperature (AV = 10)
GAIN
0
-40°C
-1
Frequency Response for Various VG (AVMAX = 10)
150
1
100
0
50
-1
0
-2
20
1.2V
-0.4V
-50
25°C
-100
-4
85°C
-150
-5
AVMAX = 10, VG = VGMAX
-6
GAIN/PHASE DATA
-7
GAIN (dB)
GAIN (dB)
-40°C
PHASE (°)
25°C
-3
PHASE
FREQUENCY VALUE AT 25°C
-9
1k
10k
100k
1M
10M
100M
-60
-4
-1.0V
-80
-5
-200
-6
-250
-7
-300
-8
-350
-9
-160
1k
1
0V
-2
-40
0V
-60
-0.48V
-80
25°C
VS = ±2.5V
-100
AVMAX = 10
GAIN NORMALIZED TO
LOW FREQUENCY
-120
-160
VALUE AT EACH VG
-7
1k
10k
100k
1M
10M
100M
-7
1G
270
2
VOUT = 0.5VPP
1
GAIN
0
-1
GAIN (dB)
GAIN (dB)
0
PHASE (°)
0.55V
GAIN
1G
Small Signal Frequency Response
-20
-1
100M
3
40
0
-6
10M
Figure 7.
20
-5
1M
100k
FREQUENCY (Hz)
PHASE
-4
10k
Figure 6.
2
-120
-140
EACH VG
FREQUENCY (Hz)
-0.48V
-100
AVMAX = 10
GAIN NORMALIZED TO LOW
FREQUENCY VALUE AT
Frequency Response for Various VG (AVMAX = 10) (±2.5V)
-3
-40
-0.4V
1G
3
0
-20
1.2V
-3
NORMALIZED TO LOW
-8
40
-1.0V
GAIN
85°C
-2
PHASE
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
1
100M
PHASE (°)
-8
-10
-10
-2
AVMAX
RF(k:)
225
100
10
2
750
1k
2.4k
180
90
45
100
-3
135
10
2
0
-45
-4
PHASE
-5
-90
-6
-135
-7
-180
-8
-9
PHASE (°)
GAIN (dB)
-5
PHASE (°)
PHASE
-225
SEE NOTE 12
-270
f (25 MHz/DIV)
FREQUENCY (Hz)
Figure 8.
Figure 9.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Frequency Response for Various VG (AVMAX = 100)
(Small Signal)
270
2
VOUT = 5VPP
AVMAX
RF(k:)
225
1
GAIN
100
10
2
750
1k
2.4k
180
GAIN (dB)
-2
100
-3
135
90
-2
45
2
0
10
-4
-45
PHASE
-5
-90
PIN = -42dBm
20
0
PHASE
-20
-40
-4
1.1V
-60
-5
0.5V
-135
-7
-180
-8
-225
-7
-270
-8
SEE NOTE 12
40
AVMAX = 100
-3
-6
-9
60
SEE NOTE 12
GAIN
0
-1
GAIN (dB)
0
-1
1
PHASE (°)
3
PHASE (°)
Large Signal Frequency Response
-80
-6
0V
-100
-0.5V
0
f (25 MHz/DIV)
-120
100M
50M
f (10 MHz/DIV)
Figure 10.
Figure 11.
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
1
Gain Control Frequency Response
5
60
SEE NOTE 12
GAIN
40
AVMAX = 100
-1
PIN = -22dBm
0
PHASE
-3
-20
-40
-4
1.1V
S21 (dB)
GAIN (dB)
-2
0
20
PHASE (°)
0
-5
-10
0.5V
-80
-6
-15
0V
-100
-7
0
-120
100M
50M
AVMAX = 2V/V
S21 (dB) + 20 PLOTTED
SEE NOTE 11
-20
100k
1M
-0.5V
-8
VG = 0V AVERAGE
PIN = 0dBm
-60
-5
f (10 MHz/DIV)
10M
100M
1G
FREQUENCY (Hz)
Figure 12.
Figure 13.
IS vs. VS
IS vs. VS
60
60
85°C
50
50
85°C
25°C
25°C
40
-40°C
IS (mA)
IS (mA)
40
30
20
30
-40°C
20
RL = OPEN
10
RL = OPEN
10
VG = VG_MAX
VG = VG_MIN
0
0
2.5
8
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
±SUPPLY VOLTAGE (V)
±SUPPLY VOLTAGE (V)
Figure 14.
Figure 15.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Input Bias Current vs. VS
AVMAX vs. VS
18
12
-40°C
16
10
85°C
14
85°C
IB (PA)
25°C
10
-40°C
8
8
AVMAX (V/V)
12
6
6
25°C
4
-40°C
4
2
VG = VG_MAX
2
VIN_DIFF = 0.1V
0
0
2.5
3
3.5
4
4.5
5
5.5
6
2.5
2
3
±SUPPLY VOLTAGES (V)
3.5
Figure 16.
4.5
5
5.5
6
Figure 17.
PSRR ±5V
PSRR ±2.5V
0
0
SEE NOTE 10
SEE NOTE 10
-10
-10
-20
-20
-30
-40
PSRR (dB)
-30
PSRR (dB)
4
±Supply Voltage (V)
+PSRR
-50
-60
+PSRR
-40
-50
-60
-PSRR
-70
-80
-70
VS = ±5V
VS = ±2.5V
-PSRR
-80
VG = VGMAX
-90
VG = VGMAX
-90
1k
10k
100k
1M
10M
100M
1k
10k
10M
Figure 18.
Figure 19.
100M
CMRR ±2.5V
0
SEE NOTE 9
SEE NOTE 9
-20
-20
-40
CMRR (dB)
-40
CMRR (dB)
1M
FREQUENCY (Hz)
CMRR ±5V
0
100k
FREQUENCY (Hz)
MAXGAIN
-60
MAXGAIN
-60
-80
-80
VS = ±5V
-100
VS = ±2.5V
-100
AVMAX = 10
AVMAX = 10
PIN = 0dBm
MIDGAIN
PIN = 0dBm
MIDGAIN
-120
-120
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20.
Figure 21.
10M
100M
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
AVMAX vs. VCM
AVMAX vs. VCM
12
12
10
10
8
85°C
6
25°C
4
-40°C
8
2
AVMAX (V/V)
AVMAX (V/V)
85°C
VS = ±2.5V
4
VS = ±5V
VIN_DIFF = 0.1V
-2
VG = VGMAX
-40°C
2
0
VIN_DIFF = 0.1V
0
25°C
6
VG = VGMAX
-4
-2
-2
-3
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-1
1
0
2
3
VCM (V)
VCM (V)
Figure 22.
Figure 23.
Supply Current vs. VCM
60
Supply Current vs. VCM
28
85°C
85°C
85°C
25°C
26
50
24
40
22
-40°C
IS (mA)
IS (mA)
25°C
30
20
20
-40°C
18
16
14
VS = ±5V
10
VS = ±2.5V
12
VG = VGMAX
0
VG = VGMAX
10
-3
-2
-1
0
1
2
-1.5
3
-1
-0.5
0
0.5
1
1.5
VCM (V)
VCM (V)
Figure 24.
Figure 25.
Output Offset Voltage vs.VCM (Typical Unit 1)
Output Offset Voltage vs.VCM (Typical Unit 2)
0
120
85°C
-5
-40°C
110
25°C
-10
VO_OFFSET (mV)
VO_OFFSET (mV)
100
90
80
85°C
70
25°C
-20
-25
-30
-40°C
60
-35
VS = ±5V
50
VS = ±5V
-40
VG = VGMAX
VG = VGMAX
-45
40
-3
-2
-1
0
1
2
3
VCM (V)
-3
-2
-1
0
1
2
3
VCM (V)
Figure 26.
10
-15
Figure 27.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Output Offset Voltage vs.VCM (Typical Unit 3)
Feed through Isolation
60
-100
40
-110
-40°C
0
85°C
GAIN (dB)
VO_OFFSET (mV)
20
-120
-130
-140
-40
AVMAX = 100
AVMAX = 2
-60
25°C
-150
AVMAX = 10
-20
-80
-160
VS = ±5V
-100
VG = VGMAX
-120
100k
-170
-2
-3
-1
1
0
2
3
1M
Figure 28.
Gain Flatness and Linear Phase Deviation
-1.0V
1.6
0.10
1.2
1.2V
0.00
0.8
PHASE
-0.10
0.4
-0.20
0
1.2V
-0.30
-0.4V
-1.0V
-0.40
-0.4
-0.8
GAIN DATA NORMALIZED TO LOW
FREQUENCY VALUE AT EACH VG
10M
RF = 1k:
1M
RG = 170:
±0.1dB
PIN = -10dBm
-1.2
VG VARIED
100k
-1.6
-0.60
±0.2dB
100M
2
-0.4V
GAIN FLATNESS (Hz)
(RELATIVE TO MAX GAIN)
GAIN
LINEAR PHASE DEVIATION (°)
GAIN (dB)
(1)
Gain Flatness Frequency vs. Gain
2.4
0.20
-0.50
100M
Figure 29.
0.40
0.30
10M
FREQUENCY (Hz)
VCM (V)
0
f (3 MHz/DIV)
1
2
3
4
5
6
7
8
9
10
AV (V/V)
Figure 30.
Figure 31.
Group Delay vs. Frequency
K Factor vs. RG
2.80
2.1
VG = VGMAX
RF = 477:
2
AVMAX = 10
RF = 690:
1.9
2.60
1.8
2.50
K (V/V)
GROUP DELAY (ns)
2.70
2.40
2.30
1.7
RF = 6.18k:
1.6
RF = 1.3k:
1.5
2.20
1.4
2.10
1.3
2.00
1.2
10
f (5 MHz/DIV)
100
1k
2k
RG (:)
Figure 32.
(1)
Figure 33.
Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB), relative to AVMAX gain. For example, for f<30MHz, here are the Flat Band Attenuation
ranges:±0.2dB:
10V/V down to 1V/V=20dB range±0.1dB:
10V/V down to 4.7V/V=6.5dB range
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Gain vs. VG Including Limits
BW vs. RF for Various RG
1000
12
RG = 100:
VIN_DIFF = ±0.1V
RG = 180:
10
RG = 466:
LIMIT HIGH
100
RG = 1190:
BW (MHz)
GAIN (V/V)
8
TYPICAL
6
LIMIT LOW
RG = 47:
10
4
RG = 27:
2
0
-1.2
-0.4
-0.8
0
0.8
0.4
1
100
1.2
1k
10k
VG (V)
Figure 34.
Figure 35.
Gain vs. VG (±5V)
Output Offset Voltage vs. VG
(Typical Unit 1)
30
11
dB
85°C
-40°C
GAIN (dB)
0
-40°C
25°C
-10
-40°C
100
9
7
85°C
-20
6
25°C
-30
5
-40
4
-50
25°C
8
VO_OFFSET (mV)
10
120
10
GAIN (V/V)
20
-60
2
-70
-80
0
40
20
0
-0.4
85°C
60
1
VIN_DIFF = ±0.1V
-0.8
80
3
V/V
-1.2
0.4
0.8
0
1.2
-1
-1.5
-0.5
VG (V)
0
0.5
1
1.5
VG (V)
Figure 36.
Figure 37.
Output Offset Voltage vs. VG
(Typical Unit 2)
Output Offset Voltage vs. VG
(Typical Unit 3)
15
0
10
-20
5
-40
0
85°C
-5
25°C
-10
-15
VO_OFFSET (mV)
VO_OFFSET (mV)
100k
RF (:)
-60
-40°C
-80
-100
85°C
25°C
-120
-20
-40°C
-140
-25
-30
-1.5
-160
1
-0.5
0
0.5
1
1.5
-1
-05
0
0.5
1
1.5
VG (V)
VG (V)
Figure 38.
12
-1.5
Figure 39.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
Output Offset Voltage vs. ±VS for Various VG
(Typical Unit 1)
Output Offset Voltage vs. ±VS for Various VG
(Typical Unit 2)
140
25
20
MAX
120
MIN
100
10
VO_OFFSET (mV)
VO_OFFSET (mV)
15
MID
80
60
MIN
40
5
0
MID
-5
-10
MAX
-15
20
-20
0
-25
2.5
3
3.5
4
4.5
5
5.5
6.5
6
2.5
3
3.5
4
4.5
±VS (V)
Figure 40.
5.5
6
6.5
Figure 41.
Output Offset Voltage vs. ±VS for Various VG
(Typical Unit 3)
Gain vs. VG (±2.5V)
10
0
VS = ±2.5V
9
-20
RF = 980:
MIN
8
-40
RG = 180:
7
-60
-80
GAIN (V/V)
VO_OFFSET (mV)
5
±VS (V)
MID
-100
-120
MAX
6
5
4
-140
3
-160
2
-180
1
0
-200
2.5
3
3.5
4
4.5
5
5.5
6
-0.6
6.5
-0.4
0.0
-0.2
0.2
0.4
0.6
VG (V)
±VS (V)
Figure 42.
Figure 43.
Noise vs. Frequency (AVMAX = 2)
Noise vs. Frequency (AVMAX = 10)
10000
10000
AVMAX = 2
MAX GAIN
AVMAX = 10
RF = 910:
RF = 1k:
RG = 820:
RG = 180:
eno (nV/ Hz)
eno (nV/ Hz)
MAX GAIN
1000
MID GAIN
100
1000
MID GAIN
100
MIN GAIN
MIN GAIN
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 44.
Figure 45.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
−1dB Compression
Noise vs. Frequency (AVMAX = 100)
24
100k
OUTPUT LIMITED , RF = 1.5k:
23
en(OUT) (nV/ Hz)
10k
-1dB COMPRESSION (dBm)
MAX GAIN
MID GAIN
NO GAIN
1k
AVMAX = 100
100 RF = 2k:
RG = 24:
22
21
20
INPUT LIMITED, RF = 620:
19
18
17
VG = VGMAX
16
RL = 100:
RG = 180:
15
10
10
1k
100
10k
100k
1M
0
10M
20
40
FREQUENCY (Hz)
60
80
100 120 140 160
FREQUENCY (MHz)
Figure 46.
Figure 47.
Output Voltage vs. Output Current
HD2 vs. POUT
90
4.5
AVMAX = 10
1MHz
VIN_DIFF = ±0.5V
4
85
VG = VGMAX
3.5
80
3
2.5
SOURCE
2
|HD (dBc)|
VOUT FROM SUPPLY (V)
SINK
75
70
65
1.5
10MHz
60
1
0.5
55
0
50
0
20
40
60
80
20MHz
-10
100
-5
0
5
10
Figure 48.
HD3 vs. POUT
THD vs. POUT
90
1MHz
85
90
1MHz
80
10MHz
80
10MHz
70
|HD (dBc)|
|HD (dBc)|
75
60
20MHz
50
70
65
60
20MHz
55
40
AVMAX = 10
50
VG = VGMAX
45
20
-10
14
20
Figure 49.
100
30
15
POUT (dBm)
IOUT (mA)
-5
0
5
10
15
20
AVMAX = 10
VG = VGMAX
40
-10
-5
0
5
10
POUT (dBm)
POUT (dBm)
Figure 50.
Figure 51.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
HD2 & HD3 vs. VG
90
HD3, 0.25VPP
0.25VPP
80
70
HD2, 0.25VPP
1VPP
60
70
HD2, 1VPP
50
|THD (dBc)|
|HD (dBc)|
THD vs. VG
80
60
50
HD2, 2VPP
40
2VPP
30
HD3, 2VPP
40
30
20
10
HD3, 1VPP
f = 20MHz
20MHZ
0
20
-1
-0.6
-0.2
0.2
0.6
-1
1
Figure 52.
50
-0.6
-0.2
0.2
0.6
1
VG (V)
VG (V)
Figure 53.
VG Bias Current vs. VG
Step Response Plot
0.5VPP SMALL SIGNAL
45
40
IVG (PA)
35
SS REF
30
25
20
LS REF
15
10
5
5VPP LARGE SIGNAL
0
-1.4 -1.0
-0.6
-0.2
0.2
0.6
1.0
1.4
4 ns/DIV
VG (V)
Figure 54.
Figure 55.
Step Response Plot
Gain vs. VG Step
1.5
10
VIN= 0.3V
1.2
9
AVMAX= 10
0.9
8
RL= 100:
0.6
VG (V)
SS REF
LS REF
7
0.3
0
6
VG
5
-0.3
VG = VG_MID
2.5VPP LARGE SIGNAL
GAIN
4
-0.6
3
-0.9
2
-1.2
1
-1.5
0
GAIN (V/V)
0.5VPP SMALL SIGNAL
4 ns/DIV
t (10ns/DIV)
Figure 56.
Figure 57.
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Typical Performance Charateristics (continued)
Unless otherwise specified: VS = ±5V, 25°C, VG = VG_MAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL
= 100Ω, Typical values, results referred to device output:
VG Feedthrough
AVMAX= 10
VG (1V/DIV)
0
VOUT
VOUT (40mV/DIV)
RL= 100:
VG
0
t (10ns/DIV)
Figure 58.
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APPLICATION INFORMATION
THEORY OF OPERATION
The LMH6503 is a linear wideband variable-gain amplifier as illustrated in Figure 59. A voltage input signal may
be applied differentially between the two inputs (+VIN, −VIN), or single-endedly by grounding one of the two
unused inputs. The LMH6503 input buffers convert the input voltage to a current (IRG) that is a function of the
differential input voltage (VINPUT = (+VIN) - (−VIN)) and the value of the gain setting resistor (RG). This current (IRG)
is then mirrored to a gain stage with a current gain of K (1.72 nominal). The voltage controlled two-quadrant
multiplier attenuates this current which is then converted to a voltage via the output amplifier. This output
amplifier is a current feedback op amp configured as a Transimpedance amplifier. Its Transimpedance gain is the
feedback resistor (RF). The input signal, output, and gain control are all voltages. The output voltage can easily
be calculated as shown in Equation 1:
VOUT = IRG x K x
VG + 1
FOR -1 < VG < +1
x RF
2
(1)
Where K = 1.72 (Nominal)
since:
VINPUT
IRG =
RG
(2)
The gain of the LMH6503 is therefore a function of three external variables: RG, RF, and VG as expressed in
Equation 3:
RF
AV =
RG
VG + 1
x 1.72 x
2
(3)
The gain control voltage (VG) has an ideal input range of −1V < VG < +1V. At VG = +1V, the gain of the LMH6503
is at its maximum as expressed in Equation 4:
AV = 1.72
RF
RG
(4)
Notice also that Equation 4 holds for both differential and single-ended operation.
VG
+VIN
X1
I
-
IRG
VINPUT
RG
K
IRG
X
VG + 1
X1
-
RF
CFB
OP AMP
+
2
VOUT
VREF
-VIN
Figure 59. LMH6503 Functional Block Diagram
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CHOOSING RF AND RG
RG is calculated using Equation 5. VINPUTMAX is the maximum peak input voltage (Vpk) determined by the
application. IRGMAX is the maximum allowable current through RG and is typically 2.3mA. Once AVMAX is
determined from the minimum input and desired output voltages, RF is then determined using Equation 6. These
values of RF and RG are the minimum possible values that meet the input voltage and maximum gain constraints.
Scaling the resistor values will decrease bandwidth and improve stability.
VINPUTMAX
RG =
RF =
I
RGMAX
(5)
1
* RG * AVMAX
K
(6)
Figure 60 illustrates the resulting LMH6503 bandwidths as a function of the maximum ( y axis) and minimum
(related to x axis) input voltages when VOUT is held constant at 1VPP.
10
5MHz
VINMAX (VP)
10MHz
2.7MHz
1
150MHz
100MHz
0.1
VOUT = 1VPP
50MHz
VG = VGMAX
20MHz
IRGMAX = 2.3mA
0.01
1
10
100
AVMAX (V/V)
Figure 60. Bandwidth vs. VINMAX and AVMAX
ADJUSTING OFFSETS
Treating the offsets introduced by the input and output stages of the LMH6503 is accomplished with a two step
process. The offset voltage of the output stage is treated by first applying −1.1V on VG, which effectively isolates
the input stage and multiplier core from the output stage. As illustrated in Figure 61, the trim pot located at R14
on the LMH6503 Evaluation Board (LMH730033) should then be adjusted in order to null the offset voltage seen
at the LMH6503's output (pin 10).
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Figure 61. Nulling the Output Offset Voltage
Once this is accomplished, the offset errors introduced by the input stage and multiplier core can then be treated.
The second step requires the absence of an input signal and matched source impedances on the two input pins
in order to cancel the bias current errors. This done, then +1.1V should be applied to VG and the trim pot located
at R10 adjusted in order to null the offset voltage seen at the LMH6503's output. If a more limited gain range is
anticipated, the above adjustments should be made at these operating points. These steps will minimize the
output offset voltage. However, since the offset term itself varies with the gain setting, the correction is not
perfect and some residual output offset will remain.
GAIN ACCURACY
Defined as the ratio of measured gain (V/V), at a certain VG, to the best fit line drawn through the typical gain
(V/V) distribution for −1V < VG < 1V (results expressed in dB) (See Figure 62). The best fit gain (AV) is given by:
AV (V/V) = 4.87VG + 4.61
For: −1V ≤ VG ≤ + 1V, RF = 1kΩ, RG = 174Ω
(7)
(8)
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the worst case ratio between the "Typical Gain" and the best fit line. The "Max" value
would be the worst case between the max/min gain limit and the best fit line.
GAIN MATCHING
Defined as the limit on gain variation at a certain VG (expressed in dB) (See Figure 62). Specified as "Max" only
(no "Typical"). For a VG range, the value specified represents the worst case matching over the entire range. The
"Max" value would be the worst case ratio between the max/min gain limit and the typical gain.
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MAX GAIN LIMIT
MIN GAIN LIMIT
GAIN (V/V)
D
C
TYPICAL GAIN
B
A
BEST FIT LINE
VG (V)
PARAMETER:
GAIN ACCURACY (TYPICAL) = B/C (dB)
GAIN ACCURACY (+ & - LIMIT) = D/C & A/C (dB)
GAIN MATCHING (+ & - LIMIT) = D/B & A/B (dB)
Figure 62. Gain Accuracy and Gain Matching Parameters Defined
NOISE
Figure 63 describes the LMH6503's output-referred spot noise density as a function of frequency with AVMAX =
10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50Ω, the input
noise contribution is minimal. At AVMAX = 10V/V, the LMH6503 has a typical flat-band input-referred spot noise
density (ein) of 6.6nV/√Hz. For applications with −3dB BW extending well into the flat-band region, the input RMS
voltage noise can be determined from the following single-pole model:
VRMS = ein * 1.57 * (-3dB BANDWIDTH)
(9)
10000
AVMAX = 10
RF = 1k:
RG = 180:
eno (nV/ Hz)
MAX GAIN
1000
MID GAIN
100
MIN GAIN
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 63. Output Referred Voltage Noise vs. Frequency
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CIRCUIT LAYOUT CONSIDERATIONS
Good high-frequency operation requires all of the de-coupling capacitors shown in Figure 64 to be placed as
close as possible to the power supply pins in order to insure a proper high-frequency low-impedance bypass.
Adequate ground plane and low inductive power returns are also required of the layout. Minimizing the parasitic
capacitances at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency performance. The parasitic
inductance of component leads or traces to pins 4, 5 and 9 should also be kept to a minimum. Parasitic or load
capacitance, CL, on the output (pin 10) degrades phase margin and can lead to frequency response peaking or
circuit oscillation. The LMH6503 is fully stable when driving a 100Ω load. With reduced load (e.g. 1kΩ) there is a
possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the
LMH6503 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g.
100Ω and 39pF in series tied between the LMH6503 output and ground). CL can also be isolated from the output
by placing a small resistor in series with the output (pin 10).
Figure 64. Required Power Supply Decoupling
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board Part Number
LMH6503MA
SOIC-14
LMH730033
SINGLE SUPPLY OPERATION
It is possible to operate the LMH6503 with a single supply. To do so, tie pin 11 (GND) to a potential about mid
point between V+ and V−. Two examples are shown in Figure 65 & Figure 66.
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LMH6503
SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
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R2
510:
R1
510:
VS
14
+VIN
13
3
+
RG
180:
-VIN
VS/2
RF
1k:
1
COUT
0.1µF
12
LMH6503
6
8
R4 7
2k:
R3
2k:
C1
0.1µF
11
2
9
10
ROUT
50:
VOUT
VG
RANGE: ±1V FROM PIN 11
VOLTAGE (FOR VS = 10V)
Figure 65. AC Coupled Single Supply VGA
C1
0.1µF
R2
510:
R1
510:
VS
14
3
13
+
RG
160:
VS/2
RF
1k:
1
COUT
0.1µF
12
LMH6503
6
7
8
11
9
2
10
ROUT
50:
VOUT
VG
Figure 66. Transformer Coupled Single Supply VGA
OPERATING AT LOWER SUPPLY VOLTAGES
The LMH6503 is rated for operation down to 5V supplies (V+ - V−). There are some specifications shown for
operation at ±2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared
to ±5V operation, at lower supplies:
a)
VG range constricts. Referring to Figure 67, note that VG_MAX (VG voltage required to get maximum gain) is
0.5V (VS = ±2.5V) compared to 1.0V for VS = ±5V. At the same time, gain cut-off (VG_MIN) would shift to
−0.5V from - 1V with VS = ±5V.
Table 1 shows the approximate expressions for various VG voltages as a function of V-:
22
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LMH6503
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SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
Table 1. VG Definition Based on V−
VG
Definition
Expression (V)
VG_MIN
Gain Cut-off
0.2 x V−
VG_MID
AVMAX/2
0
VG_MAX
AVMAX
−0.2 x V−
b)
VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device
arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive).
Referring to Figure 67, note that with V+ = 2.5V, and V− = −4V, VG_LIMIT is approaching VG_MAX and already
"Max gain" is reduced by 1dB. This means that operating under these conditions has reduced the
maximum permissible voltage on VG to a level below what is needed to get Max gain. If supply voltages
are asymmetrical, reference Figure 67 and Figure 68 plots to make sure the region of operation is not
overly restricted by the "pinching" of VG_LIMIT, and VG_MAX curves.
c)
"Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced
(see Figure 43). In addition, there is the more drastic mechanism described in "b" above and shown in
Figure 67.
Similar plots for V+ = 5V operation are shown in Figure 68 for comparison and reference.
1.6
20.5
MAX GAIN
20
1.4
VG LIMIT
19
VG (V)
1
0.8
18.5
VG MAX
18
0.6
+
0.4
V = 2.5V
17.5
0.2
RF = 1k:
17
MAX GAIN (dB)
19.5
1.2
RG = 170:
0
-4.5
16.5
-4
-3.5
-3
-2.5
-2
-
V (V)
Figure 67. VG_MAX, VG_LIMIT, & Max-gain vs. V(V+ = 2.5V)
5
20.5
VG LIMIT
4.5
20.4
4
VG (V)
3.5
20.2
MAX GAIN
3
20.1
2.5
20
+
V = 5V
2
19.9
RF = 1k:
1.5
MAX GAIN (dB)
20.3
19.8
RG = 170:
1
19.7
0.5
19.6
VG MAX
19.5
0
-6
-5.5
-5
-4.5
-4
-3.5
-3
-
V (V)
Figure 68. VG_MAX, VG_LIMIT, & Max-gain vs. V(V+ = 5V)
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LMH6503
SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
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Application Circuits
FOUR-QUADRANT MULTIPLIER
Applications requiring multiplication, squaring or other non-linear functions can be implemented with fourquadrant multipliers. The LMH6503 implements a four-quadrant multiplier as illustrated in Figure 69:
Figure 69. Four Quadrant Multiplier
FREQUENCY SHAPING
Frequency shaping and bandwidth extension of the LMH6503 can be accomplished using parallel networks
connected across the RG ports. The network shown in the Figure 70 schematic will effectively extend the
LMH6503's bandwidth.
Figure 70. Frequency Shaping
2nd ORDER TUNABLE BANDPASS FILTER
The LMH6503 Variable-Gain Amplifier placed into a feedback loop provides signal processing function such as in
a 2nd order tunable bandpass filter. The center frequency of the 2nd order bandpass shown in Figure 71 is
adjusted through the use of the LMH6503's gain control voltage, VG. The integrators implemented with two
sections of a LMH6682, provide the coefficients for the transfer function.
24
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LMH6503
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SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
VO
VIN
s
= -
1
n
p = 1.72
s2 + s
RF
RY
1
CRB
p
1
+ 2 2
CRB C RY
pRB
,Q=
RY
, ZO =
p
CRY
Figure 71. Tunable Bandpass Filter
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LMH6503
SNOSA78E – OCTOBER 2003 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH6503MA
NRND
SOIC
D
14
55
TBD
Call TI
Call TI
-40 to 85
LMH6503MA
LMH6503MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH6503MA
LMH6503MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH6503MA
LMH6503MT
NRND
TSSOP
PW
14
94
TBD
Call TI
Call TI
-40 to 85
LMH65
03MT
LMH6503MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
03MT
LMH6503MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMH65
03MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMH6503MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMH6503MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH6503MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMH6503MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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