Low Cost, High Performance
Voltage Feedback, 325 MHz Amplifiers
AD8057/AD8058
FEATURES
Low Cost Single (AD8057) and Dual (AD8058)
High Speed
325 MHz –3 dB Bandwidth (G = +1)
1000 V/␮s Slew Rate
Gain Flatness 0.1 dB to 28 MHz
Low Noise
7 nV/√Hz
Low Power
5.4 mA/Amplifier Typical Supply Current @ 5 V
Low Distortion
–85 dBc @ 5 MHz, RL = 1 k⍀
Wide Supply Range from 3 V to 12 V
Small Packaging
AD8057 Available in SOIC-8 and SOT-23-5
AD8058 Available in SOIC-8 and MSOP
CONNECTION DIAGRAMS (TOP VIEW)
RT-5 (SOT-23-5)
AD8057
VOUT 1
5
R-8 (SOIC)
+VS
–VS 2
+IN 3
4
–IN
NC 1
8
NC
–IN 2
7
+VS
+IN 3
6
VOUT
5
NC
–VS 4
(Not to Scale)
AD8057
(Not to Scale)
NC = NO CONNECT
RM-8 (MSOP)
R-8 (SOIC)
APPLICATIONS
Imaging
DVD/CD
Photodiode Preamp
A-to-D Driver
Professional Cameras
Filters
OUT1
1
–IN1
AD8058
8
+VS
2
7
OUT2
+IN1
3
6
–IN2
–VS
4
5
+IN2
(Not to Scale)
GENERAL DESCRIPTION
The AD8057 (single) and AD8058 (dual) are very high performance amplifiers with a very low cost. The balance between
cost and performance make them ideal for many applications.
The AD8057 and AD8058 will reduce the need to qualify a
variety of specialty amplifiers.
5
The AD8057 and AD8058 are voltage feedback amplifiers with
the bandwidth and slew rate normally found in current feedback
amplifiers. The AD8057 and AD8058 are low power amplifiers
having low quiescent current and a wide supply range from 3 V
to 12 V. They have noise and distortion performance required
for high end video systems as well as dc performance parameters
rarely found in high speed amplifiers.
1
The AD8057 and AD8058 are available in standard SOIC
packaging as well as tiny SOT-23-5 (AD8057) and MSOP
(AD8058) packages. These amplifiers are available in the industrial temperature range of –40°C to +85°C.
4
3
GAIN (dB)
2
G = +1
0
–1
G = +5
–2
G = +2
–3
G = +10
–4
–5
1
100
10
FREQUENCY (MHz)
1000
Figure 1. Small Signal Frequency Response
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD8057/AD8058–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
SFDR
Third Order Intercept
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Overload Recovery
(@ TA = 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1,
unless otherwise noted.)
Conditions
Min
325
95
175
30
850
1150
30
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, VO = 2 V p-p, RL = 150 Ω
f = 5 MHz, VO = 2 V p-p
f = 5 MHz, G = +2
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
VIN = 200 mV p-p, G = +1
–85
–62
–68
–35
–60
7
0.7
0.01
0.02
0.15
0.01
30
dBc
dBc
dB
dBm
dB
nV/√Hz
pA/√Hz
%
%
Degree
Degree
ns
1
2.5
3
0.5
3.0
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current for AD8057
Quiescent Current for AD8058
Power Supply Rejection Ratio
Unit
G = +1, VO = 0.2 V p-p
G = –1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V Step, RL = 2 kΩ
G = +1, VO = 4 V Step, RL = 2 kΩ
G = +2, VO = 2 V Step
DC PERFORMANCE
Input Offset Voltage
Input Offset Current
Open-Loop Gain
AD8057/AD8058
Typ
Max
VO = ± 2.5 V, RL = 2 kΩ
VO = ± 2.5 V, RL = 150 Ω
5
2.5
± 0.75
50
50
55
52
10
2
+Input
RL = 1 kΩ
VCM = ± 2.5 V
–4.0
48
RL = 2 kΩ
RL = 150 Ω
30% Overshoot
+4.0
60
–4.0
+4.0
± 3.9
30
VS = ± 5 V to ± 1.5 V
54
± 5.0
6.0
14.0
59
7.5
15
mV
mV
µV/°C
µA
µA
µA
dB
dB
MΩ
pF
V
dB
V
V
pF
V
mA
mA
dB
Specifications subject to change without notice.
–2–
REV. B
AD8057/AD8058
SPECIFICATIONS
(@ TA = 25ⴗC, VS = 5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Conditions
Min
300
155
28
700
35
MHz
MHz
MHz
V/µs
ns
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = +2
f = 100 kHz
f = 100 kHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 1 kΩ
–75
–54
–60
7
0.7
0.05
0.05
0.10
0.02
dBc
dBc
dB
nV/√Hz
pA/√Hz
%
%
Degree
Degree
1
2.5
3
0.5
3.0
50
45
55
52
mV
mV
µV/°C
µA
µA
µA
dB
dB
48
10
2
± 0.9 to ± 3.4
60
MΩ
pF
V
dB
0.9 to 4.1
1.2 to 3.8
30
V
V
pF
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Capacitive Load Drive
5
2.5
0.75
VO = ± 1.25 V, RL = 2 kΩ to Midsupply
VO = ± 1.25 V, RL = 150 Ω to Midsupply
+Input
RL = 1 kΩ
VCM = ± 2.5 V
RL = 2 kΩ
RL = 150 Ω
30% Overshoot
POWER SUPPLY
Operating Range
Quiescent Current for AD8057
Quiescent Current for AD8058
Power Supply Rejection Ratio
54
Specifications subject to change without notice.
REV. B
Unit
G = +1, VO = 0.2 V p-p
G = +1, VO = 2 V p-p
VO = 0.2 V p-p
G = +1, VO = 2 V Step, RL = 2 kΩ
G = +2, VO = 2 V Step
DC PERFORMANCE
Input Offset Voltage
Input Offset Current
Open-Loop Gain
AD8057/AD8058
Typ
Max
–3–
5.0
5.4
13.5
58
7.0
14
V
mA
mA
dB
AD8057/AD8058
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
SOIC Package (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W
SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 4.0 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the
AD8057/AD8058 is limited by the associated rise in junction
temperature. Exceeding a junction temperature of 175°C for an
extended period can result in device failure. While the AD8057/
AD8058 is internally short-circuit protected, this may not be
sufficient to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
TJ = 150ⴗC
MAXIMUM POWER DISSIPATION (W)
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead SOIC Package: ␪JA = 160°C/W
5-Lead SOT-23-5 Package: ␪JA = 240°C/W
8-Lead MSOP Package: ␪JA = 200°C/W
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
SOT-23-5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (ⴗC)
70
80
90
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
AD8057AR
AD8057ACHIPS
AD8057AR-REEL
AD8057AR-REEL7
AD8057ART-R2
AD8057ART-REEL
AD8057ART-REEL7
AD8057ARTZ-REEL7*
AD8058AR
AD8058ACHIPS
AD8058AR-REEL
AD8058AR-REEL7
AD8058ARZ-REEL7*
AD8058ARM
AD8058ARM-REEL
AD8058ARM-REEL7
AD8058ARMZ-REEL7*
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Narrow Body SOIC
Die
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
5-Lead SOT-23
5-Lead SOT-23, 13" Reel
5-Lead SOT-23, 7" Reel
5-Lead SOT-23, 7" Reel
8-Lead Narrow Body SOIC
Die
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
8-Lead SOIC, 7" Reel
8-Lead MSOP
8-Lead MSOP, 13" Reel
8-Lead MSOP, 7" Reel
8-Lead MSOP, 7" Reel
R-8
Waffle Pak
R-8
R-8
RT-5
RT-5
RT-5
RT-5
R-8
Waffle Pak
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
Standard
N/A
Standard
Standard
H7A
H7A
H7A
H7A
Standard
N/A
Standard
Standard
Standard
H8A
H8A
H8A
H8A
*Lead free
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8057/AD8058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
Typical Performance Characteristics–AD8057/AD8058
4.5
4.0
0.0
–1.5V SWING RL = 150⍀
(+) OUTPUT
VOLTAGE
–0.5
–1.0
–2.5V SWING RL = 150⍀
–1.5
ABS (–)
OUTPUT
3.0
–2.0
2.5
VOLTS
OUTPUT VOLTAGE (V)
3.5
2.0
–2.5
–3.0
1.5
–3.5
1.0
–4.0
0.5
0
10
–5V SWING RL = 150⍀
–4.5
100
–5.0
–40 –30 –20 –10
100k
1k
10k
LOAD RESISTANCE (⍀)
TPC 1. Output Swing vs. Load Resistance
0
10 20 30 40
TEMPERATURE (ⴗC)
50
60
70
80 85
TPC 4. Negative Output Voltage Swing vs. Temperature
6
–3.0
–3.5
4
–4.0
2
–5.0
–I SUPPLY @ ⴞ1.5V
VOS (mV)
–ISUPPLY (mA)
–4.5
–5.5
–6.0
–ISUPPLY @ ⴞ5V
VOS @ ⴞ1.5V
0
VOS @ ⴞ5V
–2
–6.5
–7.0
–4
–7.5
–8.0
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE ( C)
50
60
70
–6
–40 –30 –20 –10
80 85
0
10 20 30 40
TEMPERATURE (ⴗC)
50
60
70
80
TPC 5. VOS vs. Temperature
TPC 2. –ISUPPLY vs. Temperature
3.5
5.0
4.5
3.0
+5V SWING RL = 150⍀
AVOL @ ⴞ5V
4.0
2.5
AVOL (mV/V)
3.5
VOLTS
3.0
2.5
2.0
+2.5V SWING RL = 150⍀
2.0
AVOL @ ⴞ2.5V
1.5
1.0
1.5
1.0
0.5
+1.5V SWING RL = 150⍀
0.5
0.0
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (ⴗC)
50
60
70
0
–40 –30 –20 –10
80 85
10 20 30 40
TEMPERATURE (ⴗC)
50
60
70
80 85
TPC 6. Open-Loop Gain vs. Temperature
TPC 3. Positive Output Voltage Swing vs. Temperature
REV. B
0
–5–
AD8057/AD8058
0.00
+VS 4.7␮F
–0.10
0.01␮F
–0.20
HP8130A
PULSE
GENERATOR
TR/TF = 1ns
IB (␮A)
–0.30
–0.40
0.001␮F
VIN
50⍀
VOUT
AD8057/58
4.7␮F
+IB @ ⴞ5V
–0.50
–0.60
–0.70
+IB @ ⴞ2.5V
–I B @ ⴞ2.5V
–I B @ ⴞ5V
1k⍀
0.01␮F
0.001␮F
+IB @ ⴞ1.5V
–I B @ ⴞ1.5V
–VS
–0.80
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE ( C)
50
60
70
80 85
TPC 10. Test Circuit G = +1, RL = 1 kΩ for TPCs 11 and 12
TPC 7. Input Bias Current vs. Temperature
4
100mV
3
PSRR (mV/V)
PSRR @ ⴞ1.5V ⴞ5V
20mV/
DIV
2
1
–100mV
0
–40 –30 –20 –10
4ns/DIV
0
10 20 30 40
TEMPERATURE ( C)
50
60
70
80 85
TPC 11. Small Signal Step Response G = +1,
R L = 1 k Ω , VS = ± 5 V
TPC 8. PSRR vs. Temperature
0
5V
–10
PSRR (dB)
–20
–PSRR VS = ⴞ2.5V
1V/DIV
–30
+PSRR VS = ⴞ2.5V
–40
–50
–5V
4ns/DIV
–60
0.1
1
10
FREQUENCY (MHz)
100
1000
TPC 12. Large Signal Step Response G = +1,
RL = 1 kΩ, VS = ± 5.0 V
TPC 9. ± PSRR vs. Frequency
–6–
REV. B
AD8057/AD8058
5
4
1k⍀
3
+VS 4.7␮F
2
HP8130A
PULSE
GENERATOR
TR/TF = 1ns
0.001␮F
VIN 1k⍀
50⍀
GAIN (dB)
0.01␮F
VOUT
AD8057/58
4.7␮F
1
G = +1
0
–1
G = +5
–2
1k⍀
G = +2
–3
0.01␮F
G = +10
–4
0.001␮F
–5
100
10
FREQUENCY (MHz)
1
–VS
TPC 13. Test Circuit G = –1, RL = 1 kΩ for TPCs 14 and 15
1000
TPC 16. Small Signal Frequency Response,
VOUT = 0.2 V p-p
5
4
100mV
3
GAIN (dB)
2
20mV/
DIV
0V
1
G = +1
0
G = +5
–1
–2
G = +2
–3
G = +10
–4
–5
–100mV
1
10
100
FREQUENCY (MHz)
4ns/DIV
TPC 14. Small Signal Step Response G = –1, RL = 1 kΩ
1000
TPC 17. Large Signal Frequency Response, VOUT = 2 V p-p
5
4
5V
3
GAIN (dB)
2
1V/DIV
1
G = –2
G = –1
0
–1
–2
G = –5
–3
G = –10
–4
–5
–5V
4ns/DIV
TPC 15. Large Signal Step Response G = –1, RL = 1 kΩ
REV. B
1
10
100
FREQUENCY (MHz)
1000
TPC 18. Large Signal Frequency Response
–7–
AD8057/AD8058
5.0
0.5
VOUT = 0.2V
G = +2
RL = 1.0k⍀
RF = 1.0k⍀
0.3
4.5
RISE TIME AND FALL TIME (ns)
0.4
0.2
GAIN (dB)
0.1
0.0
–0.1
–0.2
–0.3
3.0
2.5
2.0
FALL TIME
1.5
RISE TIME
1.0
0.0
100
10
FREQUENCY (MHz)
1
1000
0
1
2
VOUT (V p-p)
3
4
TPC 22. Rise Time and Fall Time vs. VOUT, G = +1,
RL = 1 k Ω, R F = 0 Ω
TPC 19. 0.1 dB Flatness G = +2
5
–50
RISE TIME AND FALL TIME (ns)
–60
DISTORTION (dBc)
3.5
0.5
–0.4
–0.5
4.0
THD
–70
SECOND
–80
THIRD
–90
–100
4
3
RISE TIME
2
FALL TIME
1
0
–110
0.1
1
10
FREQUENCY (MHz)
100
TPC 20. Distortion vs. Frequency, RL = 150 Ω
0
2
VOUT (V p-p)
1
3
4
TPC 23. Rise Time and Fall Time vs. VOUT, G = +2,
RL = 100 Ω, RF = 402 Ω
–40
VOUT = –1V TO + 1V OR +1V TO –1V
G = +2
RL = 100⍀/1k⍀
0.4%
0.3%
DISTORTION (dBc)
–50
0.2%
20MHz
0.1%
–60
0.0%
–0.1%
5MHz
–0.2%
–70
–0.3%
–0.4%
–80
0.0
0
0.4
0.8
1.2
1.6
2.0
2.4
VOUT (V p-p)
2.8
3.2
3.6
4.0
TPC 21. Distortion vs. VOUT @ 20 MHz, 5 MHz,
RL = 150 Ω, VS = ± 5.0 V
10 20
30 40 50 60
TIME (ns)
TPC 24. Settling Time
–8–
REV. B
AD8057/AD8058
INPUT SIGNAL
1.8V
VS = ⴞ2.5V
RL = 1k⍀
G = +1
OUTPUT SIGNAL 1.7V
2.5V
VS = ⴞ2.5V
R1 = 1k⍀
G = +4
OUTPUT RESPONSE
500mV/
DIV
200mV/
DIV
INPUT SIGNAL = 0.6V
0V
20ns/DIV
20ns/DIV
TPC 25. Input Overload Recovery, VS = ± 2.5 V
TPC 28. Output Overload Recovery, VS = ± 2.5 V
4.5V
VS = ⴞ5.0V
RL = 1k⍀
G = +1
VS = ⴞ5.0V
R1 = 1k⍀
G = +4
INPUT SIGNAL 5V
5.0V
1V/DIV
500mV/
DIV
OUTPUT SIGNAL = 4.0V
0V
20ns/DIV
20ns/DIV
TPC 26. Output Overload Recovery, VS = ± 5.0 V
37ns
TPC 29. Output Overload Recovery, VS = ± 5.0 V
0
0
–10
–20
CROSSTALK (dB)
CMRR (dB)
–20
–30
–40
–40
–60
SIDE B DRIVEN
–80
–50
SIDE A DRIVEN
–100
–60
–70
0.1
1
10
FREQUENCY (MHz)
–120
0.1
100
TPC 27. CMRR vs. Frequency
REV. B
1
10
FREQUENCY (MHz)
100
TPC 30. Crosstalk (Output-to-Output) vs. Frequency
–9–
AD8057/AD8058
0.015
DIFFERENTIAL GAIN (%)
0.00 –0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.00 –0.00 –0.00 –0.00
0.010
0.01
–0.01
0.000
–0.02
–0.005
–0.03
–0.010
–0.04
–0.015
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
VS = +5V
RL = 150⍀
0.00
VS = ⴞ5.0V
RL = 150⍀
0.005
DIFFERENTIAL GAIN (%)
0.00 –0.00 –0.00–0.01 –0.01 –0.01 –0.01 –0.01 –0.02 –0.03 –0.04
–0.05
DIFFERENTIAL PHASE (Degrees)
0.00 0.00 0.02 0.03 0.05 0.07 0.09 0.10 0.11 0.12 0.13
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
VS = ⴞ5.0V
RL = 150⍀
1st
2nd 3rd
4th
5th
6th
7th
8th
9th
10th 11th
DIFFERENTIAL PHASE (Degrees)
0.00 0.01 0.03 0.05 0.07 0.09 0.11 0.12 0.12 0.13 0.13
VS = +5V
RL = 150⍀
1st
2nd 3rd
4th
a.
0.015
6th
7th
8th
9th
10th 11th
a.
DIFFERENTIAL GAIN (%)
0.00 0.00 0.00 0.01 0.01 0.00 0.00 0.00 –0.00 –0.01 –0.01
0.01
VS = ⴞ5.0V
RL = 1k⍀
0.010
0.005
DIFFERENTIAL GAIN (%)
0.00 0.01 –0.00–0.01 –0.01 –0.01 –0.02 –0.02 –0.03 –0.04 –0.05
VS = +5V
RL = 1k⍀
0.00
–0.01
0.000
–0.02
–0.005
–0.03
–0.010
–0.04
–0.015
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
5th
–0.05
DIFFERENTIAL PHASE (Degrees)
0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.01 –0.01 –0.01 –0.01 –0.01`
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
VS = ⴞ5.0V
RL = 1k⍀
1st
2nd 3rd
4th
5th
6th
7th
8th
9th
10th 11th
DIFFERENTIAL PHASE (Degrees)
0.00 –0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.00 –0.01 –0.01 –0.02
VS = +5V
RL = 1k⍀
1st
2nd 3rd
4th
5th
6th
7th
8th
9th
10th 11th
b.
b.
TPC 31. Differential Gain and Differential Phase
One Back Terminated Load (150 Ω) (Video Op
Amps Only)
TPC 33. Differential Gain and Differential Phase,
a. RL = 150 Ω, b. RL = 1 kΩ
100
80
90
60
45
40
0
20
1
0
–45
–90
0.01
10
VNOISE (nV/ Hz)
135
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
180
0.1
1
10
FREQUENCY (MHz)
100
–20
1000
0.1
TPC 32. Open-Loop Gain and Phase vs. Frequency
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
TPC 34. Voltage Noise vs. Frequency
–10–
REV. B
AD8057/AD8058
100
10
10
ZOUT (⍀)
INOISE (pA/ Hz)
100
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0.1
0.1
100M
TPC 35. Current Noise vs. Frequency
1
10
FREQUENCY (MHz)
1000
100
TPC 36. Output Impedance vs. Frequency
APPLICATIONS
Driving Capacitive Loads
Table I. Recommended Value for Resistors R S, RF, RG vs.
Capacitive Load, CL, Which Results in 30% Overshoot
When driving a capacitive load, most op amps will exhibit overshoot in their pulse response.
Figure 3 shows the relationship between the capacitive load
that results in 30% overshoot and the closed-loop gain of an
AD8058. It can be seen that, under the Gain = +2 condition,
the device is stable with capacitive loads of up to 69 pF.
In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor, RS, can
be added between the op amp output and the load capacitor,
CL, as shown in Figure 4.
Gain
RF
(Ω)
RG
(Ω)
CL w/RS = 0 Ω
(pF)
CL w/RS = 2.4 Ω
(pF)
1
2
3
4
5
10
100
100
100
100
100
100
100
50
33.2
25
11
11
51
104
186
245
870
13
69
153
270
500
1580
RF
For the setup shown in Figure 4, the relationship between RS
and CL was empirically derived and is shown in Table I.
+2.5V
0.1␮F
500
10␮F
RG
400
RS
AD8058
VIN = 200mV p-p
FET PROBE
VOUT
CL
50k⍀
CL (pF)
300
0.1␮F
10␮F
200
–2.5V
RS = 2.4⍀
Figure 4. Capacitive Load Drive Circuit
100
RS = 0⍀
+ OVERSHOOT
29.0%
0
1
2
3
CLOSED-LOOP GAIN
4
5
200mV
100mV
Figure 3. Capacitive Load Drive vs. Closed-Loop Gain
–100mV
–200mV
100mV/DIV
50ns/DIV
Figure 5. Typical Pulse Response with CL = 65 pF,
Gain = +2, and VS = ± 2.5 V
REV. B
–11–
AD8057/AD8058
Video Filter
Differential A-to-D Driver
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these
frequencies from the video signal.
As system supply voltages are dropping, many ADCs provide
differential analog inputs to increase the dynamic range of the
input signal while still operating on a low supply voltage. Differential driving can also reduce second and other even-order
distortion products.
Figure 6 shows a circuit that uses an AD8057 to create a single
5 V supply, 3-pole Sallen-Key filter. This circuit uses a single
RC pole in front of a standard 2-pole active section. To shift the
dc operating point to midsupply, ac coupling is provided by R4,
R5, and C4.
C2
680pF
RF
1k⍀
+5V
+5V
R1
200⍀
R2
499⍀
R3
49.9⍀
C1
100pF
C4
0.1␮F
C3
36pF
R4
10k⍀
2
3
0.1␮F
+
10␮F
7
AD8057
6
4
R5
10k⍀
Analog Devices offers an assortment of 12- and 14-bit high
speed converters that have differential inputs and can be run
from a single 5 V supply. These include the AD9220, AD9221,
AD9223, AD9224, and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.
Op amp architectures that require upwards of 2 V of headroom
at the output have significant problems when trying to drive
such ADCs while operating with a 5 V positive supply. The low
headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of ADCs.
The AD8058 can be used to make a dc-coupled, single-endedto-differential driver for one of these ADCs. Figure 8 is a
schematic of such a circuit for driving an AD9225, 12-bit,
25 MSPS ADC.
1k⍀
+5V
Figure 6. Low-Pass Filter for Video
Figure 7 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz, so it passes the video band with little
attenuation. The rejection at 27 MHz is 42 dB, which provides
more than a factor of 100 in suppression of the clock components at this frequency.
0.1␮F
0.1␮F
1k⍀
3
VIN
1k⍀
0V
+5V
+
10␮F
8
AD8058
REF
50⍀
1
VINA
2
1k⍀
AD9225
10
1k⍀
6
1k⍀
5
0
–10
LOG MAGNITUDE (dB)
+2.5V
+
10␮F
1k⍀
AD8058
50⍀
7
VINB
4
–20
0.1␮F
–30
–5V
–40
10␮F
+
1k⍀
–50
Figure 8. Schematic Circuit for Driving AD9225
–60
In this circuit, one of the op amps is configured in the inverting
mode, while the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of +2. The inverting op amp is configured for a
gain of –1, while the noninverting op amp is configured for a
gain of +2. Each of these produces a noise gain of +2, which is
only determined by the inverse of the feedback ratio. The input
signal to the noninverting op amp is divided by 2 in order to
normalize its level and make it equal to the inverting output.
–70
–80
–90
100k
1M
10M
FREQUENCY (Hz)
Figure 7. Video Filter Response
100M
–12–
REV. B
AD8057/AD8058
For 0 V input, the outputs of the op amps want to be at 2.5 V,
which is the midsupply level of the ADCs. This is accomplished by
first taking the 2.5 V reference output of the ADC and dividing it by two by a pair of 1 kΩ resistors. The resulting 1.25 V is
applied to each op amp’s positive input. This voltage is then
multiplied by the gain of +2 of the op amps to provide a 2.5 V
level at each output.
The assumption for this circuit is that the input signal is bipolar
with respect to ground and the circuit must be dc-coupled. This
implies the existence of a negative supply elsewhere in the system. This circuit uses –5 V as the negative supply for the AD8058.
If the AD8058 negative supply were tied to ground, there would
be a problem at the input of the noninverting op amp. The
input common-mode voltage can only go to within 1 V of the
negative rail. Since this circuit requires that the positive inputs
operate with a 1.25 V bias, there is not enough room to swing
this voltage in the negative direction. The inverting stage does
REV. B
not have this problem because its common-mode input voltage
remains fixed at 1.25 V. If dc coupling is not required, various
ac coupling techniques can be used to eliminate this problem.
Layout
The AD8057 and AD8058 are high speed op amps and should
be used in a board layout that follows standard high speed design
rules. All the signal traces should be as short and direct as possible. In particular, the parasitic capacitance on the inverting
input of each device should be kept to a minimum to avoid
excessive peaking and other undesirable performance.
The power supplies should be bypassed very close to the power
pins of the package with 0.1 µF in parallel with a larger, approximately 10 µF tantalum capacitor. These capacitors should be
connected to a ground plane that is either on an inner layer or
fills the area of the board that is not used for other signals.
–13–
AD8057/AD8058
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
3.00
BSC
8
5
4.00 (0.1574)
3.80 (0.1497)
4.90
BSC
3.00
BSC
1
8
5
1
4
4
1.27 (0.0500)
BSC
PIN 1
0.65 BSC
0.25 (0.0098)
0.10 (0.0040)
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
6.20 (0.2440)
5.80 (0.2284)
8ⴗ
0ⴗ
0.23
0.08
COPLANARITY
SEATING
0.10
PLANE
0.80
0.60
0.40
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
PIN 1
0.95 BSC
1.30
1.15
0.90
1.90
BSC
1.45 MAX
0.15 MAX
0.50
0.30
SEATING
PLANE
0.22
0.08
10ⴗ
5ⴗ
0ⴗ
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
–14–
REV. B
AD8057/AD8058
Revision History
Location
Page
8/03—Data Sheet changed from REV. A to REV. B.
Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. B
–15–
–16–
C01064–0–8/03(B)