430
IEEE
JOURNAL
A CMOS Four-Quadrant
KLAAS
BULT
AND HANS
OF SOLID-STATE
Analog
WALLINGA,
first
swing
has a linearity
of 36 percent
1 MHz.
an
better
than 0.14 percent
of the supply
current
The second version has floating
output
current
bandwidth
from
swing
of
for
an orrtpnt
and a bandwidth
inputs, a linearity
40 percent
of
the
supply
current
L+-
a
Fig.
F
INTRODUCTION
OUR-QUADRANT
building
filters,
pliers
blocks
many
frequency-shifters,
have received
circuits
technology,
are very useful
such
and modulators.
severe attention
[1]. Even in CMOS
Analog
in bipolar
multipliers
K=p
as adaptive
multipliers
Their
circuit
have been reported
bipolar
circuit
paper
we report
approach
concept
is based
described
in [3] and [4]. In
by Gilbert
on a new approach
characteristics
[1]. In
W=
channel
(Section
analysis
is presented.
III).
Then
Section
of MOS
in Section
V describes
of the multiplier
with
and
Consider the circuit of Fig. 1. The gate–source voltages
of the two identical
MOS transistors
Ml
and M2 are,
respectively,
Vg,l and P’&2. The sum of the gate–source
voltages
is kept at a constant
voltage
V2:
transistors
Furthermore
ldl = K(Vg,l – ~)2
operlinear
two of
IV
a distortion
the design of a
second
version
floating
inputs
Section
VI shows the results of the measurements.
(2)
Vg,l + vg,2 = V2.
and
circuits
results in a two-quadrant
multiplier,
and
duplicating
this circuit results in the four-quadrant
multiplier
width,
per unit area,
L = channel length.
this
for a four-quadrant
ated in saturation.
First a novel voltage-controlled
V– 1 convertor is explained (Section II). Combining
these
again
mobility,
on the well-known
analog multiplier
which has been realized in CMOS technology. This multiplier
relies on the quadratic
drain-current/gate-voltage
The basic circuit.
COX= gate oxide capacitance
technology
using (lateral)
[5] and [6] four-quadrant
multipliers
using switched-capacitor techniques
have been described.
A continuous-time
CMOS multiplier
has been presented by Soo and Meyer
[7].
1.
W/L,
COX
p = carrier
multi-
bipolar transistors have been reported [2]. Until now only a
few CMOS multiplier
designs have been published. Singlequadrant
V2
with
analog multipliers
in
1986
t-
M1
dc to above 4.5 MHz.
I.
3, JUNE
M2
at
and
NO.
l&2
idl
dc to
of 0.4 percent
SC-21,
MEMBER, IEEE
current
from
VOL.
Multiplier
,4Mrad
—A new circuit configuration for an MOS four-quadrant
analog multiplier
circuit is presented. It is based on the square-law
characteristics of the MOS transistor. Two versions have been realized.
The
CIRCUITS,
1~2 = K(V’,2
Applying
output
A2 – B2 = (A + B)(A
current
difference
(3)
– @2.
– B)
( 1~1 – IJ
to
(2) and (3), the
may be written
as
and
ldl–1d2=
K(V2–2~)(Vg,l
–Vg,J).
(4)
Because
II.
THE BASIC VOLTAGE-CONTROLLED
V–
In this section
I
V-8.1– V’&=
CONVERTOR
all devices have the same geometry
operate in the saturation
characteristic
is assumed
Id=
region.
The
simple
and
square-law
we may, for constant
(Idl – 1d2) is linearly
V2, conclude that the output current
dependent on P’g,l or V,,, (only one
of the two parameters
K(vg,
–~)2
(1)
Manuscript received December 2, 1985: revised March 11, 1986. This
work 1spart of a researchprogram of the Dutch Foundation for Fundamental Researchon Matter (FOM).
The authors are with the Department of Electrical Engineering, IC
Technology and Electronics Group, Twente University of Technology,
7500 AE Enschede,The Netherlands.
IEEE Log Number 8608520.
0018 -9200/86/0600-0430$01
tension
transistor
of
the
(5)
V2 – 2V3.2 = 2vg.1 – V2
can be chosen independently).
circuit
in
Fig.
1 with
another
Ex-
identical
M3 as shown in Fig. 2 enables us to control
V~,2
via F(..,3.Because M2 and M3 have the same drain current
and both devices have the same geometry, the gate–source
voltages Vg,2 and Vg,j are equal:
vg,2 = vgJ3 = Vin.
.00 01986
IEEE
(6)
BULT
AND
CMOS
WALLINGA:
FOUR-QUADRANT
Idl
ANALOG
431
“MULTIPLIER
!&j
Itjz
M
M2
V2
t---
Ml
M3
V,n
t--
Fig.
2.
The voltage-controlled
M21
V– I convertor.
m
Ml~
M31
IR
iL
t
Substitution
from
the
relationship
factor
term
( Vz – 2 ~)V2,
be controlled
it is required
the saturation
square-law
tion
and mobility
(7)
(7)
shows
proximation,
region,
by
means
of
proper
channel-length
from
the
modula-
reduction.
modulation causes the drain current to
the drain voltage. In first-order
apby
h,,,.,))
~(bs -
(12)
with
operate in
I d,sat
i.e.,
=
K(vg. – ~)2
vd,,,,,= (Vg,- U)
1
A=z/a.
and
v2>2~n–~.
(8)
Substitution
III.
Equation
THE MULTIPLIER
(7) may be rewritten
1~1 _ Id2 = K(VJ
Id=zqvg, –~)2+AKvd. (vg,–F02
a one-quadrant
tion. The first term, however, is a nonlinear
The
multiplica-
function
3 in which
terminals.
the same voltage
The input
respectively.
Now
circuit
voltages
the
of the
IL–lR=2K(v2
This represents
to both
V2
Vi. are terlrned VI and V{,
output
may be written
is applied
current
difference
of
the
(lo)
–2~)(v(–17J.
multiplier.
Note
the disap-
pearance of the nonlinear quadratic term (of V2 and of the
this
offset term for the VI input. By again duplicating
circuit and cross coupling the output currents (Fig. 4), a
four-quadrant
multiplier
is obtained. Current mirrors have
been added
to obtain
a single-ended
output.
The output
is now given by
term for the V2 input
term
is the well-known
drain
(11)
VI).
has disappeared
too.
and wanted
(13)
quadratic
output
current.
The
second
term
is quadratic
in
(Vg, – ~) but also depends cm Vd~.
The effect
of channel-length
by using long-channel
the
effect
of
of
the
modulation
MOS transistors,
channel-length
multiplier
can be reduced
Before
modulation
we will
going into
on the perfor-
consider
the mobility
reduction.
b) Mobility
modeled by
reduction
p
in
=%/(1+
an MOS
transistor
w,. -0)
with
p ~ = zero field mobility,
O=
1.”, = 2K(V2 –v;)(v/–
The offset
first
- Pj’.
term. The last term is a third-order
term which will cause
first and third harmonics of the input gate voltage in the
mance
as
a two-quadrant
- y(vg,
(9)
terminal voltage Vz and the second and third term turn up
as offset terms. Duplication
of the circuit of Fig. 2 and
cross coupling of the output currents results in the circuit
of Fig.
of these terms in (12) yields
as
_ 2~V2 + 4~Vin _ 2V2Vin) .
The last term of (9) represents
current
of (l):
Id= L,.,(I+
Vin> J(
overall
effects causing deviations
behavior
this may be modeled
a linear
Vz,, For
that all three transistors
multiplier
SECOND-ORDER EFFECTS
a) Channel-length
be dependent
on
_21~in).
Four-quadrant
are two major
ideal
( Idl – Idz) and Vi.. The conversion
between
can
operation
There
multiplier
Idz = K(V2 –2~)(Vz
4,
IV.
of (6) and (5) into (4) yields
Idl–
Apart
Two-quadrant
I
Fig.
Vi
3.
y’
I
w
Fig.
I
l/(dOx” Ec,),
dOx = oxide thickness,
EC, = critical
field.
and
may
be
(14)
432
IEEE
The
mobility
and
may
means
reduction
have
a
deviation
ranging
from
the
of
use
Id=
ranging
from
1 to
(14),
Ko(vg,
parameter
values
20
(1)
the
–~)2[1–
be
0.01
for
1-V
V-1.
This
of
~
change
in
V,,..
into
a Taylor
–fi)+e’(vg,
OF SOLID-STATE
dependent
0.25
value
developed
e(vg,
to
nominal
percent
may
d is process
from
JOURNAL
in
CIRCUITS,
VOL.
SC-21,
NO.
3, JUNE
1986
Q
M2
t--
(1)
Ml
With
series
V*
-~)2
-@(vg.
-@3.]
(15)
Fig.
5.
The voltage-controlled
V– I convertor with independent
of the dc levels of both inputs.
control
with
KO = PO”COX.W/L.
For
6( Vg, – F() <1,
portant.
higher
order
terms
As r3 is a process-dependent
be made small by optimizing
The following
uration
of Fig.
this analysis,
analysis
1
the geometries
matching
I
1
‘Vdd
less imit cannot
of the devices.
shows that in the circuit
4 some of the distortion
ideal
become
parameter
r
1
config-
terms cancel.
of the transistors
In
lout
is assumed
of the gate–source
and Id is supposed to be a function
voltage only. The second term in (13) is made small by
p_*r
,Y(
using long devices.
Irrespective
of the origins of the deviations
from the
ideal square–law
characteristic,
one can develop a Taylor
series for the expression
of the gate–source
Id=
of the drain
current
II
,A -
as a function
I
Fig.
6.
Four-quadrant
–~)+a2(V~,
above, channel–length
–~)2
+a3(v~,
the following
-@3+
].
(16)
independent
common-mode
and
differential
If mobility
of distortion,
reduction
by comparison
a2=l
Vld{2a2
that with
current
the aforemen-
10Ut of the circuit
This
means
purely
voltages
differential
VIC and
input
–/33
(20)
etc.
important
distortion
terms
indicates
the order
of magnitude
in
to
of the distor-
V1C)3)
V.
THE
MULTIPLIER
WITH
FLOATING
INPUTS
(V2C– VIC)}
–VIC)}].
voltages
V2C are constant
(18)
the common-mode
and the terms
between braces are constant. In that
for IOU, may be abbreviated
to
1.”, =
the most
(j2
tion.
VI,)
V1C)2+20a5(V2C–
that
A disadvantage
of the circuit
of
common-mode
voltage of the inputs
bias voltages.
For
0,1, ..0 ) in (16) can be
(19), i.e., C2. V~~. V2d and C3oV~~. Vl~, are proportional
92, which
+6a3(V2C–
=
as=
up to the fifth-order
as
+V~~. V2~. {a4+5a,(V2C
a4
(17)
calculation
{a4+5a5.
is geometry
a3=—(j
(V2 – vJ)/2.
the output
of Fig. 4 can be written
+V2j-V1~.
ai (i=
v2c=(v2+v’’-2~2/2
of Id it can be shown
however,
serious cause of distor-
with (15). This results in
aO=al=O
assumptions,
+12a4(V2C–
inputs.
is assumed to be the only origin
the constants
vlc=(vl+v(–2~)/2
a straightforward
10U,= KO[V2d.
.ss
can be reduced by using
reduction,
and is a much more
determined
V,d=
tioned
with floating
modulation
Vld = (Vl – v;)/2
expansion
multiplier
long devices. The mobility
tion.
With
I
voltage
KO[aO+al(V~$
We define
voltages:
L
I
in (18)
case the expression
c1v2d.vld+ C,.v:d.vld + c3.v:d.v2d.
(19)
From (18) it becomes clear that only fourth and @gher
order terms in (16) give rise to distortion.
As mentioned
duced
A way to circumvent
in this section.
three transistors
Fig. 4 is that the
are simultaneously
this problem
is intro-
Fig. 5 shows again the sqbcircuit
of
as shown in Fig. 2, but with one modifica-
tion: the sources of Ml and M3 are disconnected. .This
does not infh.ience the function of the circuit: (2)-(9) still
hold for this version. The result, however, is independent
control over the common-mode
levels of both inputs. The
next step is to quadruple this circuit in the same way as in
the circuit
of Fig. 4 and to connect
the common
sources to
BULT
AND
WALLINGA
Fig.
CMOS
:
7.
FOUR-QUADRANT
Die photograph
of the circuit
current
sources
mirrors
have been added to obtain
of Fig. 4.
Fig. 8.
with
Die photograph
of the circuit
of Fig. 6
current
a single-ended
difference
of the transistors
433
MULTIPLIER
as shown in Fig. 6. Furthermore,
Fig. 6 shows another
4: the drains
ANALOG
output.
the circuit
of Fig.
at the Vz input
are con-
nected to Vdd instead of to the output current mirrors. As
is seen in Fig. 4, the branches with M31 and .M32 conduct
the same current
equal.
because their
However,
the currents
they are connected
holds
for
currents
the
the
drained
multiplier
current
to the final
of noise.
with
is one restriction:
voltages
which
We
As
these
signal they
is advantageous
now
independently
conditions
The same
M34.
output
are
cancel as
mirrors.
i1433 and
to the supply,
discrimination
quadrant
There
with
do not contribute
are directly
for
to opposite
branches
gate–source
in these branches
have
a four-
floating
inputs.
Fig.
9,
Multiplication
of two sine waves of the same frequency
of Fig. 4).
(circuit
(8) have to be fulfilled
for each of the basic subcircuits of three transistors.
Unfortunately,
for this second version of the multiplier,
[8], [9]. As this process has isolated n-wells, both circuits
have been realized with p-channel transistors because the
the terms between
distortion
analysis
body effect may be reduced by connecting
the well substrates to the sources of the p-channel MOST’S. N-channel
braces in (18) are not constant and the
becomes much more complicated.
This
is due to the fact that now V2C and VIC are not referenced
to ground
distortion
but to the common-source
nodes. A detailed
analysis is beyond the scope of this paper and
we refer to the experimental
results in the next section.
transistors
have only been used as current
obtain a single-ended output current.
The circuit
of Fig. 4 was processed with
voltage
oxide
VI.
Both versions
realized.
circuits
in the
Figs.
EXPERIMENTAL RESULTS
of the multiplier
(Figs. 4 and 6) have been
7 and 8 show the die photographs
of the
of Figs. 4 and 6. These IC’S have been fabricated
IC processing
facility
of Twentc
TJniversity
of
Technology
using
a retrograde
twin-well
CMOS
process
of
– 0.6 V for
thickness
the p-channel
of 50 nm. All
mirrors
to
a threshold
transistors
and an
devices of this design have
W= 120 pm, L =10 pm. The activp
the same geometry:
area, including
current mirrors, is about 86400 pm2.
Fig. 9 shows the performance
of the multiplier
as a
frequency
doubler;
the input signals are two in-phase
l-kHz sine waves of 3.5 Vp _P. The output is a sine wave of
twice the input
signal frequency
mVP _ ~ measured
and has a magnitude
of 44
over a 100-0 load resistor, i.e., an output
434
IEEE
JOURNAL
OF SOLID-STATE
%
CIRCUITS,
VOL.
“SC-21,
NO.
3, JUNE
1986
J
THD
.5.
.4.
/
,3.
i
.2
/;
I
/“
“Iz_w!?@’”pp’,
50
Fig.
Fig.
Modulated
10.
triangle
wave (circuit
12.
The
efficiency
100%
total harmonic
distortion
as a function
of the current
IOUt,P_ ~ /I,~PPIY (circuit of Fig. 4). l,UPPIY = 1.65 mA.
of Fig. 4).
.
.6.
.50/
.4/
.3-
./”
%...,.”’
.2.
“’t--_!3’-s/’s.
f’ply
10
Fig.
Fig.
11.
Spectral
contents
of a sine wave at the output
of Fig. 4.
of the multiplier
13. The
efficiency
of
0.44
mA ~_ ~. The
total
supply
current
was
2.0 mA.
Fig. 10 shows the multiplier
tor. A 3.5-VP_P triangle
performance
wave was applied
and a 3.8-VP_ ~ sine wave was applied
shows the spectrum
current
of the output
of magnitude
was
second and
fundamental.
The total
third
harmonics
to the Vz input.
signal with a l-kHz
harmonic
distortion
are both
circuit
of
Fig.
load
The
sine
output
resistor.
60 dB below
was measured
6 was realized
as a function
of
the current
of Fig. 6). I,UPPIY= 1.88 mA.
of this circuit
distortion
was from
dc to
as a function
of
is shown in Fig. 13. A dc voltage
to the VI input
magnitude
The
The
the
as a func-
tion of the current efficiency
10Ut,P_P/l,uPPIY by varying
the magnitude
of a l-kHz
sine wave applied to the Vz
input.
Fig. 12 shows the result. The bandwidth
of this
circuit measured with a load resistor of 100 Q and a load
capacitor of 50 pF is from dc to above 1 MHz.
The
%
and a l-kHz
of
sine wave
to the V2 input.
was applied
as a modula-
1.7 VP_P at the input.
0.6 mA ~_ ~ m a 100-0
50
to the VI inputs
output current amplitude
measured in a 100-0 load resistor was 0.9 mAP_P. The total supply current was 1.0 mA.
With
a 3-V dc voltage applied to the VI input,
the
multiplier
was used as a linear control
circuit.
Fig. 11
wave
(circuit
harmonic
efficiency
5.3 V was applied
of variable
40
distortion
bandwidth
The total
the current
current
30
total harmonic
IOut,P_ ~ /1,.,,1,
The measured
4.5 MHz.
20
with
a threshold
voltage of – 0.2 V for the p-channel
transistors
and an
oxide thickness of 25 nm. The transistors used in the core
of the multiplier
all have the same geometry:
W = 40 pm,
used in the current mirrors
L = 20 pm. The transistors
have been designed much larger: W= 130 ~m, L =10 pm.
The active area including
current mirrors is about 76000
pm2.
VII.
The experimental
for both versions
harmonic
distortion
than
the total
(Figs.
DISCUSSION
results show an excellent performance
of the multiplier.
However,
the total
of the first version is essentially lower
harmonic
distortion
12 and 13), even though
of the second version
the channel
devices in the second version was larger.
pointed
out
that
the circuits
have been
length
of the
First, it has to be
fabricated
with
different
oxide thicknesses. The oxide thickness of the first
version was twice as large as that of the second version.
Referring
to (14) we note that the mobility
reduction
parameter
6 in the second version is twice as large as in
the first version. Moreover, as mentioned in Section V, the
common-mode
voltages V2C and VI, in the distortion
analysis of Section IV are not constant for the second version.
It can be shown that for this version
lIT
(21)
Now (18) predicts distortion
terms caused by third-order
terms in (16) and according to (20) this means that these
terms are proportional
to O instead of d 2.
BULT
AND
WALLINGA
:
The dominant
the nodes
input.
CMOS
poles in both
were
typically
Measured
less than
be performed
435
MULTIPLIER
designs are (determined
devices
can be improved
in these branches.
could
ANALOG
at the sources of the input
The bandwidth
current
FOUR-QUADRANT
15 mV.
because
No
offset
the
analysis
devices
[6]
VIII.
[7]
CONCLUSIONS
An extremely
simple and compact design for a CMOS
four-quadrant
multiplier
circuit has been presented. The
design is based on the square-law characteristics
of the
transistor
realized
in
of which
The first version
of 0.14 percent
percent,
[5]
were
available.
MOS
[4]
voltages
statistical
a few
[3]
of the V2
by increasing
input
only
by
saturation.
Two
versions
the second version
has a measured
at a current
a bandwidth,
has floating
total harmonic
efficiency
measured
100 Q and a load capacitor
have
been
inputs.
10Ut,P_.~,l,UPPIY of 36
with
a load
resistor
of
of 50 pF, frc)m dc to 1 MHz,
second
of 0.3
percent at a current efficiency of 40 percent, a bandwidth,
measured with a load resistor of 100 $2 and a load capacidc to 4.5 MHz,
[9]
distortion
and a supply
current
I,UPPIY of 1.65 mA. The
version has a measured total harmonic
distortion
tor of 50 pf, from
[8]
P. B. Denyer, J. Mavor, and J. W. Arthur, “Miniature
programmable
transversal filter using CCD\MOS
technology,”
Proc. IEEE, vol. 67,
pp. 42-50, Jan. 1979.
D. Brodarac.
D. Herbst. B. J. Hosticka,
and B. Hbfflirmer,
“Novel
sampled-data
MOS multiplier,”
Electrori Letf., vol. 18, p:. 229-230,
Mar. 1982.
M.-A.
Yasumoto,
T. Enomoto,
K. Watanabe,
and T. Ishihara,
“Single-chip
adaptive transversal filter IC employing
i.witched capacitor technology,”
IEEE J. Selected Areas Conrmun., vol. SAC-2, pp.
324-333,
Mar. 1984.
Z, Hong and H, Melchior,
“Four-quadrant
CMOS analogue multiNov. 1984.
plier;’
Electron Lett., vol. 20, pp. 1015-1016,
D. C. Soo and R. G. Meyer, “A four-quadrant
NMOS
anafog
multiplier,”
IEEE J. Solid-S~ate Circuils, vol. SC-17, pp. 1174-1178,
Dec. 1982.
A. Stolmeijer,
“The development
of a CMOS process using high
energy ion implantation,”
Ph.D. dissertation,
Twente Univ. of Technology, Enschede, The Netherlands,
Jan. 1986.
A. Stolmeijer,
“A twin-well
CMOS process using high energy ion
implantation,”
IEEE Trans. Electron Devices, vol. ED-33, no. 4, Apr.
1986.
and a supply
current
of
1.88 mA.
Kfaas Bult was born in Marii%berg,
The Netherlands, on June 26, 1959. He received the M.S.
degree in electrical
engineering
from Tsvente
University
of
Technology,
Enschede,
The
Netherlands,
in 1984, on the subject of a design
method for CMOS op amps, He is now working
towards the Ph.D. degree on the subject of analog computational
circuits
for applications
in
anafog adaptive filters.
ACKNOWLEDGMENT
The authors are grateful to A. Kooy and G. Boom of the
IC-processing
facility at Twente University
of Technology
for
processing
Wassenaar,
the
circuits.
O. W. Memelink,
They
also
thank
R.
F.
and E. Seevinlck for fruitful
discussions.
REFERENCES
[1] B.
multiplier
Circuitf,
[2]
multiplier
core with lateral
Electron. Lett., vol.’ 21, pp.
Gilbert,”A
precision
four-quadrant
second response,”
IEEE
J. Solid-State
365-373,
Dec. 1968.
Z. Hong and H. Melchior~’Four-quadrant
bipolar transistor in CMOS technology:
72-73, Jan. 1985.
with subnanovol. SC-3, pp.
Hans Wallinga (M81)
received the M, S. degree
in physics from the State University
of Utrecht,
The Netherlarsds,
in 1967 and the Ph.D. degree
in technicaf sciences from Twente University
of
Technology,
Enschede, The Netherlands,
in 1980.
In 1967 he joined Twente University
of Technology, where he initially
was involved in device
physics and device characterization
of MOST’s
and CCDS. Since 1975 he has been working on
CCD filters and electrically
filters. His present interest
programmable
CCD
is mainfy in the de-