Datorstödd Elektronikkonstruktion
[Computer Aided Design of Electronics]
Zebo Peng, Petru Eles and Gert Jervan
Embedded Systems Laboratory
IDA, Linköping University
http://www.ida.liu.se/~TDTS80
Electronics Systems
1
Goals
■
Basic principles of computer-aided design.
■
Digital design at high levels of abstraction.
■
Synthesis and testability techniques.
■
The hardware description language VHDL
and its use in the design/synthesis process.
Course Organization
■
Lectures (Zebo and Petru):
•
Introduction and basic terminology.
•
VHDL: overview and simulation semantics.
•
Behavioral modeling with VHDL.
•
Structural modeling with VHDL.
•
High-level synthesis of digital systems.
•
Testing and design for test.
2
Course Organization (Cont’d)
■
■
Laboratory part (Gert):
•
One seminar on the CAD system to be used.
•
Lab assignments with VHDL.
Literature:
•
Z. Navabi: “VHDL Analysis and Modeling of Digital
Systems,” or J. Armstrong and F. G. Gray: “Structured
Logic Design with VHDL.”
•
G. de Micheli: “High-Level Synthesis of Digital Circuits.”
•
Lecture notes (www.ida.liu.se/~TDTS80).
Lecture I
■
Trend in microelectronics
■
The design process and tasks
■
Different design paradigms
■
Basic terminology
■
The test problems
3
The Technological Trend
# of trans.
Moore’s Law
100M
75M
(# of transistors per chip
would double every 1.5 years)
50M
25M
75
80
85
90
95
00
year
Intel Microprocessor Evolution
I4004
I8080
I8086
I80286
I486DX
Intel DX2
Pentium
Pentium Pro
Pentium II
Pentium III
P4
Year/Month
1971/11
1974/04
1978/06
1982/02
1989/04
1992/03
1993/03
1995/11
1998/
2000/01
2000/09
Clock =1/tc.
108 KHz.
2 MHz.
10 MHz.
12 MHz.
25 MHz.
100 MHz.
60 MHz.
200 MHz.
450 MHz
1000 MHz.
1400 MHz.
Transistors.
2300
6000
29000
0.13 m.
1.2 m.
1.6 m
3.1 m
5.5 m
7.5 m.
28 m.
42 m.
Micras
10
6
3
1.50
1
0.8
0.8
0.35
0.25
0.18
0.18
4
Intel Microprocessor Evolution
P4
100M
Pentium II
10M
Pentium
1M
80486
80386
100K
80286
8086
10K
8080
4004
75
80
85
90
95
00
year
Technology Directions: SIA
Roadmap
Year
Feature size (nm)
2
Logic: trans/cm
Trans/chip
#pads/chip
Clock (MHz)
2
Chip size (mm )
Wiring levels
Power supply (V)
High-perf pow (W)
Battery pow (W)
2002 2005 2008 2011 2014
130 100
18M 44M
67.6M 190M
2553 3492
2100 3500
430 520
7
7-8
1.5
1.2
130 160
2
2.4
70
50
35
109M 269M 664M
539M 1523M 4308M
4776 6532 8935
6000 10000 16900
620 750
900
8-9
9
10
0.9
0.6
0.5
170
175
183
2.8
3.2
3.7
5
System on Chip (SoC)
Hardware
Software
microprocessor
200 m+ transistors
ASIC
800 MHz
2 watt with 1 volt
Analog
circuit
Embedded
memory
DSP
6-8 month design time
Source:
S3
Source: Stratus
Computers
Sensor
Network
High-speed electronics
Design Requirements
■
Technology-driven:
Greater Complexity
Higher Density
Increased Performance
Lower Power Dissipation
■
Market-driven:
Shorter Time-to-Market (TTM)
6
The Design Challenges
■
Complexity implication:
– 300 gates/person-week
– 15 000 gates/person-year
– For a 12-million gate system:
■
800 designers for one year
■
$120 million design cost
($150K salary)
Mixed Technologies
■
Embed in a single chip:
Logic, Analog, DRAM
blocks
■
Embed advanced
technology blocks:
LOGI
C
ANALOG
AM
DR
– FPGA, Flash, RF/Microwave
Beyond Electronic
– MEMS
– Optical elements
DRAM
LOGIC
RF
■
FLASH Analog
SRAM
FPGA
FPGA
Logic
7
What are the Solutions?
■
Powerful design methodology and tools.
■
Advanced architecture (modularity).
■
Extensive design reuse.
Design Paradigm
Shift
Capture and Simulate
■
■
■
■
The detailed design is
captured in a model.
The model is
simulated.
The results are used to
guide the improvement
of the design.
All design decisions are
made by the designers.
designers.
a
b
c
o
d
8
Abstraction Hierarchy
■
■
■
Layout/silicon level  The
physical layout of the integrated
circuits is described.
in
out
Circuit level  The detailed
circuits of transistors, resistors,
and capacitors are described.
Logic (gate) level  The
design is given as gates and
their interconnections.
a
b
c
o
d
Abstraction Hierarchy (Cont’d)
■
■
■
Register-transfer level (RTL)
 Operations are described
as transfers of values between
registers.
Algorithmic level  A system is
described as a set of usually
concurrent algorithms.
p
O
R1
R2
clk
For I=0 To 2 Loop
Wait until clk’event and clk = ´1´;
If (rgb[I] < 248) Then
P = rgb[I] mod 8;
Q = filter(x, y) * 8;
End If;
System level  A system is
described as a set of
processors and communication
channels.
9
Gajski’s Y-Chart
Behavioral
domain
Structural
domain
System level
RT - level
Algorithms, processes
Register-Transfer Spec.
Boolean Eqn.
Transistor functions.
Logic level
Circuit level
CPU, Memory, Bus
ALU, Reg., MUX
Gate, Flip-Flop
Transistor
Transistor layouts
Standard-Cell/Subcell
Macro-Cell, chips
Board, MCMs
Physical/geometrical
domain
The Three Domains
■
■
■
Structural domain  A component is described
in terms on an interconnection of more primitive
components.
Behavioral domain  A component is
described by defining its input/output response.
Physical/geometrical domain  A component
is described in terms of its physical placement
and characteristics (e.g., shape).
10
Describe and Synthesize
■
■
■
Description of a design in terms of behavioral specification.
Refinement of the design towards an implementation by
adding structural details.
Evaluation of the design in terms of a cost function and the
design is optimized w.r.t. the cost function.
a
b
c
o1 = (a + b) c + d c;
o2 = (d +f) c;
o3 = (a + b) d + d f;
...
o
d
High-Level
Describe and Synthesize
■
■
■
Description of a design in terms of behavioral specification.
Refinement of the design towards an implementation by
adding structural details.
Evaluation of the design in terms of a cost function and the
design is optimized for the cost function.
For I=0 To 2 Loop
Wait until clk’event
and clk=´1´;
If (rgb[I] < 248) Then
P=rgb[I] mod 8;
...
p
R
O
clk
enable
11
IP-Based Design
■
Intellectual Property:
pre-designed and preverified building blocks.
■
Design reuse
Hard v. soft IPs
Interface synthesis
Verification
Testing
■
■
■
■
Source: VSI Alliance
Basic Terminology
■
■
■
■
■
■
Design — A series of transformations from one representation to another until one exists that can be fabricated.
Synthesis — Transforming one representation to another at a
lower abstraction level or a behavioral representation into a
structural representation at the same level.
Analysis — Studying a representation to find out its behavior
or checking for certain property of a given representation.
Simulation — Use of a software model to study the response
of a system to input stimuli.
Verification — The process of determining that a system
functions correctly.
Optimization — The change of a design representation to a
new form with improved features.
12
Design Activities
Structural
Domain
Synthesis
Behavioral
Domain
Analysis
Refinement
Optimization
Abstraction
Generation
Extraction
Physical/geometrical
Domain
A Typical Top-Down Design
Process
Beha vio ra l
D om ain
Informal
Specification
Sy stem le v el
1
S tru ct u ra l
D o m a in
RT - lev e l
Lo gi c le ve l
Al go rithm s, p roc e sse s
R eg ist e r- Tran sfe r S pe c.
C PU , M e m ory, Bu s
AL U, R eg., M U X
C irc ui t le v el
B ool e an Eq n.
G at e , F l ip -F lop
Tra nsi sto r func ti ons.
Transi st or
Tra nsi st or lay ou ts
S ta nda rd -Ce ll /S ubc e ll
M a cro-C el l, chi ps
B oard, M C Ms
Phy sical D o m a in
13
Testing and its Current Practice
■
To meet users’ quality requirements.
■
Testing aims at the detection of physical faults
(production errors/defects and physical failures).
Automatic Test Equipment
Testing of Mixed Technologies
■
How to test the mixed
chip?
■
Need multiple ATE for
a single chip: Logic
ATE, Memory ATE,
Analog ATE.
Need SUPER ATE w
combined capabilities.
■
LOGI
ANALOG
C
AM
DR
14
High Performance On Chip
■
■
High speed ATE substantially
more expensive.
ATE vs chip technology
discrepancy: Tester uses 5
year old technology - Chips
move to next generation every
2 years.
ATE accuracy degrading:
Chip cycle time will crossover
ATE accuracy.
1000
T im e in n s , y ie ld lo s s in p e r c e n t
■
100
S ilic o n s p e e d
O TA
10
1
0 ,1
1980
1985
1990
1995
2000
2005
2010
2015
Year
Source: SIA Roadmap
High Complexity: Bandwidth
■
■
■
# of transistors
increases
exponentially.
# of access port
remains stable.
Implication:
– # of transistors per
pin (Testing
Complexity Index)
increases rapidly.
Im p lic a tio n s o f S IA R o a d m a p : Testing
Te sti ng C o m pl e xi ty Inde x - [# Tr . pe r P i n]
1.60E+ 5
1.40E+ 5
1.00E+ 5
8.00E+ 5
6.00E+ 4
4.00E+ 4
2.00E+ 4
0.00E+ 0
Year
1992
F. Size [µ
µm] 0.5
1995
0.35
1998
0.25
2001
018
2004
0.12
2007
0.1
Sourc e: W . Maly , 1996
Source: SIA Roadmap
15
Built-In Self Test (BIST)
■
Solution: Dedicated built-in
hardware for embedded test
functions.
External
Test
■
■
■
■
■
No need for expensive
ATE.
At-speed testing.
Current test possible.
Support O&M.
Support field test.
Standard
Digital
Tester
Limited
Speed/
Accuracy
Low
Cost-per-Pin
Memory
Embedded
Test
(Built-in)
Logic
Pattern Generation
Result Compression
Precision Timing
Diagnostics
Power Management
Test Control
Support for
Board-level Test
System-Level Test
.
MixedSignal
I/Os &
Interconnects
Source: LogicVision
Challenges to the CAD
Communities
■
System specification with very high-level
languages.
■
Modeling techniques for heterogeneous system.
■
Testing must be considered during the design
process.
■
Design verifications -> get the whole system right
the first time!
■
Very efficient power saving techniques.
■
Global optimization.
16
The Electronics System Designer
Low cos
t
High perf.
Low
pow
Good tes
tability
ity
abil
X
Conclusion Remarks
■
Much of design of digital systems is managing
complexity.
■
What is needed: new techniques and tools to help
the designers in the design process, taking into
account different aspects.
■
We need especially design tools working at the
higher levels of abstraction.
■
If the complexity of the microelectronics
technology will continue to grow, the migration
towards higher abstraction level will continue.
17