User's Guide
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LMK04826/28 User’s Guide
1
Introduction
These evaluation board instructions describes how to set up and operate the LMK04828/6 evaluation
module (EVM). The LMK04828/6 is the industry's highest performance clock conditioner with JEDEC
JESD204B support.
2
Evaluation Board Kit Contents
The evaluation board kit includes. -002 and -003 are currently available:
Table 1. EVM Contents
SV600788
-001
Evaluation Board
-002
-003
(1) LMK04826B Evaluation
Board
(1) LMK04828B Evaluation Board
USB Communications
(1) USB2UWIRE-IFACE
(1) USB2ANY
LPT Communicaitions
(1) CodeLoader uWire cable
-
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1
Quick Start
4 to 5 V
1
3
Parallel Port or USB
Connector to SPI
x
DCLKout0*
DCLKout0
Power
SDCLKout1*
SDCLKout1
Quick Start
DCLKout3*
DCLKout3
3
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DC
DC LKo
LK u t 2
ou
t2*
Default is
LDO to IC
x
x
1*
ut1
Ko ut11
L
C
o
SD CLK
SD
x
x
Laptop or PC
LMK0482x
Parallel Port Cable, or
USB2UWIRE-IFACE cable, or
USB2ANY cable
PLL1 Digital Lock Detect LED
4
DC
DC LKo
LK ut1
ou 0*
t10
Program with CodeLoader
%H VXUH WR SUHVV µ&WUO - /¶
2
Reference
OSCin
OSCin*
Reference clock from
signal generator or other
external source.
122.88 MHz (Default)
OSCout
OSCout*
1*
Kin
CLKin0
CLKin0*
CL
PLL2 Digital
Lock Detect LED
These SMAs not used by default.
With PCB change, can be used for reference
input for single PLL mode.
Figure 1. Quick Start Diagram
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Quick Start
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3.1
Quick Start Description
The LMK04828/6 EVM allows full verification of the device functionality and performance specifications.
To quickly set up and operate the board with basic equipment, refer to the quick start procedure below
and test setup shown in Figure 1.
1. Connect a voltage of 4.5 volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V
using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.
2. Connect a reference clock to the CLKin1 port from a signal generator or other source. Use 122.88 MHz
for default. Exact frequency and input port (CLKin0/CLKin1) depends on programming.
3. Connect the SPI header to a computer using USB2ANY, USB2UWIRE-IFACE, or parallel port with the
CodeLoader cable.
4. Program the device with CodeLoader. CodeLoader is available for download at:
http://www.ti.com/tool/codeloader.
(a) Select LMK04828B or LMK04826B from “Select Device → Clock Conditioners” Menu.
(b) Select LPT or USB mode from the Port Setup tab as required. If USB is selected, confirm that
USB device being used to communicate with EVM is chosen from list of available USB devices.
(c) Select a default mode from the “Mode” Menu. For the quick start use, “CLKin1 122.88 MHz, OSCin
122.88 MHz”
(d) Ctrl-L must be pressed at least once to load all registers. Alternatively click menu Keyboard
Controls → Load Device.
5. Measurements may be made at an active CLKout port via its SMA connector.
NOTE: New REV C boards dated 02-18-2013 have an updated Pin Configuration which is defaulted.
For older pre-release boards, Pin Configuration must manually be changed and only work with
USB2UWIRE-IFACE or LPT cable.
Figure 2. Pin Configuration for Pre-Release Boards
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Quick Start
3.1.1
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CLKout Tab Description
1
2
11
3
12
4
5
13
6
7
14
8
9
15
10
16
Figure 3. CLKout Tab Description Diagram
Device Clock Controls
1. CLKoutX_Y_CNTL/CNTH for controlling digital delay.
2. Half step bit (must have a HS mode selected by #6 or #7).
3. Power down digital delay for DCLKoutX.
4. DCLKoutX_DIV, divider for the output channel.
5. Analog delay (if enabled with #6).
6. Select source for output. Can be divider only, divider w/ DCC+HS (duty cycle correction and half step),
bypass, or analog delay w/ Divider (and DCC/HS if selected by #7).
7. Select DCC/HS or not when using analog delay mode.
8. Powerdown the entire CLKoutX_Y block. Both outputs will be off.
Device Clock/SYSREF Controls
9. Select output type for each output.
10. SYNC_POL bit, will allow SYNC when in default configuration (SYNC_MODE / SYSREF_MUX setup
for normal SYNC).
SYSREF Controls
11. SYSREF clock digital delay.
12. SYSREF clock half step
13. SYSREF analog delay (if enabled by #14)
14. Enable analog delay
15. Select Device Clock or SYSREF clock for output to SDCLKoutY clock.
16. Calculated output frequency.
3.1.2
CodeLoader Tips
On Bits/Pins tab right-clicking any register name in the Bits/Pins tab will display a Help prompt with the
register address, data bit location/length, and a brief register description.
• On PLL tabs clicking Show Bits will show register info.
• On other tabs, pressing ~ with a control focused will show help.
•
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Quick Start
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3.2
SYSREF Quick Start
The LMK0482x EVK allows for verification of the LMK0482x’s implementation of JESD 204B SYSREF
functionality. To quickly setup and operate the SYSREF functions refer to the following procedures.
3.2.1
1.
2.
3.
4.
5.
6.
7.
8.
Continuous SYSREF
Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
Set SYSREF_PD and SYSREF_DDLY_PD = 0
Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
Perform a SYNC event (toggle SYNC_POL on/off/on)
Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
Set SYSREF_MUX = 3 (SYSREF Continuous)
Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
In Figure 2 and Figure 4 the Blue trace is DCLKout6 at 245.76 MHz and the Green trace is SDCLKout7
(SYSREF) at 24.475 MHz. Figure 5 shows the configuration of the LMK0482xB outputs.
Figure 4. Continuous SYSREF Output
3.2.2
1.
2.
3.
4.
Pulsed SYSREF
Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
Set SYSREF_PD and SYSREF_DDLY_PD = 0
Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
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5. Perform a SYNC event (toggle SYNC_POL on/off/on)
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
7. Set SYSREF_MUX = 2 (SYSREF Pulses)
8. Set SYSREF_PULSE_CNT = 1, 2, 4, or 8 as desired
9. Generate a SYNC event (i.e. toggle SYNC_POL on/off/on)
10. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
Figure 5. Pulsed SYSREF Output
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Quick Start
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Figure 6. Clock Outputs Tab Setup for SYSREF Output on SDCLKout7
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7
PLL Loop Filters and Loop Parameters
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PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a
“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to
minimize the impact of the reference clock phase noise. The reference clock consequently serves only as
a frequency reference rather than a phase reference.
The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter for
PLL1 has been configured for a narrow loop bandwidth (> 100 kHz). The specific loop bandwidth values
depend on the phase noise performance of the oscillator mounted on the board. The following tables
(Table 2 and Table 3) contain the parameters for PLL1 and PLL2 for each oscillator option.
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:
http://www.ti.com/tool/clockdesigntool
4.1
PLL1 Loop Filter
Table 2. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO (1)
122.88 MHz VCXO PLL
Phase Margin
50˚
Kφ (Charge Pump)
450 uA
Loop Bandwidth
14 Hz
Phase Detector Freq
1.024 MHz
VCO Gain
2.5 kHz/V
Reference Clock Frequency
122.88 MHz
Output Frequency
122.88 MHz
(To PLL 2)
Loop Filter Components
C1_A1 = 100 nF
C2_A1 = 680 nF
R2_A1 = 39 kΩ
(1)
4.2
Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.
PLL2 Loop Filter
Table 3. Integrated VCO PLL (1)
LMK04826
VCO0
LMK04828
VCO1
8
VCO1
C1_A2
0.047
nF
C2_A2
3.9
nF
C3 (internal)
0.01
nF
C4 (internal)
0.01
nF
R2_A2
0.62
kΩ
R3 (internal)
0.2
kΩ
R4 (internal)
0.2
kΩ
Charge Pump Current, Kφ
3.2
mA
Phase Detector Frequency
(1)
VCO0
122.88
MHz
Frequency
1966.08
2457.6
2457.6
2949.12
MHz
Kvco
15.3
8.9
21.9
17.4
MHz/V
N
16
20
20
24
Phase Margin
73
64
73
70
degrees
Loop Bandwidth
303
151
344
233
kHz
PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop
bandwidth.
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Default CodeLoader Modes for the LMK0482x
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5
Default CodeLoader Modes for the LMK0482x
CodeLoader saves the state of the selected LMK0482x device when exiting the software. To ensure a
common starting point, the following modes listed in Table 4 may be restored by clicking “Mode” and
selecting the appropriate device configuration.
Table 4. Default CodeLoader Modes for the LMK0482x
Default CodeLoader Mode
Device Mode
CLKin Frequency
OSCin Frequency
CLKin1 122.88 MHz, OSCin
122.88 MHz
Dual PLL, Internal VCO
122.88 MHz
122.88 MHz
Figure 7. Selecting a Default Mode for the LMK04828 Device
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Using CodeLoader to Program the LMK04828
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Using CodeLoader to Program the LMK04828
The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements
with the LMK04828B device as an example. For more information on CodeLoader refer to CodeLoader 4
instructions located at http://www.ti.com/tool/codeloader
Before proceeding, be sure to follow the Section 3 section above to ensure proper connections. To
program the LMK04826B the procedure would be the same but select the LMK04826B as the device.
6.1
Start CodeLoader Application
Click “Start” → “Programs” → “CodeLoader 4” → “CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
6.2
Select Device
Click “Select Device” → “Clock Conditioners” → “LMK04828B”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select Device” from
the menu bar, then select the subgroup and finally device to load. For this example, the LMK04828B is
chosen. Selecting the device does cause the device to be programmed.
6.3
Program/Load Device
Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls” →
“Load Device” from the menu to program the device to the current state of the newly loaded LMK04828
file.
Figure 8. Loading the Device
Once the device has been initially loaded, CodeLoader will automatically program changed registers so it
is not necessary to re-load the device upon subsequent changes in the device configuration. It is possible
to disable this functionality by ensuring there is no checkmark by the “Options” → “AutoReload with
Changes.”
Because a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader,
restoring a mode, or restoring a saved setup using the File menu.
See CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader/ for more information on Port
Setup. This contains information on troubleshooting communications.
6.4
Restoring a Default Mode
Click “Mode” → “CLKin1 122.88 MHz, OSCin 122.88 MHz”; then press Ctrl+L.
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Figure 9. Setting the Default Mode for LMK04828
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.
This is important because when CodeLoader is closed, it remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
6.5
Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D4, and D5 should illuminate when PLL1 and PLL2 are
locked to the reference clock applied to CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD,
PLL2_LD_MUX = PLL2_DLD and PLLX_LD_TYPE = Output (Push-Pull).
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Evaluation Board Inputs and Outputs
6.6
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Enable Clock Outputs
While the LMK0482x offers programmable clock output buffer formats, the evaluation board is shipped
with preconfigured output terminations to match the default buffer type for each output.
To measure Phase noise at one of the clock outputs, for example DCLKout0:
1. 1. Click on the Distribution tab,
2. 2. Uncheck “Powerdown” in the Clock output box to enable the channel,
3. 3. Set the following settings as needed:
(a) Digital Delay value
(b) Clock Divider value
(c) Analog delay select and Analog Delay value (if not “Analog Delay and Divider” is selected in the
Analog Delay Select box,
Figure 10. Setting Digital Delay, Clock Divider, Analog Delay and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument
with a single-ended 50-ohm input as follows.
(a) For LVDS:
(i) A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-tosingle-ended conversion.
(b) For LVPECL:
(i) A balun can be used, or
(ii) One side of the LVPECL signal can be terminated with a 50-ohm load and the other side can
be run single-ended to the instrument.
(c) For HSDS:
(i) A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-tosingle-ended conversion.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
TI’s Clock Design Tool can be used to calculate divider values to achieve desired clock output
frequencies. See: http://www.ti.com/tool/clockdesigntool
7
Evaluation Board Inputs and Outputs
The following table (Table 5) contains descriptions of the inputs and outputs for the evaluation board.
Unless otherwise noted, the connectors described can be assumed to be populated by default.
Additionally, some applicable CodeLoader programming controls are noted for convenience.
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Table 5. Description of Evaluation Board Inputs and Outputs
Connector Name
Signal Type,
Input/Output
Description
Populated:
DCLKout0,
DCLKout0*,
SDCLKout1,
SDCLKout1*,
DCLKout2,
DCLKout2*,
SDCLKout3,
SDCLKout3*,
DCLKout10,
DCLKout10*
SDCLKout11,
SDCLKout11*
Analog,
Output
Clock outputs with programmable output buffers.
The output terminations by default on the evaluation board are shown below:
Clock Output Pair
Default Board Termination
DCLKout0
240 Ω
SDCLKout1
240 Ω
DCLKout2
240Ω
SDCLKout3
240 Ω
DCLKout4
HSDS / LVDS
SDCLKout5
HSDS / LVDS
DCLKout6
HSDS / LVDS
SDCLKout7
HSDS / LVDS
DCLKout8
HSDS / LVDS
SDCLKout9
HSDS / LVDS
DCLKout10
HSDS / LVDS
SDCLKout11
HSDS / LVDS
DCLKout12
HSDS / LVDS
SDCLKout13
HSDS / LVDS
Each CLKout pair has a programmable LVDS, LVPECL, or HSDS buffer. The
output buffer type can be selected in CodeLoader in the Clock Outputs tab via the
CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing with RF test equipment.
All LVPECL clock outputs are terminated using 240 Ω emitter-resistors.
If an output pair is programmed to LVCMOS, each output can be independently
configured (normal, inverted, or off/tri-state).
Populated:
OSCout, OSCout*
Analog,
Output
Buffered outputs of OSCin port.
The output terminations on the evaluation board are shown below.:
OSC output pair
Default Board Termination
OSCout
LVPECL
OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The
OSCout buffer type can be selected in CodeLoader on the Distribution tab via the
OSCout_FMT control.
OSCout is AC-coupled to allow safe testing with RF test equipment.
The OSCout output is terminated using 240 Ω emitter-resistors.
If OSCout is programmed as LVCMOS, each output can be independently
configured (normal, inverted, inverted, and off/tri-state).
Best performance/EMI reduction is achieved by using a complementary output
mode like Norm/Inv. It is NOT recommended to use Norm/Norm or Inv/Inv mode.
Vcc
Power,
Input
Main power supply input for the evaluation board.
The LMK0482x contains internal voltage regulators for the VCO, PLL and other
internal blocks. The clock outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability is required for optimal
performance.
On-board LDO regulators and 0 Ω resistor options provide flexibility to supply and
route power to various devices. See the schematics in section Section 11 for more
details.
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Evaluation Board Inputs and Outputs
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Table 5. Description of Evaluation Board Inputs and Outputs (continued)
Connector Name
Signal Type,
Input/Output
Description
Populated:
J1
Power,
Input
Alternative power supply input for the evaluation board using two unshielded wires
(Vcc and GND).
VccVCXO/Aux
Power,
Input
Optional Vcc input to power the VCXO circuit if separated voltage rails are needed.
The VccVCXO/Aux input can power these circuits directly or supply the on-board
LDO regulators. 0 Ω resistor options provide flexibility to route power.
Populated:
CLKin0, CLKin0*,
CLKin1*
Analog,
Input
Reference Clock Inputs for PLL1 (CLKin0, 1). CLKin1 can alternatively be used as
an External Feedback Clock Input (FBCLKin) in 0-delay mode or an RF Input (Fin)
in External VCO mode.
Apply power to either Vcc SMA or J1, but not both.
Reference Clock Inputs for PLL1 (CLKin0, 1)
FBCLKin/CLKin1* is configured by default for a single-ended reference clock input
from a 50-ohm source.The non-driven input pin (FBCLKin/CLKin1) is connected to
GND with a 0.1 uF. CLKin0/CLKin0* is configured by default for a differential
reference clock input from a 50-ohm source.
Not Populated:
CLKin1
CLKin1* is the default reference clock input selected in CodeLoader. The clock
input selection mode can be programmed on the Bits/Pins tab via the Clock Inputs
control.
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1
for 0-delay mode. See the LMK04820 family datasheet (literature number
SNAS605) for more details on using 0-delay mode with the evaluation board and
the evaluation board software.
Populated:
OSCin, OSCin*
Analog,
Input
Feedback VCXO clock input to PLL1 and Reference clock input to PLL2.
The single-ended output of the onboard VCXO (U4) drives the OSCin* input of the
device and the OSCin input of the device is connected to GND with 0.1 uF.
A VCXO add-on board may be optionally attached via these SMA connectors with
minor modification to the components going to the OSCin/OSCin* pins of device.
This is useful if the VCXO footprint does not accommodate the desired VCXO
device or if the user desires to use the LMK0482xB in single loop mode.
A single-ended or differential signal may be used to drive the OSCin/OSCin* pins
and must be AC coupled. If operated in single-ended mode, the unused input must
be connected to GND with 0.1 uF.
Refer to the LMK04820 family datasheet section “Electrical Characteristics” for
PLL2 Reference Input (OSCin) specifications (literature number SNAS605).
Test point:
VTUNE1_TP
Analog,
Input
Tuning voltage output from the loop filter for PLL1.
If a VCXO add-on board is used, this tuning voltage can be connected to the
voltage control pin of the external VCXO when this SMA connector is installed and
connected through R72 by the user.
Test point:
VTUNE2_TP
Analog,
Input
Tuning voltage output from the loop filter for PLL2.
Test points:
SDIO
SCK
CS*
CMOS,
Input/Output
10-pin header for SPI programming interface and programmable logic I/O pins for
the LMK0482x.
Populated:
SPI
10-pin header for SPI programming interface and programmable logic I/O pins for
the LMK0482x.
The programmable logic I/O signals accessible through this header include:
RESET, SYNC, Status_LD1, Status_LD2, CLKin_SEL0, and CLKin_SEL1. These
logic I/O signals also have dedicated SMAs and test points.
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Table 5. Description of Evaluation Board Inputs and Outputs (continued)
Connector Name
Signal Type,
Input/Output
Description
Test point:
Status_LD1_TP
CMOS,
Input/Output
Programmable status output pin. By default, set to output the digital lock detect
status signal for PLL1.
In the default CodeLoader modes, LED D5 will illuminate green when PLL1 lock is
detected by the LMK0482x (output is high) and turn off when lock is lost (output is
low).
Status_LD
Test point:
Status_LD2_TP
The status output signal for the Status_LD1 pin can be selected on the Bits/Pins
tab via the PLL1_LD_MUX control.
CMOS,
Input/Output
Programmable status output pin. By default, set to output the digital lock detect
status signal for PLL2.
In the default CodeLoader modes, LED D4 will illuminate green when PLL1 lock is
detected by the LMK0482x (output is high) and turn off when lock is lost (output is
low).
Status_LD2
Test points:
CLKin0_SEL_TP
CLKin1_SEL_TP
The status output signal for the Status_LD1 pin can be selected on the Bits/Pins
tab via the PLL2_LD_MUX control.
CMOS,
Input/Output
Programmable status I/O pins. By default, set as input pins for controlling input
clock switching of CLKin0 and CLKin1.
These inputs will not be functional because CLKin_SEL_MODE is set to 0 (CLKin0
Manual) by default in the Bits/Pins tab in CodeLoader. To enable input clock
switching, CLKin_SEL_MODE must be 3 and Status_CLKinX_TYPE must be 0 to 3
(pin enabled as an input).
Input Clock Switching – Pin Select Mode
When CLKin_SEL_MODE is 3, the Status_CLKinX pins select which clock input is
active as follows:
Test point:
SYNC_TP
CMOS,
Input/Output
Status_CLKin1
Status_CLKin0
Active Clock
0
0
CLKin0
0
1
CLKin1
1
0
CLKin2
1
1
Holdover
Programmable status I/O pin. By default, set as an input pin for synchronize the
clock outputs with a fixed and known phase relationship between each clock output
selected for SYNC. A SYNC event also causes the digital delay values to take
effect.
SYNC/SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous
mode (0x03) when SYSREF_REQ_EN = 1.
Populated:
SYNC
SYNC/SYSREF_REQ pin can hold outputs in a low state, depending on system
configuration. SYNC_POL adjusts for active low or active high control.
A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the
Bits/Pins tab in CodeLoader.
Test point:
RESET_TP
CMOS,
Input/Output
Programmable status I/O pin.
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Recommended Test Equipment
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Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply, particularly when the devices on the board are
being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052 is superior for phase noise measurements. At frequencies less than 100 MHz
the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A’s internal
local oscillator performance, not the device under test.
Oscilloscope
To measure the output clocks for AC performance, such as rise time or fall time, propagation delay, or
skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input bandwidth (2.5+
GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To evaluate clock synchronization or
phase alignment between multiple clock outputs, it’s recommended to use phase-matched, 50-ohm cables
to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope
probes.
16
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Appendix A: CodeLoader Usage
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9
Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the included USB2UWIRE-IFACE.
9.1
Port Setup Tab
Figure 11. Port Setup Tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be
used to program the device on the evaluation board. If parallel port is selected, the user should ensure
that the correct port address is entered. If USB mode is selected, identify the correct target device by
clicking the Identify button - the selected USB2ANY will blink the onboard LED 5 times.
The Pin Configuration field is hardware dependent and normally does not need to be changed by the user
(except for pre-release boards). For information on this configuration, refer to Figure 2.
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Appendix A: CodeLoader Usage
9.2
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PLL1 Tab
Figure 12. PLL1 Tab
The PLL1 tab allows the user to change the following parameters in Table 6.
Table 6. Registers Controls and Descriptions in PLL1 Tab
18
Control Name
Register Name
Description
Reference Oscillator Frequency (MHz)
n/a
CLKin frequency of the selected reference
clock.
Phase Detector Frequency (MHz)
n/a
PLL1 Phase Detector Frequency (PDF).
This value is calculated as:
PLL1 PDF = CLKin Frequency / (PLL1_R)
VCO Frequency (MHz)
n/a
The VCO Frequency should be the OSCin
frequency, except when operating in Dual
PLL with 0-delay feedback. This value is
calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
R Counter
PLL1_R
PLL1 R Counter value (1 to 16383).
N Counter
PLL1_N
PLL1 N Counter value (1 to 16383).
Phase Detector Polarity
PLL1_CP_POL
PLL1 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
Charge Pump Gain
PLL1_CP_GAIN
PLL1 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (50,150, 250, 1550 uA).
Charge Pump State
PLL1_CP_TRI
PLL1 Charge Pump State.
Click to toggle between Active and TriState.
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9.3
PLL2 Tab
Figure 13. PLL2 Tab
The PLL2 tab allows the user to change the following parameters in Table 7.
Table 7. Registers Controls and Descriptions in PLL2 Tab (1)
Control Name
Register Name
Description
Reference Oscillator Frequency (MHz)
OSCin_FREQ
OSCin frequency from the External VCXO
or Crystal.
Phase Detector Frequency (MHz)
n/a
PLL2 Phase Detector Frequency (PDF).
This value is calculated as:
PLL2 PDF = OSCin Frequency
*(2EN_PLL2_REF_2X) / PLL2_R.
VCO Frequency (MHz)
n/a
Internal VCO Frequency should be within
the allowable range of the LMK048xxB
device.
This value is calculated as:
VCO Frequency = PLL2 PDF * (PLL2_N *
PLL2_P * VCO divider value).
Doubler
EN_PLL2_REF_2X
PLL2 Doubler.
0 = Bypass Doubler
1 = Enable Doubler
R Counter
PLL2_R
PLL2 R Counter value (1 to 4095).
N Counter
PLL2_N
PLL2 N Counter value (1 to 262143).
PLL Prescaler
PLL2_P
PLL2 N Prescaler value (2 to 8).
Phase Detector Polarity
PLL2_CP_POL
PLL2 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
Charge Pump Gain
PLL2_CP_GAIN
PLL2 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 400, 1600, 3200
uA).
Charge Pump State
PLL2_CP_TRI
PLL2 Charge Pump State.
Click to toggle between Active and TriState.
(1)
Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency should conform to the specified
internal VCO frequency range.
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Appendix A: CodeLoader Usage
9.4
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Distribution Tab
Figure 14. Distribution Tab
The Distribution tab allows the user to control the output channel blocks.
Note that the total PLL2 N divider value is the product of the VCO Divider value and the PLL N Prescaler
and N Counter values (shown in the PLL2 tab), and is given by:
PLL2 N Total = PLL2 N Prescaler * PLL2 N Counter
(1)
Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the PLL2 tab into
focus where these values may be modified, if needed.
Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4, C4) allow one
to step through the possible values. Left click to increase the component value, and right click to decrease
the value. These values can also be changed in the Bits/Pins tab.
20
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9.5
SYSREF Tab
Figure 15. SYSREF Tab
The SYSREF tab show the controls for SYSREF functionality as well as Dynamic Digital Delay enable.
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Appendix B: Typical Phase Noise Performance Plots
9.6
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Bits/Pins Tab
Figure 16. Bits/Pins Tab
The Bits/Pins tab allows the user to program bits not available on other tabs.
NOTE: Right-clicking any register name in the Bits/Pins tab will display a Help prompt with the
register address, data bit location/length, and a brief register description.
10
Appendix B: Typical Phase Noise Performance Plots
The LMK0482x’s dual PLL architecture achieves ultra low jitter and phase noise by allowing the external
VCXO or Crystal’s phase noise to dominate the final output phase noise at low offset frequencies and the
internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This
results in the best overall noise and jitter performance.
Table 8 lists the test conditions used for output clock phase noise measurements with the Crystek 122.88
MHz VCXO.
22
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Table 8. LMK0482x Test Conditions
Parameter
Value
PLL1 Reference clock input
CLKin1* single-ended input, CLKin1 AC-coupled to GND
PLL1 Reference Clock frequency
122.88 MHz
PLL1 Phase detector frequency
1024 kHz
PLL1 Charge Pump Gain
450 uA
VCXO frequency
122.88 MHz
PLL2 phase detector frequency
122.88 MHz
PLL2 Charge Pump Gain
3200 uA
PLL2 REF2X mode
Enabled
10.1 122.88 MHz VCXO Phase Noise
The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow loop
bandwidth for PLL1 while retaining the frequency accuracy of the reference clock input. This VCXO sets
the reference noise to PLL2. Figure 17 shows the open loop typical phase noise performance of the
CVHD-950-122.88 Crystek VCXO.
Figure 17. Crystek CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz
Table 9. VCXO Phase Noise and Jitter
Offset
VCXO Phase Noise at 122.88 MHz
(dBc/Hz)
VCXO RMS Jitter to high offset of 20
MHz at 122.88 MHz (rms fs)
10 Hz
-76.6
60.5
100 Hz
-108.9
36.2
1 kHz
-137.4
35
10 kHz
-153.3
34.5
100 kHz
-162
32.9
1 MHz
-165.7
22.7
10 MHz
-168.1
515.4
40 MHz
-168.1
60.5
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Appendix B: Typical Phase Noise Performance Plots
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10.2 Output Measurement Technique
The same technique was used to measure phase noise for all three output types available on the
programmable OSCout and CLKout buffers. This was achieved by terminating one side of the LVPECL,
LVDS, or LVCMOS output with a 50-ohm load, and measuring the other side single-ended using an
Agilent E5052B Source Signal Analyzer.
10.3 Clock Outputs (DCLKout and SDCLKout)
The LMK0482x features programmable HSDS, LVDS, LVPECL buffer modes for the DCLKoutX,
SDCLKout pairs. Below is a phase noise measurement of DCLKout2 (best phase noise clock output)
using both a balun and single ended.
Figure 18. LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G
24
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Figure 19. LMK04826 DCLKout2, VCO0, 245.76 MHz, Div8, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended
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Appendix B: Typical Phase Noise Performance Plots
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Figure 20. LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = Prodyn BIB-100G
26
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Figure 21. LMK04826 DCLKout2, VCO1, 245.76 MHz, Div10 , LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended
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Appendix B: Typical Phase Noise Performance Plots
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Figure 22. LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T
28
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Figure 23. LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended
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Appendix B: Typical Phase Noise Performance Plots
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Figure 24. LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T
30
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Figure 25. LMK04828 DCLKout2, VCO1, 245.76 MHz, Div12, LVPECL20 /w
240 ohm emitter resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Single Ended
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Appendix C: Schematics
11
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Appendix C: Schematics
Direct Power - NO Regulators
VccTP
Vcc
Vcc
GND_TP
TESTPOINT
2
3
4
5
142-0701-201
VccPLLPlane
R326
DNP
120 FB
1
TESTPOINT
R328
DNP
120 FB
J1
1
2
1
2
TERMBLOCK_2
C310
10µF
C311
1µF
C312
0.1µF
C317
10µF
C318
1µF
C319
0.1µF
C324
10µF
C325
1µF
C326
0.1µF
VccCLKoutPlane
R330
DNP
120 FB
VccAuxPlane
R332
0
VccPLLPlane
R336
0
R337
0
LDO for powering LMK04828
VccCLKoutPlane
R342
LP3878SD-ADJ
VccLDOin
U302
R95
4
0
R350
8
51k
2
7
9
C340
4.7µF
OUT
SD
ADJ
NC
NC
DAP
BYP
GND
120 FB
LDO_Out_LP3878
TESTPOINT
V_LM3878-ADJ
IN
5
6
C341 R351
2200pF 2.00k
1
C342
1µF
VccAuxPlane
R349
R343
0
120 FB
Power Plane for LMK Except Outputs
VccPLLPlane
C352
10µF
R305
120 FB
3
C346
0.1µF
LP3878SD-ADJ/NOPB
R356
866
R310
C313
10µF
R307
Aux Power for XO/VCXO, Status LEDs
LP3878-ADJ 3.3 V component values:
C340 = 4.7 uF
R351= 2.00 k
C346 = 0.01 uF
R356= 866
C352 = 10 uF
R350= 51 k
C341 = 2.2 nF
120 FB
C322
0.1µF
Digital
0
DNPC320
0.1µF
C323
0.01µF
Vcc5_DIG
R329
Vcc5_DIG_1
0
C321
1µF
VCO
0
DNPC316
0.1µF
R323
Vcc1_VCO
R327
Vcc1_VCO_1
0
C315
0.01µF
C314
1µF
Vcc6_PLL1
R334
0
0
DNPC327
100pF
R74
DNP
0
R338
R331
Vcc6_PLL_1
Vcc7_OSCout_1
0
DNPC332
100pF
Vcc7_OSCout
R341
120
PLL1
OSCout
DNPC361
0.1µF
DC-DC to LDO to Power LMK04828
DNPC331 DNPC333 DNPC353
100µF
4.7µF
0.01µF R311 DNPC354
DNP
30.9k
0.1µF
R339
6
7
8
9
10
R377
DNP
0
11
LDOIN
NR
GND
LDOEN
NC
NC
RT/CLK
PWRGD
DNPGND
PGND
PGND
BOOT
PH
PVIN
PH
PVIN
EN
VIN
12
DNPC370
10µF
COMP
5
R365
DNP
40.2k
U301
TPS54120RGYR
LDOIN
0
4
GND
FB
DAP
3
VSENSE
GND
OUT
SS
R362
DNP
0
23
R340
VccAuxPlane
22
21
R335
0.1µF
1
6
R360
2
DNP
U303
4
51k
7
C350
0.47µF
142-0711-201
OUT
EN
NC
NC
GND
DAP
DNPC328
0.1µF
17
120
CP2
DNPC329
0.1µF
DNP
0.1µF
L300
DNP
16
744031220
22µH
15
14
R378
DNP
0
DNPC362 R366
DNPC363 DNPC369
100pFDNP
41.2k
47µF
0.1µF
Power Planes for LMK Outputs
VccCLKoutPlane
R379
DNP
10k
R380 DNPC372
DNP
2.2k
330pF
R347
120 FB
Vcc_VCO
Vcc2_CG1_1
Vcc4_CG2_1
120 FB
C351
0.47µF
Vcc11_CG3_1
120 FB
GND
C300
1µF
CG1
Vcc4_CG2
CG2
Vcc11_CG3
CG3
Vcc12_CG0_1
R344
LP5900SD-3.3/NOPB
R105
Vcc2_CG1
0
C347
1µF
C364
1µF
R101
0
C343
1µF
R358
R100
0
C337
1µF
R354
120 FB
R367
DNP
0
1
PLL2
0
C358
18
R371
2
5
3
Vcc10_PLL2
R346
19
Vcc_VCO_LDO
IN
OSCin
DNPC335
0.1µF
R333
Vcc9_CP2_1
0
GND
20
LP5900SD-3.3
R370
DNP
0
120 FB
Vcc9_CP2
R368
DNP
0
R229
DNP
0
R345
DNP
120 FB
R363
DNP
0
VccVCO/Aux
DNPC336
0.1µF
GND
DNPC373
0.047µF
Regulator to power VCO Separately
Vcc10_PLL2_1
0
GND
DNPC371
0.01µF
GND
DNPC334
0.1µF
C357
13
2
OUT
1
24
R361
DNP
10k
GND
Vcc8_OSCin_1
0
DNPC355 DNPC356
0.1µF
10µF
Vcc8_OSCin
R106
0
Vcc3_SYSREF_1 R107
0
Vcc12_CG0
CG0
Vcc3_SYSREF
SYSREF
LP5900 Component values
C359 = 0.47 uF
C360 = 0.47 uF
R369 = 51 k
R364
0
Vcc_VCXO
Regulator to power VCXO Separately
VccAuxPlane
R352
DNP
0
R54
DNP
0
LP5900SD-3.3
VccVCXO/Aux
R373
1
2
DNP
142-0711-201
U305
6
0
C359
0.47µF
R369
51k
4
7
Vcc_VCXO_LDO
IN
OUT
EN
NC
NC
GND
DAP
1
2
5
3
R19
0
C360
0.47µF
Switch resistor
for power.
LP5900SD-3.3/NOPB
LP5900 Component values
C359 = 0.47 uF
C360 = 0.47 uF
R369 = 51 k
GND
Figure 26. Power Supply
32
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Appendix C: Schematics
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VCC_VCO_TP
Vcc_VCO
R22
DNP
0
10
9
R43
DNP
0
8
7
GND
GND
GND
RF out
GND
PLL2 Loop Filters
DNP
0.1µF
5
PLL2_Vtune_AF
Rb2_VCO
DNP
DNP
R353
DNP
0
R302
DNP
10k
Vcc_VCO_OpAmp
R303
DNP
10k
DNPC17
100pF
GND
Vtune
GND
GND
GND
DNP GND
Fout
GND
12
11
10
9
VCO_Fout
CRO2949A-LF
U300
LMP7731MF
4
1
V+
V-
DNP
3
Vcc_VCO_LDO DNP
0
2
R304
DNP
0
DNPCb2pVCO
DNPCb2_VCO
DNP
DNPCb1_VCO DNP
DNP
R53
DNP
0
R300
DNP
0
DNPC302
0.1µF
5
6
7
8
R301
DNP
0
R33
Vcc_VCO_OpAmp
C301
1
2
3
4
R29
DNP
0
GND
Mod
GND
GND
R25
DNP
0
GND
GND
Vcc
GND
U3
PLL2 External VCO Loop Filter
16
15
14
13
12
GND
DNP
GND
4
R44
DNP
0
Vcc
Vt
GND
3
6
2
5
1
DNPC12
0.1µF
GND
GND
U5
11
R20
DNP
0
DNPC303
0.1µF
VTUNE2_TP
R55
0
Vcc11_CG3
CLKin_SEL1
VCXO-mode Loop Filter
DNPC2pA2
C1_A2
100pF
47pF
Note: CVHD-950-### is a 4 pin part but with 200 mil pin spacings. So pin
mapping from 6 pin (schematic) to 4 pin footprint is:
1 --> 1, 3 --> 2, 4 --> 3, 6 --> 4
C2_A2
3900pF
CLKin_SEL0
This arrangement also allows for many differential VCXOs to also be used
U7 is alternate footprint for 5x3.2 mm VCXO package
OSCin VCXO
R2_A2
620
ZZ1
C27
R4
49 SDCLKout9_P
Vcc6_PLL1
SDCLKout3*
CLKin1*/Fin*/FBCLKin*
CPout1
32
CPout1
Status_LD1
31
Status_LD1
SDCLKout7*
30
SDCLKout7_N
DCLKout6
SDCLKout7
29
DCLKout6*
28
27
DCLKout6_N
DCLKout6_P
Vcc5_DIG
SDCLKout7_P
26
Status_LD2
47
43
OSCin_P
42
41
40
39
C34
GND
RF*
Vs
NC
Vtune
3
R374
120 FB
2
5
4
3
2
R3_AB1
0
Switch resistor for signal
DNPC8
(shared pad) [C8 and R23]
0.1µF
R68
51
OSCin_1_P
0.1µF
R21
DNP
0
R23
DNP
0
C3_AB1
100pF
OSCin
1
GND_VCXO
VCC_VCXO_TP
Vcc_VCXO
142-0701-806
R18
R13
C6
OSCout_P
37
CLKin0_P
DNPC3 0.1µF
0.1µF
R7
DNP
270
C2
Vcc6_PLL1
35
CLKin1_N
34
CLKin1_P
R8
DNP
51
R3
CLKin0_2_P
DNPC7 0.1µF
0.1µF
4
R6
DNP
270
R14
DNP
51
5
6
S
SD
R38
DNP
51
3
PD
2
SCTDNP NC
R35
DNP
51
BALUN - ADT2-1T+
R2
R17
DNP
270
0
142-0701-806
1
P
0
R15
DNP
270
C11
10uF
CLKin0*
C10
2200pF
120 FB
C9
82pF
1
B1
0
R5
DNP
51
R9
100
C5
0
R11
CLKin0_2_N
Vcc7_OSCout
R375
0
1
4.70k
2pF
C36
C1
1
0
C367
0.1uF
C368
100pF
GND_VCXO
CLKin0
GND_VCXO
0
142-0701-806
Vcc5_DIG
CLKin0 Impedance Matching and Attenuation
VCO_Fout
C18
DNPC16 0.1µF
0.1µF
DNPC15
100pF
C20
R30
FBCLKin*/CLKin1*
1
0
R45
51
0
R31
DNP
270
R32
DNP
270
142-0701-806
CLKin1
R28
DNP
100
Vcc3_SYSREF
DNPC338
470pF
RF
Vcc8_OSCin
CLKin0_N
33
6
GND_VCXO
OSCout_N
38
36
5
R16
DNP
120
DNP
C38
0.1µF
R12
0
5
4
3
2
OSCin_N
1
Vtune
C28
DNP
0.01µF
U2
4
CVHD-950-122.88
2200pF
R69
DNP
0
Vcc9_CP2
44
R65
DNP
0
C304
1000pF
2
R381
Vcc10_PLL2
45
Vs
R306
DNP
0
3
GND
RF*DNP NC
6
R10
DNP
120
R308
DNP
10k
D6
SMV1249-079LF
C32
46
142-0701-806
RF
4.70k
DNP
Status_LD2
C4
33pF
U7
4
5
5
4
3
2
48
DNPC330
33pF
SDIO
Switch resistor for signal
(shared pad) [C4 and R1]
R62
U2 and U7: 4 pin and 6 pin footprints are compatible
Assembly Note
Vcc4_CG2
C14
Status_LD1
R382
DNP
51
DNP
C19 0.1µF
0.1µF
R56
DNP
51
R26
DNP
270
FBCLKin/CLKin1
C13
R24
DNP
18
1
0
R27
DNP
270
DNP
R230
DNP
0
5
4
3
2
25
DCLKout4_N
17
CS*
SCK
SCK
SDIO
DNPC305
33pF
DCLKout4
DCLKout2*
Vcc4_CG2
CLKin1/Fin/FBCLKin
DCLKout4*
DCLKout2
DNP
1
5
4
3
2
CLKin0
SDCLKout3
Y300
DNP
Y301
OSCin*
5
4
3
2
50 SDCLKout9_N
51 DCLKout8_P
DCLKout8
SDCLKout9
SDCLKout9*
54 DCLKout10_P
53
52 DCLKout8_N
DCLKout8*
DCLKout10
Vcc11_CG3
57 SDCLKout11_N
56 SDCLKout11_P
55 DCLKout10_N
DCLKout10*
SDCLKout11
59
58
CLKin_SEL0
CLKin_SEL1
SDCLKout11*
62 DCLKout12_P
61 SDCLKout13_N
60 SDCLKout13_P
SDCLKout13
SDCLKout13*
DCLKout12
LDObyp2
Vcc2_CG1
CS*
DAP PAD
CLKin0*
Vcc2_CG1
DCLKout2_N 16
Vcc7_OSCout
0
LDObyp1
SDCLKout5*
DCLKout2_P 15
OSCout0
Vcc1_VCO
SDCLKout5
SDCLKout3_N 14
OSCout*
NC
24
C37
0.1µF
SDCLKout3_P 13
LMK04828
NC
22
12
C35
10µF
OSCin
Vcc8_OSCin
23
11
OSCin*
SYNC
SDCLKout5_P
9
10
Vcc1_VCO
Status_LD2
RESET
NC
C375
DNP
CPout2
SDCLKout5_N
8
U1
LMK04828
Vcc9_CP2
DCLKout4_P
7
R60
DNP
0
100
R61
51
D1
SMV1249-079LF
Vcc10_PLL2
Vcc3_SYSREF
6
R376
DNP
51
C374
2pF
0.1µF
2200pF
SDCLKout1*
21
SYNC
C33
12pF
SDCLKout1
SDIO
SYNC
DCLKout0*
20
RESET
5
Vcc12_CG0
64
4
SCK
3
SDCLKout1_N
CS*
2
SDCLKout1_P
DCLKout0
19
DCLKout0_N
RESET
C29
100pF
1
18
DCLKout0_P
DCLKout12*
Vcc12_CG0
63 DCLKout12_N
OSCin_1_N
R1
DNP
0
142-0701-806
PLL2_Vtune_AF
FBCLKin/CLKin1 Impedance Matching and Attenuation
Vcc_VCXO_LDO
VTUNE1_TP
VCXO Loop Filter
C2_A1
0.68uF
R34
DNP
0
DNPC2pA1
2.7µF
4
3
V+
DNP
V-
2
C1_A1
0.1µF
Vcc_VCXO_OpAmp
DNPC41
0.1µF
5
R78
DNP
0
R36
1
DNP
0
U4
LMP7731MF
R2_A1
39k
R75
PLL1 Loop Filter
0
Figure 27. LMK04828B
SNAU145A – MAY 2013 – Revised JUNE 2013
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Appendix C: Schematics
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VccPLLPlane
Status_LD1
Status_LD1
R80
DNP
15k
TESTPOINT
Status_LD1_TP
R84
1
R85
0
270
2
DNP
142-0711-201
DNPC43
100pF
R87
DNP
27k
D5
Green
Status_LD1
CLKin Select 0
CLKin Select 1
CLKIN0_SEL_TP
CLKIN1_SEL_TP
R318
R317
TESTPOINT
15k
R319
27k
CLKin_SEL0
15k
R93
DNP
270
Shared pad
R108
DNP
0
R320
27k
TESTPOINT
R79
DNP
270
CLKin_SEL1
VccPLLPlane
TESTPOINT
RESET_TP
D2
D3
Red
SPI HEADER
Red
R109
0
Shared pad
R383
DNP
27k
RESET
R384
27k
R110
DNP
0
R94
VccPLLPlane
TESTPOINT
15k
R51
DNP
27k
R312
SCK
SCK
15k
DNPC306
100pF
SPI
R313
27k
R113
0
10
8
6
4
2
9
7
5
3
1
HEADER_2X5
VccPLLPlane
The pull-down resistors on CS*, SCK, SDIO
pins are to be used only in the case of 5V logic.
TESTPOINT
SDIO
R57
DNP
27k
R315
SDIO
15k
DNPC307
100pF
R316
27k
R322
DNP
27k
R321
SYNC_TP
142-0711-201
SYNC
CS*
R50 15k
1
27k
TESTPOINT
DNP
2
DNPC308
100pF
Status_LD2
R81
15k
Status_LD2_TP
142-0711-201
Status_LD2
R82
1
SYNC
0
DNP
R83
TESTPOINT
270
2
CS*
Status_LD2
R324
15k
VccPLLPlane
TESTPOINT
DNPC309
100pF
R325
27k
DNPC42
100pF
R86
27k
D4
Green
SYNC Level Translation
S1
S2
0.375" Standoff
0.375" Standoff
GND
S3
PCB Number: SV600788
PCB Rev: C
GND
S4
0.375" Standoff
0.375" Standoff
GND
S5
GND
S6
0.375" Standoff
Texas Instruments
PCB
LOGO
0.375" Standoff
GND
PCB
LOGO
ESD Susceptible
GND
Figure 28. Digital
34
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Appendix C: Schematics
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SYSREF CLOCK OUTPUTS
SDCLKout5
SDCLKout3
R124
DNP
51
R102
DNP
51
SDCLKout1_N
0.1µF
R126
240
5
4
3
2
R104
240
R59
DNP
100
SDCLKout3_1_N
SDCLKout3_N
0.1µF
R58
DNP
100
142-0701-806
R142
51
SDCLKout3*
C54
SDCLKout1*
SDCLKout1_1_N 1
1
SDCLKout5*
C60
SDCLKout5_1_N
SDCLKout5_N
R148
DNP
240
5
4
3
2
C48
142-0701-806
142-0701-806
R63
560
GND
1
DNP
0.1µF
5
4
3
2
SDCLKout1
GND
GND
SDCLKout3
0.1µF
R134
240
5
4
3
2
R112
240
R117
DNP
51
SDCLKout3_1_P
SDCLKout3_P
0.1µF
1
R138
DNP
51
SDCLKout5
C64
SDCLKout5_1_P
SDCLKout5_P
R156
DNP
240
5
4
3
2
SDCLKout1_P
SDCLKout1
SDCLKout1_1_P 1
R158
51
142-0701-806
1
DNP
0.1µF
5
4
3
2
C58
C52
142-0701-806
142-0701-806
GND
GND
GND
SDCLKout9
SDCLKout11
R192
DNP
240
DNP
0.1µF
SDCLKout9_1_N
SDCLKout9_N
5
4
3
2
R64
560
142-0701-806
R67
560
1
0.1µF
142-0701-806
R66
560
142-0701-806
1
GND
GND
GND
SDCLKout11
C82
SDCLKout9
C76
SDCLKout7_1_P
1
R200
DNP
240
DNP
5
4
3
2
0.1µF
R182
51
SDCLKout9_1_P
SDCLKout9_P
1
DNP
0.1µF
5
4
3
2
SDCLKout7
C70
SDCLKout7_P
R178
DNP
240
SDCLKout11*
SDCLKout11_1_N
R215
DNP
240
DNP
0.1µF
R206
51
SDCLKout11_1_P
SDCLKout11_P
R222
DNP
240
0.1µF
1
5
4
3
2
R170
DNP
240
1
SDCLKout11_N
5
4
3
2
SDCLKout7_1_N
C78
SDCLKout9*
C72
SDCLKout7*
C66
SDCLKout7_N
R212
DNP
51
R190
51
R164
51
5
4
3
2
SDCLKout7
R228
DNP
51
142-0701-806
142-0701-806
142-0701-806
GND
GND
GND
SDCLKout13
R37
51
SDCLKout13*
C21
SDCLKout13_1_N
SDCLKout13_N
1
DNP
0.1µF
5
4
3
2
R42
DNP
240
142-0701-806
R70
560
GND
SDCLKout13
C25
SDCLKout13_1_P
SDCLKout13_P
1
DNP
0.1µF
5
4
3
2
R52
DNP
240
R72
51
142-0701-806
GND
Figure 29. Clock Outputs 1 of 2
SNAU145A – MAY 2013 – Revised JUNE 2013
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Appendix C: Schematics
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DEVICE CLOCK OUTPUTS AND OSCout
OSCout
R90
DNP
51
OSCout
C44
C23
OSCout_1_P
OSCout_1_2_P
R231
240
0
0.1µF
1
5
4
3
2
OSCout_P
142-0701-806
R40
DNP
100
GND
OSCout*
C46
C24
OSCout_1_N
OSCout_1_2_N
R232
240
0
0.1µF
1
5
4
3
2
OSCout_N
R96
DNP
51
142-0701-806
GND
DCLKout2
DCLKout4
R121
DNP
51
R99
DNP
51
C53
DCLKout0_1_P
0.1µF
DCLKout2_N
R125
240
5
4
3
2
R103
240
1
0.1µF
R76
DNP
100
DCLKout4
DCLKout4_1_P
R147
DNP
240
142-0701-806
R73
560
GND
1
DNP
0.1µF
142-0701-806
R71
DNP
100
142-0701-806
R141
51
C59
DCLKout4_P
5
4
3
2
DCLKout0
C47
DCLKout0_P
DCLKout2*
DCLKout2_1_N1
5
4
3
2
DCLKout0
GND
GND
DCLKout0_N
0.1µF
DCLKout2_P
R133
240
5
4
3
2
R111
240
1
R114
DNP
51
DCLKout2
DCLKout2_1_P 1
0.1µF
R135
DNP
51
DCLKout4*
C63
DCLKout4_1_N
DCLKout4_N
R155
DNP
240
5
4
3
2
DCLKout0_1_N
R157
51
142-0701-806
1
DNP
0.1µF
5
4
3
2
C57
DCLKout0*
C51
142-0701-806
142-0701-806
GND
GND
GND
DCLKout8
DCLKout10
R163
51
DCLKout6
1
5
4
3
2
R88
560
GND
R213
DNP
240
1
R179
51
DCLKout8_1_N
R199
DNP
240
5
4
3
2
0.1µF
R204
51
142-0701-806
GND
DCLKout10*
C81
1
DNP
0.1µF
142-0701-806
GND
1
142-0701-806
GND
DCLKout8*
C75
DCLKout8_N
DNP
5
4
3
2
DCLKout6_1_N
0.1µF
R91
560
GND
DCLKout6*
C69
DCLKout10_1_P
DCLKout10_P
142-0701-806
R89
560
DCLKout10
C77
1
DNP
0.1µF
142-0701-806
DCLKout6_N
R177
DNP
240
DCLKout8_1_P
R191
DNP
240
R209
DNP
51
DCLKout8
C71
DCLKout8_P
DNP
0.1µF
DCLKout10_1_N
DCLKout10_N
R221
DNP
240
0.1µF
1
5
4
3
2
DCLKout6_1_P
R169
DNP
240
5
4
3
2
C65
DCLKout6_P
R187
51
5
4
3
2
DCLKout6
R225
DNP
51
142-0701-806
GND
DCLKout12
R41
51
DCLKout12
C22
DCLKout12_1_P
DCLKout12_P
1
DNP
0.1µF
5
4
3
2
R46
DNP
240
142-0701-806
GND
R92
560
DCLKout12*
C26
DCLKout12_1_N
DCLKout12_N
1
DNP
0.1µF
5
4
3
2
R77
DNP
240
R237
51
142-0701-806
GND
Figure 30. Clock Outputs 2 of 2
36
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Appendix D: Bill of Materials
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12
Appendix D: Bill of Materials
Table 10. Bill of Materials
Item
Designator
Description
Manufacturer
PartNumber
Quantity
1
PCB
Printed Circuit
Board
Any
SV600788C
1
2
C1, C5, C13, C20,
C23, C24, R3,
R3_AB1, R11, R12,
R19, R30, R55,
R75, R82, R84,
R95, R109, R113,
R310, R323, R327,
R329, R331, R334,
R335, R336, R337,
R338, R339, R340,
R346, R349, R364,
R373, R375
RES, 0 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW06030000Z0
EA
36
3
C1_A1, C2, C6,
C18, C19, C21,
C22, C25, C26,
C27, C38, C37,
C44, C46, C47,
C48, C51, C52,
C53, C54, C57,
C58, C59, C60,
C63, C64, C65,
C66, C70, C71,
C72, C75, C76,
C77, C78, C81,
C82, C312, C319,
C346
CAP, CERM, 0.1uF, Kemet
25V, +/-5%, X7R,
0603
C0603C104J3RACT 40
U
4
C1_A2
CAP, CERM, 47pF,
50V, +/-5%,
C0G/NP0, 0603
Kemet
C0603C470J5GAC
TU
1
5
C2_A1
CAP, CERM,
0.68uF, 10V, +/10%, X5R, 0603
Kemet
C0603C684K8PAC
TU
1
6
C2_A2
CAP, CERM,
3900pF, 50V, +/10%, X7R, 0603
MuRata
GRM188R71H392K 1
A01D
7
C3_AB1, C29, C368 CAP, CERM,
100pF, 50V, +/-5%,
C0G/NP0, 0603
Kemet
C0603C101J5GAC
TU
3
8
C4
CAP, CERM, 33pF,
100V, +/-5%,
C0G/NP0, 0603
AVX
06031A330JAT2A
1
9
C9
CAP, CERM, 82pF,
50V, +/-10%,
C0G/NP0, 0603
Kemet
C0603C820K5GAC
TU
1
10
C10, C32, C341,
C375
CAP, CERM,
2200pF, 50V, +/10%, X7R, 0603
Kemet
C0603C222K5RAC
TU
4
11
C11
CAP, CERM, 10uF,
10V, +/-20%, X5R,
0805
Kemet
C0805C106M8PAC
TU
1
12
C33
CAP, CERM, 12pF,
50V, +/-5%,
C0G/NP0, 0603
AVX
06035A120JAT2A
1
13
C34, C374
CAP, CERM, 2pF,
50V, +/-12.5%,
C0G/NP0, 0603
Kemet
C0603C209C5GAC
TU
2
14
C35, C310, C317,
C324, C352
CAP, CERM, 10uF,
10V, +/-10%, X5R,
0805
Kemet
C0805C106K8PAC
TU
5
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Appendix D: Bill of Materials
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Table 10. Bill of Materials (continued)
38
Item
Designator
Description
PartNumber
Quantity
15
C69, C322, C326,
C367
CAP, CERM, 0.1uF, Kemet
25V, +/-10%, X7R,
0603
Manufacturer
C0603C104K3RAC
TU
4
16
C300, C311, C314,
C318, C321, C325,
C337, C342, C343,
C347, C364
CAP, CERM, 1uF,
10V, +/-10%, X5R,
0603
Kemet
C0603C105K8PAC
TU
11
17
C304
CAP, CERM,
Kemet
1000pF, 50V, +/5%, C0G/NP0, 0603
C0603C102J5GAC
TU
1
18
C313
CAP, CERM, 10uF,
6.3V, +/-20%, X5R,
0603
Kemet
C0603C106M9PAC
TU
1
19
C315, C323
CAP, CERM,
0.01uF, 100V, +/10%, X7R, 0603
Kemet
C0603C103K1RAC
TU
2
20
C340
CAP, CERM, 4.7uF, Kemet
10V, +/-10%, X5R,
0603
C0603C475K8PAC
TU
1
21
C350, C351, C359,
C360
CAP, CERM,
0.47uF, 16V, +/10%, X7R, 0603
C0603C474K4RAC
TU
4
22
CLKin0, CLKin0*,
DCLKout0,
DCLKout0*,
DCLKout2,
DCLKout2*,
DCLKout10,
DCLKout10*,
FBCLKin*/CLKin1*,
OSCin, OSCin*,
OSCout, OSCout*,
SDCLKout1,
SDCLKout1*,
SDCLKout3,
SDCLKout3*,
SDCLKout11,
SDCLKout11*
Connector, SMT,
Emerson
End launch SMA 50 Network Power
ohm
142-0701-806
23
23
D1, D6
DIODE VARACTOR Skyworks Inc
15V 20MA SC-79
SMV1249-079LF
2
24
D2, D3
LED 2.8X3.2MM
565NM RED CLR
SMD
Lumex
Opto/Components
Inc.
SML-LX2832IC
2
25
D4, D5
LED 2.8X3.2MM
565NM GRN CLR
SMD
Lumex
Opto/Components
Inc.
SML-LX2832GC
2
26
J1
CONN TERM BLK
Weidmuller
PCB 5.08MM 2POS
OR
1594540000
1
27
R2, R13, R332
RES, 0 ohm, 5%,
0.125W, 0805
Vishay-Dale
CRCW08050000Z0
EA
3
28
R2_A1
RES, 39k ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW060339K0JN 1
EA
29
R2_A2
RES, 620 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW0603620RJN 1
EA
30
R4, R9
RES, 100 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW0603100RJN 2
EA
31
R18, R305, R307,
R342, R343, R344,
R345, R347, R354,
R358, R371, R374
FB, 120 ohm, 500
mA, 0603
Murata
BLM18AG121SN1D 12
Kemet
LMK04826/28 User’s Guide
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Appendix D: Bill of Materials
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Table 10. Bill of Materials (continued)
Item
Designator
Description
Manufacturer
PartNumber
32
R37, R41, R45,
R61, R68, R72,
R141, R142, R157,
R158, R163, R164,
R179, R182, R237
RES, 51 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW060351R0JN 15
EA
33
R50, R86, R313,
R316, R319, R320,
R325, R384
RES, 27k ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW060327K0JN 8
EA
34
R62, R381
RES, 4.70k ohm,
1%, 0.1W, 0603
Yageo America
RC0603FR-074K7L
35
R63, R64, R66,
RES, 560 ohm, 5%,
R67, R70, R73,
0.1W, 0603
R88, R89, R91, R92
Vishay-Dale
CRCW0603560RJN 10
EA
36
R81, R94, R312,
R315, R317, R318,
R321, R324
RES, 15k ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW060315K0JN 8
EA
37
R83, R85
RES, 270 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW0603270RJN 2
EA
38
R100, R101, R105,
R106, R107
RES, 0 ohm, 5%,
0.063W, 0402
Vishay-Dale
CRCW04020000Z0
ED
39
R103, R104, R111,
R112, R125, R126,
R133, R134, R231,
R232
RES, 240 ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW0603240RJN 10
EA
40
R333, R341
FB, 120 ohm, 500
mA, 0402
TDK
MMZ1005Y121C
41
R350, R360, R369
RES, 51k ohm, 5%,
0.1W, 0603
Vishay-Dale
CRCW060351K0JN 3
EA
42
R351
RES, 2.00k ohm,
1%, 0.1W, 0603
Vishay-Dale
CRCW06032K00FK 1
EA
43
R356
RES, 866 ohm, 1%,
0.1W, 0603
Vishay-Dale
CRCW0603866RFK 1
EA
44
S1, S2, S3, S4, S5,
S6
0.375" Standoff
VOLTREX
SPCS-6
6
45
SPI
Low Profile Vertical
Header 2x5 0.100"
FCI
52601-G10-8LF
1
46
U1
47
U2
122.88 MHz VCXO
CVHD-950-122.88
1
48
U302
Micropower 800mA Texas Instruments
Low Noise "Ceramic
Stable" Adjustable
Voltage Regulator
for 1V to 5V
Applications, 8-pin
LLP, Pb-Free
LP3878SDADJ/NOPB
1
49
U303, U305
Ultra Low Noise,
150mA Linear
Regulator for
RF/Analog Circuits
Requires No
Bypass Capacitor,
6-pin LLP, Pb-Free
Texas Instruments
LP5900SD3.3/NOPB
2
50
Vcc
Connector, TH,
SMA
Emerson Network
Power
142-0701-201
1
LMK04826
LMK04828
Texas Instruments
Crystek
SNAU145A – MAY 2013 – Revised JUNE 2013
Submit Documentation Feedback
LMK04826BISQ
LMK04828BISQ
Quantity
2
5
2
1
LMK04826/28 User’s Guide
Copyright © 2013, Texas Instruments Incorporated
39
Appendix E: Properly Configuring LPT Port
13
www.ti.com
Appendix E: Properly Configuring LPT Port
When trying to solve any communications issue, it is most convenient to verify communication by
programming the POWERDOWN bit to confirm normal or low supply current consumption of the
evaluation board.
13.1 LPT Driver Loading
The parallel port must be configured for proper operation. To confirm that the LPT port driver is
successfully loading click “LPT/USB” → “Check LPT.” If the driver properly loads then the following
message is displayed in Figure 31:
Figure 31. Successfully Opened LPT Driver
Successful loading of LPT driver does not mean LPT communications in CodeLoader are setup properly.
The proper LPT port must be selected and the LPT port must not be in an improper mode.
NOTE: The PC must be re-booted after install for LPT support to work properly.
13.2 Correct LPT Port/Address
To determine the correct LPT port in Windows, open the device manager (On Windows XP, Start →
Settings → Control Panel → System → Hardware tab → Device Manager) and check the LPT port under
the Ports (COM & LPT) node of the tree. It can be helpful to confirm that the LPT port is mapped to the
expected port address, for instance to confirm that LPT1 is really mapped to address 0x378. This can be
checked by viewing the Properties of the LPT1 port and viewing Resources tab to verify that the I/O
Range starts at 0x378. CodeLoader expects the traditional port mapping, shown in Table 11:
Table 11. LPT Port Addresses
Port
Address
LPT1
0x378
LPT2
0x278
LPT3
0x3BC
If a non-standard address is used, use the “Other” port address in CodeLoader and type in the port
address in hexadecimal. It is possible to change the port address in the computer’s BIOS settings. The
port address can be set in CodeLoader in the Port Setup tab as shown in Figure 31.
Figure 32. Selecting the LPT Port Address
40
LMK04826/28 User’s Guide
SNAU145A – MAY 2013 – Revised JUNE 2013
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Appendix F: USB2UWIRE-IFACE under Windows 7
www.ti.com
13.3 Correct LPT Mode
If communications are not working, then it is possible the LPT port mode is set improperly. It is
recommended to use the simple, Output-only mode of the LPT port. This can be set in the BIOS of the
computer. Common terms for this desired parallel port mode are “Normal,” “Output,” or “AT.” It is possible
to enter BIOS setup during the initial boot up sequence of the computer.
14
Appendix F: USB2UWIRE-IFACE under Windows 7
USB2ANY provides native support for Windows 7. In order to operate in Windows 7 using the
USB2UWIRE-IFACE , reference the following instrucions to use a Windows XP Virtual Machine.
14.1 (One-time step) Download and install Microsoft Windows XP mode for Windows 7
Download and install Microsoft’s Windows XP Mode for the Windows 7 operating system by following this
link: http://www.microsoft.com/windows/virtual-pc/download.aspx
Follow all of the installation steps listed on Microsoft’s website, as shown below.
Figure 33. Installation Steps for Microsoft Windows XP Mode for Windows 7
14.2 Launch Microsoft XP Mode
Launch Microsoft XP Mode by clicking on Start > All Programs > Windows Virtual PC > Windows XP
Mode, as shown below.
SNAU145A – MAY 2013 – Revised JUNE 2013
Submit Documentation Feedback
LMK04826/28 User’s Guide
Copyright © 2013, Texas Instruments Incorporated
41
Appendix F: USB2UWIRE-IFACE under Windows 7
www.ti.com
Figure 34. Launch Microsoft XP Mode
14.3 (One-time step) Install the ALP software from within Windows XP
Once Windows XP is running, install the CodeLoader software by running the executable file.
14.4 Attach the USB device to your computer
Figure 35. Attach USB
42
LMK04826/28 User’s Guide
SNAU145A – MAY 2013 – Revised JUNE 2013
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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