1626 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 An Insight into the Switching Process of Power MOSFETs: An Improved Analytical Losses Model Miguel Rodrı́guez, Student Member, IEEE, Alberto Rodrı́guez, Student Member, IEEE, Pablo Fernández Miaja, Student Member, IEEE, Diego González Lamar, Member, IEEE, and Javier Sebastián Zúniga, Member, IEEE Abstract—The piecewise linear model has traditionally been used to calculate switching losses in switching mode power supplies due to its simplicity and good performance. However, the use of the latest low voltage power MOSFET generations and the continuously increasing range of switching frequencies have made it necessary to review this model to account for the parasitic inductances that it does not include. This paper presents a complete analytical switching loss model for power MOSFETs in low voltage switching converters that includes the most relevant parasitic elements. It clarifies the switching process, providing information about how these parasitics, especially the inductances, determine switching losses and hence the final converter efficiency. The analysis presented in this paper yields two different types of possible switching situations: capacitance-limited switching and inductance-limited switching. This paper shows that, while the piecewise linear model may be applied in the former, the proposed model is more accurate for the latter. Carefully-obtained experimental results, described in detail, support the analytical results presented. Index Terms—Losses, modeling, MOSFETs, switched mode power supplies. I. INTRODUCTION HE continuously increasing range of operating frequencies in actual power converters has caused switching losses to greatly determine the final performance of a design. On the one hand, switching losses can be accurately calculated using physical simulation software or circuit simulations that use complete MOSFET models [1]; unfortunately, both methods are quite time consuming, and the information required to obtain precise results is not always available for many designers. Besides, as each simulation only provides valid results for the case under study, neither general conclusions nor a clear physical insight into the switching process are easily obtained from these tools. On the other hand, analytical switching loss models (usually based upon certain simplifications) provide less accurate results, but enable the designer to make fast calculations, thus allowing almost immediate comparison between different operating conditions or between different semiconductor performances. Furthermore, analytical models also provide physical T Manuscript received June 23, 2009; revised November 3, 2009. Current version published June 4, 2010. This work has been supported by the Spanish Ministry of Science and Innovation under Grants AP2006-04777, AP2008-03380, and project TEC-2007-66917. Recommended for publication by Associate Editor E. Santi. The authors are with the Power Supply Systems Group, Department of Electrical and Electronic Engineering, University of Oviedo, Gijón 33204, Spain (e-mail: rodriguezmiguel.uo@uniovi.es; rodriguezalberto@uniovi.es; fernandezpablo.uo@uniovi.es; gonzalezdiego@uniovi.es; sebas@uniovi.es). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2010.2040852 insight into the switching process, allowing designers to acquire in-depth knowledge of the switching loss mechanisms. The classical analytical model, or piecewise-linear model [2], is based on the assumption that MOSFET’s capacitances completely determine its switching behavior. However, it does not account for parasitic inductances. The latest generation of lowvoltage power MOSFETs exhibit an extremely good switching performance, mainly due to their low capacitances and increased transconductances; this key fact means that parasitic inductances limit the switching process in practice. The classical model thus needs a review to account for the effect of these parasitics (actual values for the parasitic inductances vary from around 15 nH in a classic TO-220 package to less than 1 n in the DirecFET package used by International Rectifier). Several detailed models that include such parasitics have already been proposed, including either a fully analytical treatment [3], [4] or a more empirical approach [5]. This issue has also been addressed in [6]– [8], but applied to a current source resonant driver. This paper presents an analytical loss model for power MOSFETs in actual low-medium voltage (< 40 V) switching converters that includes all the parasitics. It is obtained by solving the equivalent circuits during the switching transitions; all the approximations used are clearly stated, and the solutions are presented in a relatively simple form. The model is easy to understand and provides a deep insight into the switching process. The paper is organized as follows: first, the motivation and basis of the model are given. Then, the model and the procedure employed to obtain all the waveforms are fully explained. Finally, the proposed model is compared to the classical model and tested by means of several experiments. II. MOTIVATION AND BASIS OF THE MODEL Fig. 1(a) shows a synchronous buck converter. During switching transitions, the output inductance L may be considered to be a current source, and the output capacitor C may be considered a constant voltage source. Such assumptions yield the circuit in Fig. 1(b), from which the output voltage has been removed as it is in series with a current source. As the dead time control used in synchronous buck converters causes the freewheeling diode Df either to be conducting before the high-side MOSFET, HS, turns on or to start conducting after HS turns off, the low-side MOSFET, LS, does not play any role during the switching transitions, and it can be removed from the circuit. Furthermore, the said dead time forces LS to switch in zero voltage conditions, thus adding no extra losses. Thus, only HS has to be considered in the switching loss analysis. After taking into account such considerations and adding the parasitic capacitances of HS, the 0885-8993/$26.00 © 2010 IEEE Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL Fig. 1. (a) Synchronous buck converter; (b) equivalent circuit for the switching transition; (c) intermediate circuit after the LS MOSFET has been removed and the parasitic capacitances of HS have been added; (d) final equivalent circuit obtained from a rearrangement of elements in (c). 1627 Fig. 2. (a) Typical turn-ON waveforms in the classical model; (b) equivalent circuit with an extra parasitic drain inductance. circuit in Fig. 1(c) is obtained. Finally, a rearrangement of the elements in Fig. 1(c) yields the circuit in Fig. 1(d). The same transformations can easily be applied to boost or buck–boost converters, yielding exactly the same final equivalent circuit; the only difference is that the values of voltages and currents change (e.g., in the boost converter the voltage source value is Vout and the current source value is Iin ). A synchronous buck converter will be used in the following sections to present the model. The major advantage of this approach arises from a practical issue: in a conventional buck converter, conduction losses would mask switching losses due to the high-conduction losses caused by the freewheeling diode Df , thus hindering any laboratory measurement aimed at testing the proposed model. However, it is worth to comment that the analysis is still directly applicable to a conventional buck converter: the only special concern should be that the model would become more difficult to verify due to the aforementioned issues. A. Range of Application of the Classical Model The classical model has been widely used by power supply designers. It provides quite accurate results, especially bearing in mind its simplicity. It also provides a simple, comprehensive approach to the switching process. However, careful analysis of the model shows that it is based on the assumption that the switching transitions are strongly determined by the parasitic capacitances. Fig. 2(a) shows the typical turn-ON waveforms in the piecewise-linear model. First, the drain current increases linearly until reaching its final value Iout ; then, the drain-source voltage drops to 0 V. The procedure is easy to understand: as the freewheeling diode of Fig. 1(d) is initially forward biased, it forces the drain-source voltage to remain constant until the MOSFET carries all the output current. The turn-OFF process is very similar, but the voltage increase takes place before the current drop. This switching behavior can be referred to as capacitance limited. Fig. 2(b) shows the equivalent circuit of Fig. 1(d) with an extra inductance in the drain terminal of the MOSFET. This inductance limits the drain current change rate, and thus nothing stops the drain-source voltage from changing before the Fig. 3. (a) Simplified physical view of a power MOSFET; (b) simplified 3-D view of the silicon die with the package. current. In this situation, the assumptions of the classical model are no longer valid. B. Basis of the Proposed Model The proposed model includes the most relevant parasitics present in actual power MOSFETs. Fig. 3(a) shows a simplified physical view of a MOSFET. Three intrinsic parasitic capacitances are considered in this model: the gate-source capacitance, the gate-drain capacitance, and the drain-source capacitance. As both the drain-source capacitance and the gate-drain capacitance are associated with a reverse-biased p-n junction, they change with the applied voltage. This change is modeled by the following equation: C0 (1) C (v) = v γ 1+ K Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1628 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 4. Equivalent MOSFET circuit including internal and major external parasitics. beginning of each substage, the equivalent circuit with its corresponding initial conditions is stated. Capacitance values are chosen using (1) in accordance with the initial voltage over the capacitance at the beginning of the substage; though this procedure might yield discontinuities at the substage boundaries, it will provide more accurate results when calculating switching losses and the obtained waveforms will also be more meaningful from a physical point of view. The time-domain equations of the equivalent circuit are then obtained and solved using Laplace transforms. Once the drain current and the internal drain-source voltage are known, switching losses are calculated in terms of energy by integrating the product of those waveforms, and then the energy is multiplied by the switching frequency fsw . In certain substages, it is possible to obtain equations that allow the energy losses to be directly found (without an integration procedure). Tables I and II summarize all the relevant equations. As the final conditions of one substage are used as the initial conditions for the following, and to simplify the use of Laplace transforms, the state variables are chosen such that their initial condition is zero in each substage. Mathematically, x being a state variable, then x (t = 0) = 0. The initial conditions are included in the circuits and in the corresponding equations as independent voltage sources (for the capacitances) or current sources (for the inductances), but are not drawn in most of the equivalent circuits for the sake of clarity. The actual voltages and currents in the circuits (electrical variables) are noted with an apostrophe, while the state variables are noted without the apostrophe. It is straightforward to find one from the other Fig. 5. Final equivalent circuit used to obtain the proposed model, along with the electrical variables. x (t) = x (t) + x (0) . where K and γ are two adjustment parameters extracted from the capacitance versus voltage curve that can be found in the datasheet of the MOSFET, and C0 is the 0 V capacitance value. The gate-source capacitance remains approximately constant regardless of the applied voltage. The model also includes several parasitic inductances that can appear for different reasons. Fig. 3(b) shows the silicon die together with the MOSFET package. The pad parasitic inductances and the internal bondings between the silicon die and the package pads contribute to the total parasitic inductance. Current packaging technology tries to minimize such inductances by directly connecting the die with almost noninductive pads, achieving inductances as low as 0.1 nH [9]. The layout of the printed circuit board also contributes slightly to the inductance. Fig. 4 shows the equivalent circuit resulting from the previous considerations. The final circuit model used to analyze the switching process is shown in Fig. 5. All the parasitic inductances in series in each terminal of the MOSFET are added and thus represented as one single element. The gate circuit resistance Rg is made up of the gate driver equivalent resistance and an internal resistance due to the gate contact. The internal nodes are Gint , Dint , and Sint , while the final external nodes, which include the effect of all the parasitic inductances are G, D, and S. The procedure to obtain the model equations is as follows: first, the theoretical analysis is divided into two different stages, the turn-ON and turn-OFF transitions. Within each transition, different substages arise; these are treated separately. At the (2) Furthermore, the initial time is chosen as zero at the beginning of each substage. The ultimate goal of this paper is to obtain relatively simple and handy analytical expressions of voltage and current waveforms that enable the designer to easily calculate switching losses using a conventional spreadsheet. A simple model for MOSFET behavior must be used to achieve such objective. Thus, the MOSFET is considered to be a resistance, an open circuit or a dependent current source in all the analytical calculations presented in this paper. The behavior as a dependent current source (controlled by the voltage between Sint and Gint ) is described by (3). (3) ichannel = gm vgs − VTH gm and VTH being the MOSFET transconductance and the threshold voltage, respectively. Obviously, modeling MOSFET behavior using (3) provides results with limited accuracy. However, its use provides a physical insight into the switching process that would be very difficult to obtain if more complicated expressions were used. III. TURN-ON TRANSITION The equivalent circuit at the beginning of the turn-ON transition is shown in Fig. 6. As the freewheeling diode is forward biased, the voltage Vin is applied over the MOSFET equivalent circuit and its parasitics. A detailed analysis of this circuit leads to the four different substages described in the following sections. Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL 1629 TABLE I SUMMARY OF LOSS CALCULATIONS DURING TURN-ON A. Substage I During substage I, the gate-source equivalent capacitance is charged until it reaches VTH . As the MOSFET is open circuited, approximately no drain current flows in the circuit and the drainsource voltage remains constant. Thus, only the gate circuit must be considered. The equivalent circuit is shown in Fig. 7. The initial conditions for the electrical variables are: ig (0) = 0 (10) vgs (0) = 0 . (11) From the circuit in Fig. 7, the following equations are obtained: dig Ls Ld + ig Rg + vgs (12) Vg = Lg + Ls + Ld dt ig = (Cgs + Cgd ) dvgs . dt (13) Applying Laplace transforms to (12) and (13) and solving for vg s yields vgs (s) = Vg 1 2 s Leq Ceq s + Rg Ceq s + 1 Leq and Ceq now being Ls Ld Leq = Lg + Ls + Ld (14) Ceq = (Cgs + Cgd ) . The inverse Laplace transform of (14) is shown in Table I as (4). The current ig can be obtained from (12) and (13), following the same procedure. This current, as shown in Table I as (5), is used to calculate the initial current for the following substage. As the MOSFET is not activated, there is no power loss during this period, except for the losses in the gate drive circuit that are included as a separate term in the final loss calculations. Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1630 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 TABLE II SUMMARY OF LOSS CALCULATIONS DURING TURN-OFF Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL 1631 A total of seven differential equations can be obtained from the circuit in Fig. 8, one for each state variable in the circuit (yielding six equations) and (3) being the seventh. This set of differential equations can be reduced to four by eliminating three state variables: the current through the source inductance is , the channel current ichannel , and the voltage across the gate-drain capacitance vdg . The remaining set of equations is Vg − Vth = (ig + Ig 1 ) Rg did dig dig + vgs + Ls + dt dt dt did did dig + Ls + 0 = vds + Ld dt dt dt dvds dvgs dvgs = ig + Ig 1 + Cgd − Cg s dt dt dt dvds dvgs dvds − + gm vgs . id = Cgd + Cds dt dt dt + Lg Fig. 6. Equivalent circuit at the beginning of the turn-ON transition. Fig. 7. Equivalent circuit during substage I. Fig. 8. Equivalent circuit during substage II. (29) (30) (31) (32) As this set of equations is, in general, coupled, a simple analytical solution cannot be easily found. However, considering the typical values of the capacitances and transconductances in modern low-voltage power MOSFETs, it can be concluded that the channel current will increase very fast, rapidly discharging the drain-source capacitance. The parasitic inductances stop the drain current from increasing, thus allowing Cds to be discharged by the channel current. The drain current id and its derivatives can be neglected. B. Substage II When vgs reaches VTH , the MOSFET channel starts conducting. Equation (3) then applies, and the channel current is directly proportional to Vgs − VTH . Fig. 8 shows the equivalent circuit for this substage. The initial conditions are: with Ig 1 (0) = VTH vgs (24) vgd (0) = Vin − VTH (25) vds (0) = Vin (26) id (0) = 0 (27) ig is (0) = (0) = Ig 1 being the initial current in the gate circuit. (28) Equation (34) is no longer needed, and the other three equations are uncoupled. Thus, the remaining set of equations can be solved to find voltages and currents in a simple form. Using Laplace transforms, vgs (s) is obtained as vgs (s) = · 1 s Vg − Vth + Ig 1 Leq s s2 (Leq Ceq ) + s (Rg Ceq + (M − 1) (Leq /Rg )) + M Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. (37) 1632 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 9. Equivalent circuit during substage III. with M , Leq and Ceq now being M = 1 + Rg gm Cgd Cgd + Cds Leq = Lg + Ls Ceq = Cgs + Cgd Cds . Cgd + Cds The inverse Laplace transform of (37) is shown in Table I as (6). The drain-source voltage state variable can also be obtained by applying Laplace transforms to vds gm vds (s) = 2 s (Cgd + Cds ) · (Vg − Vth + Ig 1 Leq s) (s(Cgd /gm ) − 1) . (38) s2 (Leq Ceq ) + s (Rg Ceq + (M − 1) (Leq /Rg )) + M The inverse Laplace transform of (38) is shown in Table I as (7). The power loss during this substage has to be found by integrating the product ichannel vds . The end of this substage takes place when the drain-source voltage reaches approximately 0 V. If the input voltage were higher than a few tens of volts, Vds would not reach 0 V, but would tend to reach an intermediate voltage. As the present analysis is limited to input voltages below approximately 40 V, this situation is not considered and Vds will drop to 0 V in most practical situations. C. Substage III After the drain-source voltage reaches approximately 0 V, the MOSFET starts behaving as a resistor. Fig. 9 shows the equivalent circuit. The initial condition is id (0) ≈ 0 . (39) Thus, the drain current is approximately determined by the input voltage source and the parasitic inductances id ≈ Vin t. Ld + Ls (40) Once again, the state variable id and the actual drain current id are the same. As this substage lasts for a short period of time and Rds, ON is usually very low, switching losses can be neglected. This substage finishes when the drain current reaches the output current. D. Substage IV This substage, which is usually called the reverse recovery period, has been extensively analyzed in [3]. When the drain current reaches the output current, the reverse recovery period Fig. 10. Equivalent circuits during substage IV. The initial current through the inductances has been drawn as an independent current source: (a) equivalent circuit at the beginning of substage IV; (b) equivalent circuit after an appropriate rearrangement of elements in (a); (c) equivalent circuit when the freewheeling diode becomes capable of blocking voltage, i.e., when the drain current has reached its maximum value Ip e a k ; (d) equivalent circuit after an appropriate rearrangement of elements in (c). begins. Fig. 10(a) shows the equivalent circuit at the beginning of this period. The freewheeling diode is unable to block reverse voltage until a certain amount of charge has been removed from its junction. Thus, the drain current increases until it reaches a certain peak current Ip eak ; at this moment, the charge has been removed from the diode junction and it becomes capable of blocking reverse voltage. Fig. 10(c) shows the equivalent circuit at this moment, CD being the equivalent freewheeling diode capacitance. A resonant period then begins, at the end of which the capacitance is charged to Vin and the current through the inductance is Iout once again. Fig. 11 shows the definition of the reverse recovery charge Qrr and the reverse recovery time trr , under common test conditions. The reverse recovery charge is the total charge that has to be provided to the diode junction until the voltage across it reaches its steady-state value and the current through the diode drops to 0 A. The charge provided to the equivalent diode capacitance during the resonant period is hence included in the term Qrr . This is the major difference between the present analysis and previously presented results. The energy stored in the circuit at the beginning of substage IV is 1 2 (41) EL = (Ls + Ld ) Iout 2 EC D = 0 . (42) Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL 1633 As CD depends on the applied voltage, (47) can be rewritten as 1 Eloss = Vin Qrr − QD Vin 2 (48) with QD being the total charge supplied to the diode junction; this charge can be calculated integrating the capacitance versus voltage graph. Noteworthily, significant reverse recovery parameters are very difficult to calculate; for instance, Qrr strongly depends on Iout and on the rate of change of the current, see, e.g., [10]. If the freewheeling diode is a Schottky diode, which suffers almost no reverse recovery effects, then (47) becomes Qrr Eloss = Vin (Vin CSchottky ) 1 1 − CSchottky Vin2 = CSchottky Vin2 2 2 (49) with CSchottky being the Schottky diode equivalent capacitance. Fig. 11. (a) Test circuit for reverse recovery charge and reverse recovery time. At time t0 , when the forward current through the diode is IF , switch S 1 opens and switch S 2 closes; (b) current through the diode. When the current reaches Ip eak , the energy stored in the inductance is EL ,p eak = 1 (Ls + Ld ) Ip2 eak . 2 (43) The energy provided by the voltage source during said period is EV i n = Vin Qrr,1 (44) with Qrr,1 being the part of Qrr that is removed from the diode before the current reaches Ip eak . Thus, the energy loss is Eloss,1 = Vin Qrr,1 − 1 2 (Ls + Ld ) Ip2 eak − Iout . 2 (45) During the resonant period, the energy stored in the induc2 tance changes from 12 (Ls + Ld )Ip2 eak to 12 (Ls + Ld )Iout , so the net energy provided to the inductance during the whole substage is zero. The energy loss during the resonant period is Eloss,2 1 = Vin Qrr,2 − CD Vin2 2 1 + (Ls + Ld ) Ip2 eak − I02 2 (46) with Qrr,2 being the part of Qrr that is needed to charge the equivalent parasitic diode capacitance once it is able to block reverse voltage. The second term in (46) stands for the final energy stored in the diode parasitic capacitance. The total energy loss is thus given by (47) Eloss = Eloss,1 + Eloss,2 = Vin (Qrr,1 + Qrr,2 ) 1 1 − CD Vin2 = Vin Qrr − CD Vin2 . 2 2 (47) E. Example Waveforms Fig. 12 shows a set of example waveforms provided by the model, using typical MOSFET parameters. Fig. 12(a) shows the drain to source voltage and the channel current, as well as the instantaneous power in the channel, during the first three substages (the reverse recovery substage has not been included). It can be seen that, as long as the reverse recovery process is not taken into account, significant power loss only takes place during substage II, which lasts for a relatively short period. Thus, the model suggests that, when an inductance-limited switching takes place, there are small turn-ON losses. Furthermore, as stated in [11], there is no need to include the rather arbitrary output capacitance loss term, 12 Cds Vin2 . Fig. 12(b) shows the gate to source voltage; it can be seen that the Miller effect takes place during substage II, and that it is predicted by the analytical model. The gate to source voltage is essentially equal to that of the classical model and to the waveforms found in conventional MOSFET datasheet. IV. TURN-OFF TRANSITION The equivalent circuit at the beginning of the turn-OFF transition is shown in Fig. 13. As the freewheeling diode is reverse biased, the current Iout circulates through the MOSFET and the parasitic inductances. A detailed analysis of this circuit leads to the five different substages described in the following sections. A. Substage I The gate circuit discharges the gate-source equivalent capacitance. Fig. 14 shows the equivalent circuit during this period. The initial conditions are (0) = Vg vgs (50) ig (0) = 0 . (51) Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1634 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 12. (a) Turn-ON example waveform (the reverse recovery period is not included). The sudden change in the channel current is a consequence of the approximations that were made during the analysis; (b) gate to source voltage example waveform. The Miller effect takes place during substage II and causes the actual channel current waveform. Fig. 14. Equivalent circuit during substage I. Fig. 15. Equivalent circuit during substage II. The inverse Laplace transform of (54) is shown in Table II as (15). The current ig can be obtained from (52) and (53), following the same procedure. This current, as shown in Table II as (16), is used to calculate the initial current for the following substage. Even though the MOSFET is carrying the output current, this period lasts for a short time and the losses can be neglected. Substage I finishes at a time t1 , when the MOSFET enters into the linear region, where (3) applies. Thus, t1 can be calculated as vgs (t1 ) = −Vg + VTH + Iout . gm (55) B. Substage II Fig. 13. Equivalent circuit at the beginning of the turn-OFF transition. From the circuit in Fig. 14, the following equations can be easily obtained: dig + ig Rg + vgs −Vg = (Lg + Ls ) dt dvgs . ig = (Cgs + Cgd ) dt Fig. 15 shows the equivalent circuit during this period. The channel current suddenly decreases, thus causing the excess current Iout − ichannel charging the MOSFET capacitances. The initial conditions are (0) = VTH + vgs (52) Iout vdg (0) = − VTH + gm (53) (0) ≈ 0 vds Using Laplace transforms, vgs is found Vg 1 vgs (s) = − s Leq Ceq s2 + Rg Ceq s + 1 ig (0) = −Ig (54) id Ceq = Cgs + Cgd . with Ig 2 (56) (57) (58) (59) 2 (0) = Iout is (0) = Iout − Ig Leq and Ceq now being Leq = Lg + Ls Iout gm (60) 2 being the initial current in the gate circuit. Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. (61) RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL 1635 The circuit equations are the following: dig 0 = (ig + Ig 2 ) Rg + Lg dt diL s Iout − vgs − VTH + + Ls gm dt vds = vgs + vgd ig + Ig 2 (62) (63) + Cgs dvgs dvgd = Cgd dt dt dvds dvgd = ichannel + Cgd dt dt ig + is = 0 . Iout − Cds (64) (65) (66) These equations can be solved directly using Laplace transforms to find vgs vgs (s) = − · 1 s sLeq Ig 2 + (Vth + (Iout /gm )) Leq Ceq s2 + (Rg Ceq + (M − 1) (Leq /Rg )) s + M (67) M = 1 + Rg gm Ceq t→∞ Cds Cgd = Cgs + Cds + Cgd s→0 C. Substage III has reached Vin and the At the beginning of this substage, vds freewheeling diode becomes forward biased. Fig. 16(a) shows the equivalent circuit during this period. The initial conditions are (0) = Iout (68) is (0) ≈ Iout (69) vds (0) = Vin . Iout gm Iout (M − 1) − VTH gm . (72) M In this substage, the initial conditions have been represented by independent voltage and current sources in the circuit in Fig. 16(a); instead of solving the circuit equations, a rearrangement of these sources easily yields the circuit in Fig. 16(c). Fig. 16(c) shows that the final equivalent circuit is a simple parallel resonant circuit. As the current and voltage waveforms in this circuit are oscillating, it seems clear that the proposed approximation is valid as long as the substage lasts for a time shorter than half a resonant period. vds is easily found from Fig. 16(c) = Applying the inverse Laplace transform to (67) yields (17) in Table II. The results are very similar to those obtained in Section III-B. The drain-source voltage can be obtained from (62)–(66) using the same procedure. The result is shown in Table II as (18). This period ends when the drain-source voltage reaches Vin . The channel current could reach 0 A before that moment; such a situation will be addressed in Section IV-F. ichannel (0) = Ich,∞ t→∞ = lim svgs + VTH + Cgd . Cgd + Cds id using (67) and the final value theorem Ich,∞ = lim ichannel = lim gm Vgs (t) with M , Leq , and Ceq being the same as in Section III-B Leq = Ls + Lg Fig. 16. (a) Equivalent circuit during substage III; (b) intermediate circuit obtained by changing the position of the current sources; (c) final equivalent circuit during substage III. (70) (71) (t) = Vin + (Iout − Ich,∞ ) Ld ω0 sin (ω0 t) vds with ω0 being ω0 = 1 (Ls + Ld ) Cds . (74) This substage ends when the drain current reaches the channel current Ich,∞ . At this moment, the drain-source voltage has reached its peak voltage Vds,p eak . This value can easily be calculated once t3 is known. (t3 ) . Vds, p eak = vds As the drain inductance impedes a sudden change in the drain current, the drain-source voltage continues increasing. It is assumed that the gate voltage remains constant during this period, and as does the channel current. The latter can be approximated (73) (75) D. Substage IV During this period, the drain current continues decreasing toward zero, forced by the voltage difference that exists between Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1636 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 17. (a) Equivalent circuit during substage IV; (b) equivalent circuit for the resonant turn-OFF stage (substage V). Vds, p eak and Vin . As the current that charged Cds to Vds, p eak was the difference between the drain and the channel current, there will not be a high amount of current to change Vds during this period. Thus, Vds is considered to remain approximately equal to Vds, p eak during this substage. In order to simplify the analysis, the channel current is assumed to decrease as if it were controlled by the voltage source Vin , instead of by the gate-source voltage. The power loss can thus be obtained as Ploss = Vds ichannel dt ≈ Vds, p eak ichannel dt . (76) Fig. 17(a) shows the equivalent circuit. Thus, the channel current can be approximated as Vds, p eak − Vin t. ichannel (t) = Ich,∞ − Ls + Ld (77) E. Substage V A resonant stage begins when the channel current reaches 0 A; the MOSFET stops conducting current and becomes an open circuit. The gate circuit continues discharging Cgs and Cgd more or less independently from the rest of the circuit. At the same time, the resonant circuit formed by Ls + Ld and Cds starts oscillating until it reaches its steady-state value. The equivalent circuit is shown in Fig. 17(b). R stands for the equivalent resistance that dumps the oscillations, which is mainly made up of the circuit tracks high-frequency resistance and the parasitic inductance and capacitance high-frequency equivalent resistances. The loss calculations during this substage are identical to those in Section III-D. Once again, losses can be calculated by considering the energy stored at the beginning and the end of the substage. The energy stored at the beginning is EL = 0 EC ,i = (78) 1 Cds (Vds, p eak )2 . 2 (79) The energy stored at the end of the period is EL = 0 EC ,f = 1 Cds Vin2 . 2 (80) (81) Fig. 18. Turn-OFF example waveform. The energy provided by the voltage source is EV in = Vin Cds (Vin − Vds, p eak ) (82) an equation that shows that some energy has been returned to the input source. Finally, the energy loss is Eloss = EV in − (EC ,f − EC ,i ) 1 = Cds Vp2eak + Vin2 − Cds Vp eak Vin . (83) 2 The latter expression is the same as the one obtained in [3]. F. Substage III: Drain Current Drops to Zero Before vds reaches Vin As previously stated in Section IV-B, the channel current could drop to 0 A during substage II, thus causing a sudden end of said substage. This is likely to happen if Iout is relatively small. In that case, the MOSFET becomes open circuited and the analysis is straightforward; switching losses during the rest of the turn-OFF transition can be approximated by considering that all the energy stored in the parasitic inductances is lost during the resonant period 1 2 (Ls + Ld ) Iout . (84) 2 Equation (84) neglects the voltage difference between Vds and Vin at the moment when this substage begins. However, as the switching losses given by (84) are noticeably smaller than in the normal switching transition, this case is of minor relevance. Eloss ≈ G. Example Waveforms Fig. 18 shows a set of example waveforms provided by the model, using typical MOSFET parameters. As the gate to source voltage provided by the model is again essentially equal to what can be found in a conventional MOSFET datasheet, it has not been included in this section. It can be seen in Fig. 18 that a noticeable power loss occurs during the turn-OFF transition, especially in comparison with the turn-ON. Thus, the model suggests that turn-OFF switching losses are much higher than turn-ON switching losses. This fact can be easily explained taking into consideration the effect of the parasitic inductances: these limit the current Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL Fig. 20. Fig. 19. Comparison between the losses provided by the proposed model and the classical piecewise–linear model [2]. change rate during turn-ON, thus inducing an almost zerocurrent-switching transition. Conversely, during the turn-OFF transition, the inductances lengthen the duration of the process, thereby causing an increase in the losses. 1637 LM3152 demo board. and its effect should be taken into account. Both conditions are stated in (86) and (87): Iout << tturn−on Vin ⇒ capacitance limited 2Ld (86) Iout >> tturn−on Vin ⇒ inductance limited. 2Ld (87) A comprehensive differentiation of these two cases can also be found in [12]. V. COMPARISON WITH THE CLASSICAL PIECEWISE-LINEAR MODEL VI. EXPERIMENTAL RESULTS Fig. 19 shows a comparison between the results provided by the classical model (extracted from [2]) and the proposed model. It is apparent that the classical model yields higher losses during turn-ON than the proposed model, whereas during turn-OFF the opposite happens and the classical model yields smaller losses than the proposed model. However, there is a “compensation effect” between these two errors that leads to the final losses not being very different from one model to another. This coincidence means that the classical model is still very useful, but only when the switching process is not inductance limited: in that case it yields inaccurate results, as is shown in Section VI. The proposed model clearly indicates that turn-OFF losses are much higher than turn-ON losses in the inductance-limited case. From a designer’s point of view, it is interesting to establish an approximate boundary between the region where the classical model can be reliably applied (capacitance-limited switching) and the region when the proposed model should be used because the effect of parasitic inductances cannot be neglected (inductance-limited switching). The classical model states that the turn-ON time is Qswitching Rg tturn−on = (85) Vth + (Iout /gm ) To experimentally test the proposed model, several laboratory measurements were conducted. First, the efficiency of a synchronous buck converter was measured and compared with the data provided by the proposed model. A National Semiconductor LM3152 demo board switching at 500 kHz (see Fig. 20) was used. As not enough reverse recovery data are given in the datasheet of the MOSFETs (RJK0305), a Schottky diode was connected in parallel with the low-side MOSFET. Thus, (49) can be used to estimate the losses during substage IV of the turn-ON transition. Conduction losses of both MOSFETs and the diode were fully taken into account and calculated using conventional equations (e.g., in the case of one of the MOSFETs, the expression i2rm s Rds,ON was used, irm s being the root mean square current through the MOSFET); power losses in input and output capacitances and in the control circuitry were also considered, as well as the increase of the MOSFETs on-resistance with operating temperature. The results are shown in Fig. 21(a) and (b). It can be seen that the model provides accurate results and that the trend followed by experimental data is clearly reproduced by the model. Switching losses account for approximately 25% of the total amount of losses in this experiment. There is a certain amount of uncertainty in the efficiency results provided by the model mainly caused by the uncertainty in the current ripple of the demo board output inductance and by the reverse recovery losses that may still be existing in the circuit. A second experiment was carried out to minimize these uncertainties. A synchronous buck converter switching at 1.3 MHz was built using RJK0305 MOSFETs and an LM2727 controller. Several changes were made with respect to the previously described experiment. First, the switching frequency was increased to give more weight to switching losses against other loss terms. Second, a very small inductor (≈ 300 nH) was used to obtain a with Qswitching being the total switching charge that has to be transferred into the gate-drain capacitance during the Miller effect period, the value of which is usually given in the datasheet. Thus, the current increase through Ld during the estimated turnON time can be compared with the output current Iout ; if the latter is much smaller than the former, Ld will not be able to limit the current rate of change and the switching will be capacitance limited. On the contrary, if Iout is much bigger than the current increase through Ld , then Ld will limit the current rate of change Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1638 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 22. Prototype with the small coreless inductance and different positions of decoupling capacitors in the layout used to achieve the extra drain inductance. Fig. 21. (a) Experimental and model results (V in = 6 V); (b) experimental and model results (V in = 12 V). very high current ripple. The effect of reverse recovery losses was thus diminished, because the inductor current at the turnON instant was much smaller than the current at the turn-OFF. Moreover, the high current ripple allowed us to have less average output current while maintaining a high turn-OFF current, thus achieving lower conduction losses and giving more weight to switching losses. As core losses were also another source of uncertainty, a coreless inductor was used. The output voltage ripple was kept small by incrementing the output capacitance (≈ 150 µF) and by using several low-equivalent series resistance capacitors. Third, the current through the inductor was measured using a current transformer built with a small toroid. Fig. 22 shows the prototype. Switching losses were more than 30% of total losses with this setup. Two different sets of measurements were made: first, the efficiency was measured and compared to the results provided by the classical model and the proposed model; second, a small drain inductance was added to the circuit and the efficiency was measured again. Fig. 22 shows how the inductance was achieved in practice: the decoupling capacitors were separated about 1 cm from their previous position. The current loop that causes the inductance was thus made longer and the inductance was increased. The layout was measured by a precision impedance analyzer before and after the change. The measurements yielded an extra inductance of approximately 10–15 nH. Fig. 23. (a) Comparison between the experimental data and the results provided by the models with decoupling capacitors in position 1 (see Fig. 22); (b) comparison between the experimental data and the results provided by the models with decoupling capacitors in position 2. Fig. 23 shows a comparison between the experimental results obtained and the results provided by the classical and the proposed model. Fig. 23(a) demonstrates that both the classical and the proposed model can approximately reproduce the measured efficiency when decoupling capacitances are in position 1; i.e., when the parasitic inductance is minimized. An error of nearly one point can be appreciated in the results: as the exact values of most of the parameters are not precisely known, it is very difficult to achieve more accuracy using datasheet values, regardless of the model being used. Fig. 23(b) shows the results when the decoupling capacitors are in position 2. It is apparent that, as the classical model does Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. RODRÍGUEZ et al.: INSIGHT INTO THE SWITCHING PROCESS OF POWER MOSFETS: AN IMPROVED ANALYTICAL LOSSES MODEL Fig. 24. Fig. 25. 1639 Breakdown of total losses provided by the model. Detailed breakdown of total losses (Io u t, average = 7 A). not take into account any inductance, its results were noticeably different from the measured data. In contrast, the proposed model was able to reproduce the experimental efficiency. Fig. 24 shows the breakdown of losses provided by the proposed and the classical model. These values were used to obtain the results, as shown in Fig. 23. The influence of each contribution can be clearly appreciated: as stated, the contribution of switching losses to the total losses was above 30%. Fig. 25 shows the detailed contribution of each loss term when the average output current was 7 A. Yet again, the contribution of switching losses to the total losses can be clearly noticed, along with the higher contribution of the turn-OFF term in all operating conditions. Furthermore, the extra drain inductance (the capacitance in position 2) only increased the turn-OFF losses, while the rest of the terms remained constant. VII. CONCLUSION This paper has presented a new detailed switching model for power MOSFETs, which allows switching losses to be calculated. It has been shown that although the classical model is very useful and provides relatively accurate results, it may not precise enough in actual synchronous buck converter designs if their switching process is inductance limited. The proposed model takes into account the major circuit parasitics, especially inductances, providing analytical solutions for the waveforms and enabling the designer to create a simple spreadsheet to estimate switching losses. All the equations required for loss calculations are summarized in Tables I and II. Furthermore, the model provides a clear physical overview of the switching process and shows the effect that the different parasitics of the transistor and the circuit have on this process. For instance, it shows that the turn-ON and the turn-OFF transitions are quite different in nature. This paper has shown, via carefully planned experimental measurements, that the model provides quite accurate results. It has also demonstrated that the classical model, though very useful and accurate, has certain application limits; the proposed model is intended to provide better results than the classical model in such situations. The conditions in which each model should be used have also been stated, clearly differentiating between capacitance-limited switching and inductance-limited switching. The experimental results have also shown that it is very difficult to accurately predict the efficiency, regardless of the model being used, mainly due to the uncertainty that exists when determining the value of most of the parameters. For instance, both the proposed and the classical model are very sensitive to the MOSFET threshold voltage and the transconductance. As the operating conditions in which these parameters are given in the datasheet may not match actual working conditions, and also given that each parameter has its own variation range within each MOSFET, a certain deviation in the model predictions is almost unavoidable. Furthermore, the values of the parasitic capacitances change with the voltage applied across them, while the parasitic inductances change with the frequency of operation. It is however worth pointing out that, even though the use of analytical models cannot provide results as accurate as, e.g., a physical simulation software, a relatively precise prediction can be made and tested by carefully planned setups, as this paper has shown. Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply. 1640 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 REFERENCES [1] T. Lopez and R. Elferich, “Quantification of power MOSFET losses in a synchronous buck converter,” in Proc. IEEE Appl. Power Electron. Conf., 2008, pp. 1594–1600. [2] J. Klein, “Synchronous buck MOSFET loss calculations with Excel model,” Appl. note AN–6005, Fairchild Semicond. version 1.0.1,, Apr. 2006. [3] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of power MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319, Mar. 2006. [4] S. Clemente, B. R. Pelly, and A. Isidorf, “Understanding HEXFET switching performance,” The HEXFET Designer´s Manual, Application note 947, pp. 85–98, published by International Rectifier, EL Segundo, CA, 1993. [5] W. Eberle, Z. Zhang, Y. Liu, and P. C. Sen, “A practical switching loss model for Buck voltage regulators,” IEEE Trans. Power Electron., vol. 24, no. 3, pp. 700–713, Mar. 2009. [6] Z. Zhang, W. Eberle, Z. Yang, Y. Liu, and P. C. Sen, “Optimal design of resonant gate driver for Buck converter based on a new analytical loss model,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 653–666, Mar. 2008. [7] Z. Yang, S. Yen, and Y. Liu, “A new dual-channel resonant gate drive circuit for low gate drive loss and low switching loss,” IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1574–1583, May 2008. [8] Z. Zhang, W. Eberle, P. Lin, Y. Liu, and P. C. Sen, “A 1-MHz highefficiency 12-V Buck voltage regulator with a new current-source Gate driver,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2817–2827, Nov. 2008. [9] M. Pavier, A. Sawle, A. Woodworth, R. Monteiro, J. Chiu, and C. Blake, “High frequency DC-DC power conversion: The influence of package parasitics,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2003, vol. 2, pp. 699–704. [10] B. Tien and C. Hu, “Determination of carrier lifetime from rectifier ramp recovery waveform,” IEEE Electron Device Lett., vol. 9, no. 10, pp. 553– 555, Oct. 1988. [11] Y. Xiong, S. Sun, H. Jia, P. Shea, and Z. J. Shen, “New physical insights on power MOSFET switching losses,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 525–531, Feb. 2009. [12] L. Gorgens, “Maximizing the effect of modern low voltage power MOSFETs,” in Proc. Appl. Power Electron. Conf., 2009, Professional Education Seminars, vol. II, Seminar 8, pp. 65–95. [13] M. Eaglin, “LM3152–3.3 demonstration board datasheet,” National Semiconductor, Sep. 2008. [14] R. Eriksson and D. Maksimovic, Fundamentals of Power Electronics. Boston, MA: Kluwer, 2001, ISBN 0–7923–7270–0. [15] N. Mohan, Power Electronics: Converters, Applications and Design. New York: Wiley, 2003, ISBN 0–4712–2693–9. Miguel Rodrı́guez (S’06) was born in Gijón, Spain, in 1982. He received the M.S. degree in telecommunication engineering from the Universidad de Oviedo, Spain in 2006, where he is currently working toward the Ph.D. degree in the Department of Electrical and Electronic Engineering (granted by the Spanish Ministry of Science and Education under the Formación de Profesorado Universitario Program). His research interests include dc/dc conversion, high-frequency power conversion, and power-supply systems for RF amplifiers. Alberto Rodrı́guez (S’07) was born in Oviedo, Spain, in 1981. He received the M.S. degree in telecommunication engineering in 2006 from the University of Oviedo, Gijón, Spain, where he is currently working toward the Ph.D. degree. In 2006, he was a Telecommunications Engineer with the Government of the Principality of Asturias and an Assistant Professor with the Department of Electrical Engineering, University of Oviedo. Since 2007, he has been working in University of Oviedo at full time. His current research interests include bidirectional dc–dc power converters. Pablo Fernández Miaja (S’07) was born in Oviedo, Spain, in 1984. He received the M.S. degree in telecommunication engineering in 2007 from the University of Oviedo, Gijón, Spain, where e is currently working toward the Ph.D. degree. His work is funded by the Spanish Ministry of Science and Technology to study dc–dc converters to feed RF power amplifiers. His current research interests include dc–dc converters, digital control of switching power supplies and techniques to increase the efficiency of RF power amplifiers like envelope tracking. Diego González Lamar (M’05) was born in Zaragoza, Spain, in 1974. He received the M.Sc. and Ph.D. degrees in electrical engineering from the Universidad de Oviedo, Gijón, Spain, in 2003 and 2008, respectively. In 2003, he was a Research Engineer at the University of Oviedo, where he has been an Assistant Professor since September 2005. His current research interests include switching-mode power supplies, converter modeling, and power-factor-correction converters. Javier Sebastián Zúniga (M’´87) was born in Madrid, Spain, in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, Spain, and the Ph.D. degree from the University of Oviedo, Gijón, Spain, in 1981 and 1985, respectively. He was an Assistant Professor and an Associate Professor at both the Polytechnic University of Madrid and at the University of Oviedo. Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests include switching-mode power supplies, modeling of dc-todc converters, low-output voltage dc-to-dc converters, and high-power-factor rectifiers. Authorized licensed use limited to: UNIVERSIDAD DE OVIEDO. Downloaded on June 17,2010 at 07:00:48 UTC from IEEE Xplore. Restrictions apply.