ECE 331 – Digital System Design
Constraints in Logic Circuit Design
(Lecture #14)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Logic Circuits
●
Thus far, we have focused on the design of logic
circuits in terms of their logical behavior only.
●
When designing a logic circuit, we must also
consider several real-world constraints, including:
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Noise
–
Fan-out
–
Fan-in
–
Power consumption
–
Time delay
–
Transient behavior
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Representing Logic Levels
●
A voltage range is specified for each logic level.
VDD
Logic 1
V1,MIN
Undefined
Threshold voltages
V0,MAX
Logic 0
GND
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Noise and Noise Margin
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Noise
●
External noise sources can cause the logic gate
output voltages to deviate from their expected values.
noise
●
VOH
VIH
VOL
VIL
As a result, the voltages may be misinterpretted.
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An output low voltage not interpreted as a logic 0
–
An output high voltage not interpreted as a logic 1
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Noise Margin
●
Must select logic gates to allow the logic circuit to
function properly even in the presence of noise.
●
The noise margin is the amount of noise that the logic
circuit can withstand while still functioning properly.
●
It is a measure of the noise immunity provided by the
logic circuit.
●
The noise margin is defined for both logic 1 and logic 0
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NMH = VOH – VIH
High noise margin
–
NML = VIL – VOL
Low noise margin
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Noise Margin
VDD
VDD
VDD
Logic 1
Logic 1
VOH
VOH
VIH
VIH
Undef
Undef
VIL
VIL
Logic 0
GND
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VOL
VOL
NML
Logic 0
GND
Input
NMH
GND
Output
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Noise Margin
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Noise Margin
●
●
The noise margin must be positive, for both logic 1
and logic 0, for the circuit to function properly.
–
VOH (driver) > VIH (load)
–
VOL (driver) < VIL (load)
A negative noise margin implies that the voltage
output by the driving gate will not be interpreted
properly by the load gate(s).
VOH
VOH + noise
VOL
VOL + noise
Driver
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Load
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Example: Noise Margin
Calculate NMH and NML
when a 74LS08 drives a 74LS32.
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Example: Noise Margin
VOH, VOL
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Example: Noise Margin
VIH, VIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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VOH
VOL
2.7V
0.4V
VIH
2.0V
VIL
NMH
NML
0.7V
0.4V
0.8V
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Example: Noise Margin
Calculate NMH and NML
when a 74HC32 drives a 74LS08.
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Example: Noise Margin
74HC32
VOH, VOL
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Example: Noise Margin
VIH, VIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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VOH
VOL
4.18V
0.26V
VIH
2.0V
VIL
NMH
NML
2.18V
0.54V
0.8V
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Example: Noise Margin
Calculate NMH and NML
when a 74LS08 drives a 74HC32.
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Example: Noise Margin
VOH, VOL
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Example: Noise Margin
74HC32
VIH, VIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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VOH
VOL
2.7V
0.4V
VIH
3.15V
VIL
NMH
NML
- 0.45V
0.95
1.35V
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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VOH
VOL
2.7V
0.4V
VIH
2.0V
2.7V
NML
0.7V
0.4V
- 0.45V
0.95
2.18V
0.54V
1.35V
0.26V
2.0V
NMH
0.8V
0.4V
3.15V
4.18V
VIL
0.8V
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Fan-out
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Fan-out
To the input of n logic gates
●
Fan-out is the number of logic gate inputs that can be
properly driven by a single logic gate output.
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Fan-out
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Logic gates can sink and source a limited amount of
current, both at the input and the output.
●
These currents are defined in terms of four
parameters
–
IOH = output high current
IIH = input high current
–
IOL = output low current
IIL = input low current
●
These are specified in the data sheet for the
corresponding logic gate.
●
They differ from one logic family to another.
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Fan-out
●
Fan-out is limited by the output current of the driving
gate and the input current of the load gates.
●
Fan-out is calculated, simply, as the ratio of the
output current (of the driving gate) to the total input
current (of the load gates).
●
It must be calculated for both the logic 1 output (highstate) and the logic 0 output (low-state).
●
Both must be considered when designing a logic
circuit.
–
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Select the worst-case as the limit.
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Fan-out
●
Low-state Fan-out =
Floor[ IOL_max (driver) / IIL_max (load) ]
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High-state Fan-out =
Floor[ IOH_max (driver) / IIH_max (load) ]
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Example: Fan-out
Calculate the fan-out
when a 74LS08 drives one or more 74LS32.
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Example: Fan-out
IOH, IOL
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Example: Fan-out
IIH, IIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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IOH
IOL
0.4 mA
8 mA
IIH
IIL
FOH
FOL
20
22.2
20 µA 0.36 mA
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Example: Fan-out
Calculate the fan-out
when a 74HC32 drives one or more 74LS08.
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Example: Fan-out
74HC32
IOH, IOL
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Example: Fan-out
IIH, IIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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IOH
IOL
IIH
IIL
4.0 mA 4.0 mA
FOH
FOL
200
11.1
20 µA 0.36 mA
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Example: Fan-out
Calculate the fan-out
when a 74LS08 drives one or more 74HC32.
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Example: Fan-out
IOH, IOL
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Example: Fan-out
74HC32
IIH, IIL
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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IOH
IOL
0.4 mA
8 mA
IIH
1 µA
IIL
FOH
FOL
400
8000
1 µA
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Example: Noise Margin
Gate
LS08
LS32
LS08
HC32
HC32
LS08
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IOH
IOL
0.4 mA
8 mA
IIH
IIL
FOH
FOL
20
22.2
400
8000
200
11.1
20 µA 0.36 mA
0.4 mA
8 mA
1 µA
1 µA
4.0 mA 4.0 mA
20 µA 0.36 mA
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Fan-out
●
Exceeding fan-out limit leads to
–
Increase in output-low voltage (VOL)
●
–
Decrease in output-high voltage (VOH)
●
–
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And possibly the wrong logic state
Increase in temperature
●
–
And possibly the wrong logic state
And possible destruction of the circuit / device
Increase in propagation delay
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Effect of Fan-out on Gate Delay
V f for n = 1
VDD
V f for n = 4
Gnd
0
Time
(c) Propagation times for different values of n
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Electrical Constraints
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Devices in the same logic family have the same
electrical characteristics.
●
Devices in different logic families often have different
electrical characteristics.
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In order to interconnect devices of different logic
families:
–
Must consider the noise margin
●
–
Must consider the fan-out
●
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voltage constraint
current constraint
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Fan-in
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Fan-in
●
Fan-in is the number of inputs to a logic gate.
●
It is limited by
●
–
Silicon area
–
Input capacitance
Thus, when designing a logic circuit, we must consider
the practical limit on the fan-in of the logic gates.
–
Cannot assume that an n-input logic gate is available
●
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where n is large.
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Fan-in
●
●
As we have already seen,
–
A SOP expression is most easily realized using a
two-level AND-OR circuit
–
A POS expression is most easily realized using a
two-level OR-AND circuit
However, if the logic circuit requires logic gates that
exceed the fan-in limit, an alternate design will be
necessary.
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Manipulate the Boolean expression
–
Realize using a multiple-level circuit
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Example: Fan-in
Design a combinational logic circuit using 3-input
NOR gates only, for the following logic function:
F(A,B,C,D) = Π M(1, 2, 6, 7, 11, 12, 13)
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Example: Fan-in
F = [b + d′ + (a + c)(a′ + c′)][a + c′ + b′d][a′ + b′ + c]
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Questions?
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