Programmable Picosecond Pulse Generator in CMOS
Xue Wu and Kaushik Sengupta
Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544, USA
Abstract—In this paper, a scalable and reconfigurable architecture is presented for digitally programmable sub-THz
waveform generation in CMOS. The architecture allows individual control of both amplitudes and phases of harmonic
frequencies beyond fmax to achieve waveform shaping. This is
enabled through controlled interference of multiple travelingwaves with rich harmonic components and delays. As an example,
inspired from mode-locked laser, picosecond pulse generation is
demonstrated in CMOS with a measured pulse-width of 2.6ps
and 0.46 mW output power for the pulse train. To the best of the
authors’ knowledge, this is the smallest pulse width demonstrated
in integrated circuit technology with additional capability of
dynamic reconfiguration. The chip is fabricated in 65nm LP
CMOS process.
Keywords—Picosecond pulse, harmonics, nonlinearity, waveform shaping, traveling-wave, terahertz, millimeter-wave, CMOS.
I.
I NTRODUCTION
Time-signatures generating pico-second pulses has rich
application possibilities ranging from high-resolution radar and
imaging to spectroscopic sensing in chemical and biomedical
sciences. Classical methods of generation and detection of such
wideband THz signals rely on femtosecond lasers exciting
photoconductive substrates [1]. In recent years, silicon-based
integrated technology has been shown to generate and radiate
power at THz frequencies, above fmax of the technology [2].
However, most of these architectures are inherently narrowband. Broadband pulse generation techniques have been experimented with nonlinear lattice and digital delay methods
which are limited by the gate delay and the cut-off frequency of
the technology [3]-[6]. As the increase fmax of IC technology
slows with scaling, new architectures have to be innovated that
can allow pulse generation with THz bandwidth for enabling
the unique range of applications.
This paper proposes a scalable architecture that allows
programmable periodic waveform generation by controlling
the amplitudes and phases of multiple harmonic frequencies
beyond fmax . A train of picosecond pulses of width (δT ) at a
pulse repetition frequency of frep imply that the output signal
contains harmonics of frep with constant amplitude and linear
phase progression (constant delay) extending upto THz frequencies (f ∼ δ1T ). An optical analogue is a mode-locked laser
where the multiple harmonics align up in phase resulting in fspulses emanating from the output. Therefore, the key towards
generation of ps-pulses is to harness multiple harmonics above
fmax simultaneously with amplitude and phase control, such
that all of them have equal amplitudes and proportional phases.
When all the harmonics align up in this fashion, sharp pulses
are generated with time-widths (δT ) comparable to half the
1
time period of the highest harmonic frequency i.e. δτ ∼ 2nf
,
0
where nf0 is the highest harmonic frequency beyond fmax .
In fact, by controlling the amplitudes and phases of all the
harmonic components, it is possible to achieve generation of
digitally programmable arbitrary periodic THz waveforms.
II.
A RCHITECTURE AND C IRCUITS
In order to program the amplitudes and phases of the
fundamental and the harmonic frequencies independently, the
architecture needs to generate these frequencies, filter and
isolate them, and thereafter control their amplitudes and
phases. Since amplifiers cannot provide gain beyond fmax ,
this will be an inefficient method. Fig. 1 shows the proposed
architecture which exploits device nonlinearities to produce
a series of harmonic frequencies and employs controllable
interference of traveling-waves to generate arbitrary amplitudes
and phases of the spectral components. This eliminates the
necessity of harmonic filtering and separations with lossy
passives, and individual gain control of frequencies above
fmax . A multi-port controllable interference medium with a
low-loss, low-dispersion transmission line allows a scalable
method to control amplitudes and phases of multiple harmonics
simultaneously.
Fig. 1. Architecture of a programmable THz periodic waveform generator
on-chip.
A central frequency synthesizer operating at f0 below fmax
distributes the fundamental signal to multiple channels. A
narrow-band phase rotator in each channel operating at f0 controls the phase of the fundamental signal driving a nonlinear
generator which launches a traveling wave rich in harmonic
frequencies, as shown in Fig. 1. A rotation of ∆θ at f0 creates
proportional phase changes for the higher harmonics in each
channel. It can be shown that by allowing interference of these
separate paths in a combining network (transmission-line),
978-1-4799-8275-2/15/$31.00 ©2015 IEEE
Fig. 2.
Programmable pico-second pulse generator in 65 nm CMOS.
individual control of amplitudes and phases of all the harmonic
components is possible by just controlling the narrow-band
phase rotator settings (∆θi ) at f0 . If (Ai , θi ) represent the
amplitude and phase components of the fundamental and the
harmonic frequencies for the desirable waveform, and if the
harmonic components of the nonlinear harmonic generator
output are represented by i = (α1 ejφ1 , α2 ejφ2 , ...αn ejφn ),
then the harmonic components of the combined output of ‘m’
channels can be represented as
A1 ejθ1 = α1 ejφ1 (ej∆θ1 +ψ1 + ...ej∆θm +mψ1 )
A2 ejθ2 = α2 ejφ2 (ej2∆θ1 +ψ2 + ...ej2∆θm +mψ2 )
...
jθn
An e
= αn ejφn (ejn∆θ1 +ψn + ...ejn∆θm +mψn ) (1)
th
where ψk represents the phase shift suffered by the k
harmonic as it passes through the transmission line and combines at the output. For a dispersion-less transmission line,
ψk = kψ1 . However, as it can be seen from (1), even for a
transmission line with dispersion αi , ψi are constants, and it
is possible to arrive at a solution for (∆θi ) for any desirable
(Ai , θi ) if m = 2n. In summary, dynamic reconfiguration
of the output periodic THz waveform can be achieved by
simply controlling the phase rotator settings of the fundamental
frequency f0 .
The architecture gives us the flexibility to choose how
we incorporate phase rotations through ∆θi and the delay
line ψi . An example of this architecture optimized for picosecond pulse generation and exploiting two harmonics and
implemented in this paper is shown in Fig. 2. A voltage
controlled oscillator (VCO), which is locked to a reference
signal, provides a differential fundamental signal at 108 GHz.
The fundamental signal is buffered and amplified using two
cascaded amplifiers with transmission line based matching
networks to produce an output power of 4.5 dBm at 108
GHz. This differential signal passes through variable delay
lines and drives two pseudo-differential harmonic generators
whose outputs are combined in a transmission line for pulse
generation, as shown in Fig. 2. The transmission line based
varactor loaded delay line can provide an overall phase shift of
around 27◦ as shown in Fig. 2. The variable delay lines allow
us to overcome process variations and dynamically reconfigure
the time-domain waveform, as will be shown later. The 108
GHz VCO and, therefore the pulse train, is locked to an
external reference signal through an on-chip divider chain with
injection-locking and digital dividers. The phase frequency
detector and the charge pump are implemented off-chip. For
the VCO frequency of 108 GHz, the divider chain output is
at 1.6875 GHz which is locked to an external reference at the
same frequency. The constituent circuit blocks are also shown
in Fig. 2.
In order to align the harmonics for pulse generation, the
phases of the fundamental frequency at 108 GHz and the
second harmonic signal at 216 GHz (θ1 , θ2 in (1)) should
satisfy 2θ1 = θ2 or 2θ1 = θ2 + π. As shown in Fig. 2, the
second condition can be satisfied if interference is allowed on
a suitable transmission line of length (ψ1 ∼ 26◦ ≤ 90◦ for
f0 ), such that the harmonic current vectors rotate and align in
the required phase relation and equal in magnitude. It can be
shown that if if 0 and i2f 0 are the amplitudes of the harmonic
currents, then the required length of the transmission line is
given by the following relation if 0 sin ψ21 = i2f 0 cos(ψ1 ).
The impedances seen by the harmonic generators at the two
harmonic frequencies adjust themselves to provide the required
vector rotation for pulse generation. Since ψ1 ≤ 90◦ for f0 ,
the impedances seen by the harmonic generators are inductive
and capacitive for the fundamental frequency and the second
harmonic signal, respectively. A matching network is added
to optimize power delivery to the load at the two harmonic
frequencies. The simulated pulse-width is approximately 2.6
ps, as shown in Fig. 2.
III.
M EASUREMENT R ESULTS
The chip is implemented in a 65 nm LP-CMOS process
with fmax ∼ 190 GHz. The die micrograph is shown in
978-1-4799-8275-2/15/$31.00 ©2015 IEEE
Fig. 2. The area of the chip is 1.1 mm × 2.3 mm. The
chip consumes 108 mW of DC power in the main signal
generation path (which has a VCO, two power amplifiers, two
controllable delay lines and a pulse generator) and 327 mW
in the divider chain (which includes three injection locking
dividers and three digital dividers). The output pulse train is
locked to an external reference signal, but in the absence of a
sampling scope with more than 220 GHz bandwidth, a reliable
method to measure the time-domain waveform is to perform
frequency-domain measurements of the magnitudes and phases
of the fundamental and the harmonic signals simultaneously,
as shown in Fig. 3.
Fig. 4. Measured and calibrated power spectra of the fundamental frequency
at 107 GHz and second harmonic at 214 GHz showing almost equal power of
-6.4 dBm each, resulting in a pulse train with an output power of -3.4 dBm.
harmonic at 214 GHz are -6.4 dBm with the desired phase
relation 2θ1 − θ2 = π, resulting in a pulse train with -3.4 dBm
of output power with 2.6 ps pulse-width.
Fig. 3. Measurement set-up to capture time-domain waveforms at f0 =107
GHz and f0 =214 GHz by measuring the amplitudes and phases of the
fundamental and the second harmonic signals simultaneously. The frequency
domain measurement is necessary since no commercial sampling scope exists
with bandwidth greater than 220 GHz.
The receiver path consists of a 110-170 GHz probe, a Dband harmonic mixer, a diplexer, a splitter, an amplifier and
coaxial cables. The frequency components of the output signal
and their power is measured with an Agilent N9030A PXA
signal analyzer, connected to an output splitter. The relative
phases of the two harmonics are measured from the timedomain waveform on an Agilent DSO90604 oscilloscope at the
IF frequency. The PM4 power meter with WR6-WR10 taper
measures the total absolute power delivered from the other
output pad located symmetrically on the chip (Fig. 2, Fig. 3).
The entire receiver path is calibrated extensively for both
amplitude and phase between the measurement frequencies
from 107-214 GHz. In the absence of a probe that operates
in single-mode for both the harmonics, over-moded operation
is unavoidable. But the effect is taken into account during the
calibration process. The phase shifts through the mixer at both
107 GHz and 214 GHz is calibrated by exploiting the mixer
itself to generate the second harmonic signal, when driven by a
107 GHz source. Since the harmonic mixer itself is nonlinear,
the second harmonic generation (214 GHz) from the chip is
verified by driving the mixer with a signal source at 107 GHz
and observing the second harmonic signal at 214 GHz which is
found to be negligible. Repeated measurements are performed
to show the robustness of the reconstructed waveform.
Fig. 4 shows the measured and calibrated spectra of the
fundamental frequency at 107 GHz and the second harmonic
at 214 GHz, showing equal output power of -6.4 dBm.
Measurements of both the magnitudes and the phases of the
harmonic components are necessary for retrieving the timedomain waveform. Fig. 5 shows the measured time-domain
outputs for multiple settings of the on-chip variable delay lines.
The optimized pulse setting shows that the output power of
both the fundamental frequency at 107 GHz and the second
Fig. 5. Measured time-domain waveforms for five different settings of the
controllable delay lines. The optimized pulse train shows a record 2.6 ps
pulse-width.
Fig. 6. Measured and simulated variations of phase relationship and amplitudes of the fundamental frequency f0 =107 GHz and the second harmonic
2f0 =214 GHz with the changing of the varactor loaded variable delay line
settings. Phase offset between f0 and 2f0 is defined as 2θ1 − θ2 .
As noted before, the controllable delay lines allow us to
reconfigure the phases and amplitudes of the spectral components. While independent control for all the harmonics will
require four harmonic paths, the optimized pulse generator
architecture in Fig. 2 enables partial control of both the
harmonics. The measured and simulated variations of the
output power and phase relationship of both the harmonics
are shown in Fig. 6. It shows that the phase offset (2θ1 − θ2 )
can be approximately varied from 175◦ to 230◦ . The variation
of the signal strength at the two harmonic frequencies are also
shown in Fig. 6. These variations in the frequency domain
enable us to dynamically reconfigure the time-domain output
waveforms. Fig. 5 shows four time-domain waveforms for
different differential delay line settings (Vctrl = −1 V, −0.5
V, 0 V, 0.5 V and 1 V).
Fig. 7 shows that the VCO can be tuned from 106.5 GHz
978-1-4799-8275-2/15/$31.00 ©2015 IEEE
TABLE I.
Pulse width (ps)
Reconfigurability
RF power (dBm)
Measurement domain
Pulse generation method
Technology
PERFORMANCE SUMMARY OF SILICON - BASED SOURCES
This work
2.6
Yes
-3.4 (on-chip)
Frequency (mag.+phase)
Interfering traveling waves
65nm-LP CMOS
[3]
8
No
13 (EIRP)
Time and Frequency (mag.)
Digital pulse
0.13µm SiGe
[4]
26
No
13 (EIRP)
Time and Frequency (mag.)
Oscillator-based
0.13µm SiGe
[5]
45
No
15.7 (EIRP)
Frequency (mag.)
Oscillator-based
65nm CMOS
[6]
21.5†
No
N/A
Time
Nonlinear t-line
0.18µm SiGe
†limited by measurement set-up
waveform shaping is achieved through controlled interference
of multiple traveling-waves with rich harmonic components
and delays. Picosecond pulse generation is demonstrated with
a record 2.6 ps pulse-width, and an output power of 0.46mW
for the pulse train. To the best of the authors’ knowledge, this
is the smallest pulse width demonstrated in integrated circuit
technology with additional capability of dynamic reconfiguration.
Fig. 7.
Measured frequency tuning and phase noise of the harmonic
components of the pulse train with free-running VCO. The phase noise of
the fundamental frequency component is approximately 6 dB lower than that
of the second harmonic component.
R EFERENCES
[1]
[2]
to 108.3 GHz. The phase noise of the fundamental frequency
and the second harmonic of the pulse train generated from the
free-running VCO is also shown in Fig. 7. The phase noise of
the fundamental frequency component of the pulse train shows
-70 dBc/Hz at 1 MHz offset, expectedly 6 dB lower than the
second harmonic component as shown in Fig. 7.
[3]
[4]
[5]
[6]
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Fig. 8. Measured harmonic powers and phase offsets for four different chips.
It demonstrates the robustness of the architecture against process variations.
Fig. 8 shows the measured power and phase offset of the
harmonic frequencies for four different dies. The measured
results are for nominal settings of the delay lines. The variation
in the amplitudes and phases can be partially compensated
through the delay line settings. This demonstrates the robustness of the architecture against process variations. Table I
compares the chip performance with prior art. To the best
of the authors’ knowledge, this work generates the smallest
pulse width demonstrated in integrated circuit technology with
additional capability of dynamic reconfiguration.
IV.
C ONCLUSION
This paper presents a scalable and reconfigurable architecture for programmable sub-THz periodic waveform generation
in CMOS. In the architecture, individual control of both amplitudes and phases of harmonic frequencies beyond fmax for
978-1-4799-8275-2/15/$31.00 ©2015 IEEE