Chapter 2. – Introduction (12/12/06)
Page 2.0-1
CHAPTER 2 – CMOS TECHNOLOGY
INTRODUCTION
What is Integrated Circuit Technology?
Webster:
Integrated circuit a combination of interconnected circuit elements inseparably
associated on or within a continuous substrate.
Technology application of science or a body of knowledge to achieve an objective.
Integrated circuit technology is the application of scientific knowledge to build a
combination of interconnected circuit elements inseparably associated on or with a
continuous substrate.
Packaging and
Assembly
Semiconductor
Processes
Integrated
Circuit
Lithography
Materials
040903-01
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Introduction (12/12/06)
Page 2.0-2
How Does IC Technology Influence Analog IC Design?
Characteristics of analog IC design:
• Continuous in signal amplitude
• Discrete or continuous in time
• Signal processing primarily depends on ratios of values and time constants
- Ratios are generally resistance, conductance, or capacitance
- Time constants are generally products of resistance and capacitance
• Dynamic range is determined by the largest and smallest signals
Influence of IC Technology:
• Accuracy of signal processing depends on the accuracy of the ratios of values
• The dynamic range depends upon the linearity of the circuit elements and the noise
• The value of components is limited by area considerations
• IC technology introduces resistive, capacitive and inductive parasitics that cause
deviation from desired behavior
• An analog circuit is subject to the influence of other circuits fabricated in the same
substrate
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Introduction (12/12/06)
Page 2.0-3
Classification of Silicon Technology
Silicon IC Technologies
Bipolar
Junction
Isolated
060112-02
Dielectric
Isolated
SiliconGermanium
Bipolar/CMOS
Oxide
isolated
Silicon
CMOS
Aluminum
gate
MOS
PMOS
(Aluminum
Gate)
Silicon
gate
NMOS
Aluminum
gate
CMOS Analog Circuit Design
Silicon
gate
© P.E. Allen - 2006
Chapter 2. – Introduction (12/12/06)
Page 2.0-4
Why CMOS Technology?
Comparison of BJT and MOSFET technology from an analog viewpoint:
Comparison Feature
Cutoff Frequency(fT)
Noise (thermal about the same)
DC Range of Operation
BJT
100 GHz
MOSFET
50 GHz (0.25μm)
Less 1/f
More 1/f
9 decades of exponential 2-3 decades of square law
behavior
current versus vBE
Transconductance
Larger by 10X
Smaller by 10X
Small Signal Output Resistance Slightly larger
Smaller for short channel
Switch Implementation
Poor
Good
Capacitor
Voltage dependent
More options
Technology Improvement
Slower
Faster
Therefore,
• Almost every comparison favors the BJT, however a similar comparison made from a
digital viewpoint would come up on the side of CMOS.
• Therefore, since large-volume mixed-mode technology will be driven by digital
demands, CMOS is an obvious result as the technology of availability.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Introduction (12/12/06)
Page 2.0-5
Components of a Modern CMOS Technology
Illustration of a modern CMOS process:
Metal Layers
0.8μm
M8
NMOS
PMOS
M7
Transistor
Transistor
M6
M5 7μm
Polycide 0.3μm
Polycide
Sidewall Spacers
M4
Salicide
Salicide
M3
Salicide
M2
M1
;
n+
n+
Source/drain
extensions
STI
STI
;
p+
p+
Source/drain
STI
extensions
Deep n-well
Deep p-well
p-substrate
031211-02
In addition to NMOS and PMOS transistors, the technology provides:
1.) A deep n-well that can be utilized to reduce substrate noise coupling.
2.) A MOS varactor that can serve in VCOs
3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Introduction (12/12/06)
Page 2.0-6
CMOS Components – Transistors
fT as a function of gate-source overdrive, VGS-VT (0.13μm):
Typical, 25°C
70
60
NMOS
Slow, 70°C
fT (GHz)
50
Typical, 25°C
40
30
Slow, 70°C
PMOS
20
10
0
0
100
200
300
|VGS-VT| (mV)
400
500
030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in the
vicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-1
SECTION 2.1 – BASIC IC PROCESS TECHNOLOGY
FUNDAMENTAL IC PROCESSING STEPS
Basic Steps
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
• Shallow trench isolation
• Epitaxy
Photolithography
Photolithography is the means by which the above steps are applied to selected areas of
the silicon wafer.
Silicon Wafer
125-200 mm
(5"-8")
0.5-0.8mm
n-type: 3-5 Ω-cm
p-type: 14-16 Ω-cm
Fig. 2.1-1r
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
Page 2.1-2
Oxidation
Description:
Oxidation is the process by which a layer of silicon dioxide is grown on the surface of a
silicon wafer.
Original silicon surface
tox
Silicon dioxide
0.44 tox
Silicon substrate
Fig. 2.1-2
Uses:
• Protect the underlying material from contamination
• Provide isolation between two layers.
Very thin oxides (100Å to 1000Å) are grown using dry oxidation techniques. Thicker
oxides (>1000Å) are grown using wet oxidation techniques.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-3
Diffusion
Diffusion is the movement of impurity atoms at the surface of the silicon into the bulk of
the silicon.
Always in the direction from higher concentration to lower concentration.
Low
Concentration
High
Concentration
Fig. 150-04
Diffusion is typically done at high temperatures: 800 to 1400°C
N0
Gaussian
ERFC
N(x)
N0
t1 < t2 < t3
N(x)
t1 < t2 < t3
NB
NB
t1
t2
t3
Depth (x)
Infinite source of impurities at the surface.
t1
t3
t2
Depth (x)
Finite source of impurities at the surface.
Fig. 150-05
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
Page 2.1-4
Ion Implantation
Ion implantation is the process by which
impurity ions are accelerated to a high
velocity and physically lodged into the
target material.
Path of
impurity
atom
Fixed Atom
Fixed Atom
• Annealing is required to activate the
Impurity Atom
impurity atoms and repair the physical
final resting place
damage to the crystal lattice. This step
is done at 500 to 800°C.
• Ion implantation is a lower temperature
N(x)
process compared to diffusion.
• Can implant through surface layers, thus it is
useful for field-threshold adjustment.
• Can achieve unique doping profile such as
NB
buried concentration peak.
0
CMOS Analog Circuit Design
Fixed Atom
Fig. 150-06
Concentration peak
Depth (x)
Fig. 150-07
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-5
Deposition
Deposition is the means by which various materials are deposited on the silicon wafer.
Examples:
• Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum
• Polysilicon
There are various ways to deposit a material on a substrate:
• Chemical-vapor deposition (CVD)
• Low-pressure chemical-vapor deposition (LPCVD)
• Plasma-assisted chemical-vapor deposition (PECVD)
• Sputter deposition
Material that is being deposited using these techniques covers the entire wafer and
requires no mask.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Etching
Page 2.1-6
Mask
Film
Etching is the process of selectively
removing a layer of material.
Underlying layer
When etching is performed, the
(a) Portion of the top layer ready for etching.
etchant may remove portions or all of:
a Selectivity
• The desired material
Mask
c
Film
• The underlying layer
Anisotropy
b
• The masking layer
Selectivity
Underlying layer
Important considerations:
(b) Horizontal etching and etching of underlying layer.
Fig. 150-08
• Anisotropy of the etch is defined as,
A = 1-(lateral etch rate/vertical etch rate)
• Selectivity of the etch (film to mask and film to substrate) is defined as,
film etch rate
Sfilm-mask = mask etch rate
A = 1 and Sfilm-mask = are desired.
There are basically two types of etches:
• Wet etch which uses chemicals
• Dry etch which uses chemically active ionized gases.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-7
Shallow Trench Isolation
Nitride
1.) Cover the wafer with pad oxide and silicon nitride.
(1)
2.) First etch nitride and pad oxide. Next, an anisotropic
etch is made in the silicon to a depth of 0.4 to 0.5 microns.
Silicon
(2)
3.) Grow a thin thermal oxide layer on the trench walls.
(3)
4.) A CVD dielectric film is used to fill the trench.
(4)
5.) A chemical mechanical polishing (CMP) step is used to
polish back the dielectric layer until the nitride is reached.
The nitride acts like a CMP stop layer.
(5)
6.) Densify the dielectric material at 900°C and strip the
nitride and pad oxide.
(6)
060203-01
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-8
Epitaxy
Epitaxial growth consists of the formation of a layer of single-crystal silicon on the
surface of the silicon material so that the crystal structure of the silicon is continuous
across the interfaces.
• It is done externally to the material as opposed to diffusion which is internal
• The epitaxial layer (epi) can be doped differently, even oppositely, of the material on
which it grown
• It accomplished at high temperatures using a chemical reaction at the surface
• The epi layer can be any thickness, typically 1-20 microns
Gaseous cloud containing SiCL4 or SiH4
Si +
Si
+
Si
Si
Si
Si
Si
Si
Si
CMOS Analog Circuit Design
Si
Si
Si
- Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
-
Si
Si
Si
Si
Si
Si
Si
Si
+
Si
Si
Si
-
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
+
Si
Si
Si
Si
Si
+
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
-
Si
Si
Si
Si
Si
Si
Si
-
Si
Si
-
Si
Si
Si
Si
Si
Si
Si
Fig. 150-09
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-9
Photolithography
Components
• Photoresist material
• Mask
• Material to be patterned (e.g., oxide)
Positive photoresist
Areas exposed to UV light are soluble in the developer
Negative photoresist
Areas not exposed to UV light are soluble in the developer
Steps
1. Apply photoresist
2. Soft bake (drives off solvents in the photoresist)
3. Expose the photoresist to UV light through a mask
4. Develop (remove unwanted photoresist using solvents)
5. Hard bake ( 100°C)
6.
Remove photoresist (solvents)
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-10
Illustration of Photolithography - Exposure
The process of exposing
Photomask
selective areas to light
through a photo-mask is
called printing.
Types of printing include:
• Contact printing
• Proximity printing
UV Light
• Projection printing
Photomask
Photoresist
Polysilicon
Fig. 150-10
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-11
Illustration of Photolithography - Positive Photoresist
Develop
Polysilicon
Photoresist
Etch
Photoresist
Polysilicon
Remove
photoresist
Polysilicon
Fig. 150-11
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
© P.E. Allen - 2006
Page 2.1-12
TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS
Major Fabrication Steps for a DSM CMOS Process
1.) p and n wells
2.) Shallow trench isolation
3.) Threshold shift
4.) Thin oxide and gate polysilicon
5.) Lightly doped drains and sources
6.) Sidewall spacer
7.) Heavily doped drains and sources
8.) Siliciding (Salicide and Polycide)
9.) Bottom metal, tungsten plugs, and oxide
10.) Higher level metals, tungsten plugs/vias, and oxide
11.) Top level metal, vias and protective oxide
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-13
Step 1 – Starting Material
The substrate should be highly doped to act like a good conductor.
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-02
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-14
Step 2 - n and p wells
These are the areas where the transistors will be fabricated - NMOS in the p-well and
PMOS in the n-well.
Done by implantation followed by a deep diffusion.
n well implant and diffusion
p well implant and diffusion
p+
n+
n-well
p-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-03
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-15
Step 3 – Shallow Trench Isolation
The shallow trench isolation (STI) electrically isolates one region/transistor from another.
p+
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
n-well
p-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n+
n
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-04
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-16
Step 4 – Threshold Shift and Anti-Punch Through Implants
The natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An pimplant is used to make the NMOS harder to invert and the PMOS easier resulting in
threshold voltages balanced around zero volts.
Also an implant can be applied to create a higher-doped region beneath the channels to
prevent punch-through from the drain depletion region extending to source depletion
region.
n+ anti-punch through implant
p+ anti-punch through implant
p threshold implant
p threshold implant
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-05
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-17
Step 5 – Thin Oxide and Polysilicon Gates
A thin oxide is deposited followed by polysilicon. These layers are removed where they
are not wanted.
p+
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-06
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-18
Step 6 – Lightly Doped Drains and Sources
A lightly-doped implant is used to create a lightly-doped source and drain next to the
channel of the MOSFETs.
Shallow pImplant
Shallow pImplant
Shallow nImplant
p+
Shallow nImplant
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-07
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-19
Step 7 – Sidewall Spacers
A layer of dielectric is deposited on the surface and removed in such a way as to leave
“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. These sidewall
spacers will prevent the part of the source and drain next to the channel from becoming
heavily doped.
Sidewall
Spacers
Sidewall
Spacers
p+
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
CMOS Analog Circuit Design
060118-08
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-20
Step 8 – Implantation of the Heavily Doped Sources and Drains
Note that not only does this step provide the completed sources and drains but allows for
ohmic contact into the wells and substrate.
n+
implant
p+
implant
p+
implant
n+
implant
n+
implant
p+
implant
n+
p+
p+
n+
nn++
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-09
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-21
Step 9 – Siliciding
Siliciding and polyciding is used to reduce interconnect resistivity by placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions.
Polycide
Polycide
pp++
p+
n+
Salicide
Salicide
Salicide
Salicide
n+
Shallow
Trench
Isolation
nn++
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-10
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-22
Step 10 – Intermediate Oxide Layer
An oxide layer is used to cover the transistors and to planarize the surface.
Lower
level
Oxide
Layer
pp++
p+
n+
nn++
n+
Shallow
Trench
Isolation
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-11
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-23
Step 11- First-Level Metal
Tungsten plugs are built through the lower intermediate oxide layer to provide contact
between the devices, wells and substrate to the first-level metal.
Intermediate
Oxide
Layers
Tungsten
Plugs
Salicide
Tungsten
Plug
Salicide
pp++
p+
n+
nn++
n+
Shallow
Trench
Isolation
First
Level
Metal
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-12
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-24
Step 12 – Second-Level Metal
The previous step is repeated to from the second-level metal.
Intermediate
Oxide
Layers
Tungsten Plugs
Tungsten
Plugs
Tungsten
Plugs
Salicide
Salicide
Salicide
pp++
p+
n+
nn++
n+
Shallow
Trench
Isolation
Tungsten
Plug
Salicide
Second
Level
Metal
First
Level
Metal
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
CMOS Analog Circuit Design
p
p-
n-
n
n+
Poly
Salicide Polycide
Metal
060118-01
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-25
Completed Fabrication
After multiple levels of metal are applied, the fabrication is completed with a thicker
top-level metal and a protective layer to hermetically seal the circuit from the
environment. Note that metal is used for the upper level metal vias. The chip is
electrically connected by removing the protective layer over large bonding pads.
Protective Insulator Layer
Top
Metal
Metal Vias
Intermediate
Oxide
Layers
Tungsten
Plugs
Tungsten Plugs
Polycide
Sidewall
Spacers
Tungsten
Plugs
Salicide
Metal Via
Salicide
Salicide
pp++
p+
n+
nn++
n+
Shallow
Trench
Isolation
Tungsten
Plug
Salicide
Second
Level
Metal
First
Level
Metal
p+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
CMOS Analog Circuit Design
Metal
060118-01
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-26
Scanning Electron Microscope of a MOSFET Cross-section
Tungsten Plug
TEOS
SOG
Polycide
Sidewall
Spacer
TEOS/BPSG
Poly
Gate
Fig. 2.8-20
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-27
Scanning Electron Microscope Showing Metal Levels and Interconnect
Metal 3
Aluminum
Vias
Metal 2
Tungsten
Plugs
Metal 1
Transistors
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
Fig.180-11
© P.E. Allen - 2006
Page 2.1-28
DSM CMOS Technology Summary
• Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.
• Basic process steps include:
1.) Oxide growth
4.) Deposition
7.) Epitaxy
2.) Thermal diffusion
5.) Etching
3.) Ion implantation
6.) Shallow Trench Isolation
• The complexity of a process can be measured in the terms of the number of masking
steps or masks required to implement the process.
• Major CMOS Processing Steps:
1.) p and n wells
7.) Heavily doped drains and sources
2.) Shallow trench isolation
8.) Siliciding (Salicide and Polycide)
3.) Threshold shift
9.) Bottom metal, tungsten plugs, and oxide
4.) Thin oxide and gate polysilicon 10.) Higher level metals, tungsten plugs/vias,
and oxide
5.) Lightly doped drains and sources
11.) Top level metal, vias and protective oxide
6.) Sidewall spacer
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-29
Minimum Feature Size (μm)
ULTRA DEEP SUBMICRON (UDSM) CMOS FABRICATION PROCESS
What is UDSM CMOS Technology?
1
• Vindication of Moore’s Law
“The minimum feature
size decreases by
Deep Submicron Technology
approximately 0.7 every
0.1
two years.”
Ultra Deep Submicron Technology
0.01
1985
1990
1995
Year
2000
2005
2010
060112-03
• Minimum feature size less than 100 nanometers
• Today’s state of the art:
- 65 nm drawn length
- 35 nm transistor gate length
- 1.2 nm transistor gate oxide
- 8 layers of copper interconnect
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
© P.E. Allen - 2006
Page 2.1-30
65 Nanometer CMOS Technology
TEM cross-section of a 35 nm NMOS and PMOS transistors.†
NMOS:
PMOS:
220 nm pitch
NMOS
These transistors utilize enhanced channel strains to increase drive capability and to
reduce off currents.
†
P. Bai, et. Al., “A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and
0.57 μm2 SRAM Cell, IEEE Inter. Electron Device Meeting, Dec. 12-15, 2005.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-31
UDSM Metal and Interconnects
Physical aspects:
Layer
Isolation
Polysilicon
Contacted Gate Pitch
Metal 1
Metal 2
Metal 3
Metal 4
Metal 5
Metal 6
Metal 7
Metal 8
Pitch
(nm)
220
220
220
210
210
220
280
330
480
720
1080
Thickness Aspect
(nm)
Ratio
230
90
170
1.6
190
1.8
200
1.8
250
1.8
300
1.8
430
1.8
650
1.8
975
1.8
CMOS Analog Circuit Design
Chapter 2. – Section 1 (12/12/06)
© P.E. Allen - 2006
Page 2.1-32
What are the Advantages of UDSM CMOS Technology?
Digital Viewpoint:
• Improved Ion/Ioff
70 Mbit SRAM chip:
• Reduced gate capacitance
• Higher drive current capability
• Reduced interconnect density
• Reduction of active power
Analog Viewpoint:
• More levels of metal
• Higher fT
• Higher capacitance density
• Reduced junction capacitance per gm
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-33
What are the Disadvantages of UDSM CMOS Technology (for Analog)?
• Reduction in power supply resulting in reduced headroom
• Gate leakage currents
• Reduced small-signal intrinsic gains
• Increased nonlinearity (IIP3)
• Noise and matching??
Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:†
†
Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp.
132-143.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-34
What is the Gate Leakage Problem?
Gate current occurs in thin oxide devices due to direct tunneling through the thin oxide.
Gate current depends on:
1.) The gate-source voltage (and the drain-gate voltage)
iGS = K1vGS exp(K2vGS) and
iGD = K3vGD exp(K4vGD)
2.) Gate area – NMOS leakage 6nA/μm2 and PMOS leakage 3nA/μm2
Unfortunately, the gate leakage current is nonlinear with respect to the gate-source and
gate-drain voltages. A possible model is:
f(vGD)
f(vGS)
−
vGD
+
+
vGS
−
+
f(vSG)
f(vDG)
vSG
−
−
vDG
+
PMOS
NMOS
Large Signal Models
051205-03
ggd
gsg
ggs
gdg
NMOS
PMOS
Small Signal Models
Base current cancellation schemes used for BJTs are difficult to apply to the MOSFET.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-35
Gate Leakage and fgate
The gate leakage can be represented by a conductance, ggate, in parallel with the gate
capacitance, Cgate. Since these two elements have identical area dependence, they result
in a frequency, fgate, that is are independent and fairly independent of the drain-source
voltage, vds.
1.5·1016 v 2etox(vGS-13.6) (NMOS)
ggate
GS
fgate = 2 Cgate 0.5·1016 v 2etox(vGS-13.6) (PMOS)
GS
where tox is in nm and vGS is in V.
For frequencies above fgate the
MOSFET looks capacitive and below
fgate, the MOSFET looks resistive (gate
leakage).
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 1 (12/12/06)
Page 2.1-36
UDSM CMOS Technology Summary
• Increased transconductance and frequency capability
• Low power supply voltages
• Reduced parasitics
• Gate leakage causes challenges for analog applications of UDSM technology
• Other??
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-1
SECTION 2.1 – PN JUNCTIONS
How are PN Junctions used in CMOS?
• PN junctions are used to electrically isolate one semiconductor region from another
• PN diodes
• Creation of the thermal voltage for bandgap purposes
• Depletion capacitors – voltage variable capacitors (varactors)
Components of a pn junction:
1.) p-doped semiconductor – a semiconductor having atoms containing a lack of electrons
(acceptors). The concentration of acceptors is NA in atoms per cubic centimeter.
2.) n-doped semiconductor – a semiconductor having atoms containing an excess of
electrons (donors). The concentration of these atoms is ND in atoms per cubic
centimeter.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-2
Abrupt PN Junction
Metal-semiconductor junction
pn junction Metal-semiconductor junction
p+ semiconductor
n semiconductor
Depletion Region
W
p+ semiconductor
W1 0
W1 = Depletion width on p side
060121-02
n semiconductor
x
W2
W2 = Depletion width on n side
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-3
Influence of Doping Level on the Depletion Regions
Intuitively, one can see that the depletion regions are inversely proportional to the doping
level. To achieve equilibrium, equal and opposite fixed charge on both sides of the
junction are required. Therefore, the larger the doping the smaller the depletion region on
that side of the junction.
The equations that result are:
2(o -vD)
1
W1 =
NA
NA qNA1 + ND
and
W2 =
2(o -vD)
ND qND1 + NA 1
ND
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-4
Mathematical Characterization of the Abrupt PN Junction
Impurity Concentration (cm-3)
Assume the pn junction is open-circuited.
ND
Cross-section of an ideal pn junction:
xp
p+ semiconductor
iD
vD −
NAND
o = Vt ln n 2 ,
i
where
Electric Field (V/cm)
iD
x
+v D
iD
+v D
E0
Potential (V)
Fig. 06-03
kT
Vt = q
ni2 is the intrinsic concentration of silicon.
CMOS Analog Circuit Design
-qNA
060121-03
Symbol for the pn junction:
Built-in potential, o:
NA
Impurity Concentration (cm-3)
qND
-W1
x
0
W2
n semiconductor
+
x
0
xd
xn
ψο
x
xd
060121-04
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-5
Reverse-Biased PN Junctions
Depletion region:
xd = xp + xn = W1 + W2
xd
vD
xp = W1 vR
iD
and
Influence
of vR on
depletion
region width
− vR = 0V +
xd
vR
xn = W2 vR
060121-05
− vR > 0V +
Breakdown voltage (BV):
If vR > BV, avalanche multiplication will
occur resulting in a high conduction state as
illustrated.
iD
BV
vD
Reverse
Bias
Forward
Bias
060121-06
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-6
Depletion Capacitance
Physical viewpoint of the depletion capacitance:
d
xd
W1
−
−
−
−
−
−
W2
060204-01
+
+
+
+
+
+
+ vD −
siA
siA
Cj = d = W1+W2
=
=A
=
Cj
siA
2si(o-vD) ND
q(ND+NA) NA +
siqNAND
2(NA+ND)
Cj0
vD
1 - o
CMOS Analog Circuit Design
1
o-vD
Ideal
NA ND
Cj0
GummelPoon Effect
Reverse Bias
0
v
ψo D
060204-02
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-7
Forward-Biased PN Junctions
When the pn junction is forward-biased, the potential barrier is reduced and significant
current begins to flow across the junction. This current is given by:
-V
D p
Dnnpo qAD ni2
vD
p no
GO
3
iD = Isexp Vt - 1
where Is = qA Lp + Ln L N = KT exp Vt Graphically, the iD versus vD characteristics are given as:
25
20
ln(iD/Is)
iD 15
Is 10
5
0
-5
-4
-3
-2
-1
0
vD/Vt
1
2
3
Decade current
change/60mV
or
Octave current
change/18mV
4
10 x1016
8 x1016
16
iD 6 x10
Is
4 x1016
vD
0V
16
2 x10
060204-03
0
-40
-30
-20
-10
0
vD/Vt
10
20
30
40
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-8
Graded PN Junctions
In practice, the pn junction is graded rather than abrupt.
Impurity
Concentration Impurity profile
approximates a
p+
constant slope
n+
p+
Intrinsic
Concentration
x
x
0
Surface
Junction
060204-04
The previous expressions become:
Depletion region widths2si(o-vD)NDm
W1 = qNA(NA+ND) 2si(o-vD)NAm
W2 = qND(NA+ND) CMOS Analog Circuit Design
Depletion capacitance qN N 1
A D m
si
C
=
A
j
2(N
+N
)
A D
1 m
(o-vD)m
W N
Cj0
= vDm
1 o
where 0.33 m 0.5.
© P.E. Allen - 2006
Chapter 2. – Section 2 (12/12/06)
Page 2.2-9
Metal-Semiconductor Junctions
Ohmic Junctions: A pn junction formed by a highly doped semiconductor and metal.
Energy band diagram
IV Characteristics
I
1
Vacuum Level
;;;;
;;;;
Thermionic
or tunneling
qφm
qφs
qφB
Contact
Resistance
EC
EF
V
EV
n-type semiconductor
n-type metal
Fig. 2.3-4
Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.
Energy band diagram
IV Characteristics
;;;;
;;;;
;;;;
qφB
n-type metal
I
Forward Bias
EC
EF
Reverse Bias
Forward Bias
Reverse Bias
V
EV
Fig. 2.3-5
n-type semiconductor
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-1
SECTION 2.3 – MOS TRANSISTOR
PHYSICAL ASPECTS OF MOS TRANSISTORS
Physical Structure of MOS Transistors in an n-well Technology
Substrate Salicide
Substrate Salicide
Well Salicide
W
W
n+
p+
Shallow
Trench
Isolation
p+
L
nn++
L
Shallow
Trench
Isolation
nnn+++
p-well
n-well
Substrate
Gate Ox
Oxide
p+
p
p-
n-
n
n+
Poly
Salicide Polycide
060204-05
Metal
Width (W) of the MOSFET = Width of the source/drain diffusion
Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions
Note that the MOSFET is isolated from the well/substrate by reverse biasing the resulting
pn junction
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-2
Enhancement MOSFETs
The channel between the source and drain of an enhancement MOSFET is formed when
the proper potential is applied to the gate of the MOSFET. This potential inverts the
material immediately below the gate to the same type of impurity as the source and drain
forming the channel.
VGS=0V
S
0V<VGS<VT V <V (sat)
DS DS
VDS<VDS(sat)
G
D
S
VDS
Cutoff
G
D
VGS>VT
S
VDS
G
VDS<VDS(sat)
D
VDS
Strong Inversion
Weak Inversion
060205-06
How is the threshold voltage determined?
Qb0 QSS Qb - Qb0
= VT0 + |-2F + vSB| - |-2F|
VT = MS -2F - Cox - Cox - Cox
where
Qb 2qNAsi(|-2F+vSB|) QSS is the undesired surface-state charge
Qb0 QSS
VT0 = MS - 2F - Cox - Cox
=
and
2qsiNA
Cox
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-3
Depletion Mode MOSFET
The channel is diffused into the substrate so that a channel exists between the source and
drain with no external gate potential.
Source Gate
Drain
ne
lW
id
th
,W
Bulk
Ch
an
Polysilicon
p+
Fig.
4.3-4
n+
n+
n-channel
Channel
Length, L
p substrate (bulk)
The threshold voltage for a depletion mode NMOS transistor will be negative (a negative
gate potential is necessary to attract enough holes underneath the gate to cause this region
to invert to p-type material).
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-4
Weak Inversion Operation
0V<VGS<VT VDS<VDS(sat)
Weak inversion operation occurs when the applied
gate voltage is below VT and occurs when the surface
of the substrate beneath the gate is weakly inverted.
G
S
Regions of operation according to the surface
potential, S.
S < F :
Drift current versus
diffusion current in
a MOSFET:
VDS
Diffusion
Current
Weak Inversion
Substrate not inverted
F < S < 2F :
(diffusion current)
2F < S :
D
060205-07
Channel is weakly inverted
Strong inversion (drift current)
log iD
Diffusion Current
Drift Current
10-6
10-12
0
VGS
VT
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-5
LAYOUT OF MOS TRANSISTORS
Layout of a Single MOS transistor:
L
STI
L
Well/Bulk
Well/Bulk
Drain
Drain
W
W
p-well
n-well
Gate Source
Gate Source
060223-01
Comments:
• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.
• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-6
Geometric Effects
Orientation:
Devices oriented in the same direction match more precisely than those oriented in other
directions.
;;;
;;;
;;;
;;;
Good Matching
;;;;;
;;;;;
;;
;;
Poorer Matching
041027-02
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-7
Diffusion and Etch Effects
• Poly etch rate variation – use dummy elements to prevent etch rate differences.
;;
;;
;;
;;
;;
;;;
;;
;;
;;
;;
;;;
;;
;;
;;
;;
;;;
;;
;;
;;;;;
Dummy
Gate
Dummy
Gate
041027-03
• Do not put contacts on top of the gate for matched transistors.
• Be careful of diffusion interactions for diffusions near the channel of the MOSFET
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-8
Thermal and Stress Effects
• Oxide gradients – use common centroid geometry layout
• Stress gradients – use proper location and common centroid geometry layout
• Thermal gradients – keep transistors well away from power devices and use common
centroid geometry layout with interdigitated transistors
Examples of Common Centroid Interdigitated transistor layout:
SA/SB
DA
B
DA
A
GA
GB
GB
GA
Interdigitated, common centroid layout
041027-04
A
B
GA
GB
GB
GA
B
A
Dummy Gate
B
SA/SB
Dummy Gate
A
DB
Dummy Gate
SA/SB
Dummy Gate
DA
DB
DB SB/SA DA
Cross-Coupled Transistors
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-9
MOS Transistor Layout
Photolithographic invariance (PLI) are transistors that exhibit identical orientation. PLI
comes from optical interactions between the UV light and the masks.
Examples of the layout of matched MOS transistors:
1.) Examples of mirror symmetry and photolithographic invariance.
;;
;
;;
;
;;
;
;;;
Mirror Symmetry
CMOS Analog Circuit Design
;;;;
;;
;;;;
;;
Photolithographic Invariance
Fig. 2.6-05
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-10
MOS Transistor Layout - Continued
2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.
;;
;
;;
;
;;
;
;;;
Metal 2
Via 1
;;;;
;
;;
;;
;
;;
;
;;
;;
;
;;;;
;
;;
;;
;
;;;;;;;;
Metal 1
Fig. 2.6-06
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 3 (12/12/06)
Page 2.3-11
MOS Transistor Layout - Continued
3.) Compact layout of the previous example.
Metal 2
;;
;;;
;;
;;
;;;
;;
;;
;;;
;;
;;
;;;;;
Via 1
Metal 2
CMOS Analog Circuit Design
Metal 1
Fig. 2.6-07
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-1
SECTION 2.4 – CAPACITORS
INTRODUCTION
Types of Capacitors for CMOS Technology
1.) PN junction (depletion)
xd
capacitors
W1
W2
−
−
−
−
−
−
+
+
+
+
+
+
+ vD −
060204-01
G
2.) MOSFET gate capacitors
d
D,S,B
Cox
n+
n+
Cjunction
p+
p-well
060207-01
3.) Conductor-insulator-conductor
capacitors
Top Conductor
Bottom
Conductor
Dielectric
Insulating layer
CMOS Analog Circuit Design
060206-02
Chapter 2. – Section 4 (12/12/06)
© P.E. Allen - 2006
Page 2.4-2
Characterization of Capacitors
What characterizes a capacitor?
1.) Dissipation (quality factor) of a capacitor is
C
Q = CRp = Rs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the
electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.
3.) The density of the capacitor in Farads/area.
4.) The absolute and relative accuracies of the capacitor.
5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).
6.) The variation of a variable capacitance with the control voltage.
7.) Linearity, q = Cv.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-3
PN JUNCTION CAPACITORS
PN Junction Capacitors in a Well
Generally made by diffusion into the well.
Anode
;;;
;;;
Cj
n+
Cathode
rD
Cj
Cw
p+
n-well
C
VA
p+
n+
Rwj
Rw
Depletion
Region
Rwj
Substrate
Anode
VB
Rwj
Cathode
Rs
p- substrate
Fig. 2.5-011
Layout:
n+ diffusion
Minimize the distance between the p+ and n+ diffusions.
Two different versions have been tested.
1.) Large islands – 9μm on a side
2.) Small islands – 1.2μm on a side
p+ diffusion
n-well
Fig. 2.5-1A
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 4 (12/12/06)
Page 2.4-4
PN-Junction Capacitors – Continued
The anode should be the floating node and the cathode must be connected to ac ground.
Experimental data (Q at 2GHz, 0.5μm CMOS)†:
Cmax
Cmin
Qmin
120
Qmax
100
3
2.5
Large Islands
Small Islands
2
1.5
Anode
1
C
R-X
Bridge
0.5
0
Cathode
Cathode
Voltage
C
Anode
80
QAnode
CAnode (pF)
4
3.5
R-X
Bridge
60
40
Small Islands
Cathode
Cathode
Voltage
Large Islands
20
0
0
0.5
1
1.5
2
2.5
Cathode Voltage (V)
3
3.5
0
0.5
1
1.5
2
2.5
Cathode Voltage (V)
3
3.5
060206-03
Terminal Small Islands (598 1.2μm x1.2μm)
Large Islands (42 9μm x 9μm)
Under Test Cmax/Cmin
Qmin
Qmax
Cmax/Cmin
Qmin
Qmax
Anode
1.23
94.5
109
1.32
19
22.6
Cathode
1.21
8.4
9.2
1.29
8.6
9.5
Electrons as majority carriers lead to higher Q because of their higher mobility.
The resistance, Rwj, is reduced in small islands compared with large islands higher
†
E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-5
MOSFET GATE CAPACITORS
MOSFET Gate Capacitor Structure
The MOSFET gate capacitors have the gate as one terminal of the capacitor and some
combination of the source, drain, and bulk as the other terminal.
In the model of the MOSFET gate capacitor shown below, the gate capacitance is really
two capacitors in series depending on the condition of the channel.
1
Cgate = 1
1
Cox + Cj
S
G
B
D
Cox
Cox
n+
Cjunction
G Channel Resistance
D
S
n+
p+
p-well
Cjunction
060207-02
B
Bulk Resistance
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-6
MOSFET Gate Capacitor with D = S = B
In this configuration, the MOSFET gate capacitor has 5 regions of operation. For the
first four regions, the gate capacitance is the series combination of Cox and Cj.
1
Cgate = 1
1
Cox + Cj
1.) Channel is not formed (accumulation mode), Cgate = Cox
2.) The channel is in depletion mode (the channel resistance is large and Cj Cox),
Cgate 0.5Cox 0.5Cj
3.) The channel is weak inversion (channel resistance is large and Cj < Cox ),
Cgate Cj
4.) The channel is in moderate inversion (channel resistance is decreasing and Cj < Cox ),
Cj < Cgate < Cox
5.) The channel is in strong inversion (Cox is in parallel with Cj and Cj < Cox),
Cgate Cox
(The bulk resistance will influence the above when Cgate Cj)
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-7
Illustration of the MOSFET Gate Capacitor as a function of VGS with D=S=B
G
D,S,B
Capacitance
Cox
Cox
n+
n+
Cjunction
p+
Cox
Weak
Inv.
Accumulation
p-well
Depletion
Strong
Inversion
VG-VD,S,B
Moderate
Inversion
060207-03
Conditions:
• D=S=B
• Operates from accumulation to inversion
• Nonmonotonic
• Nonlinear
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-8
MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode)
G
D,S
B
Cox
Cox
n+
Cjunction
Capacitance
n+
p+
Cox
B=D= S
Inversion
Mode MOS
p-well
VT shift
if VBS ≠ 0
0
VG-VD,S
060207-04
Conditions:
• D = S, B = VSS
• Accumulation region removed by connecting bulk to VDD
• Nonlinear
• Channel resistance:
L
Ron = 12KP'(VBG-|VT|)
• LDD transistors will give lower Q because of the increased series resistance
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
;;;
;;;
;;;;;;;;
;;;
;;;;;;;;
Inversion Mode NMOS Capacitor
Best results are obtained
Shown in inversion mode
when the drain-source are
on ac ground.
Cov
Bulk R C
sj
p+
Page 2.4-9
D,S
G
Cox
j
n+
Rd
p- substrate/bulk
Csi Cd
Cd
D,S
Cov
Rd
B
n+
G
n- LDD
Rsi
Fig. 2.5-2
†
Experimental Results (Q at 2GHz, 0.5μm CMOS) :
Cmin
Cmax
4.5
34
VG = 2.1V
3.5
3
QGate
CGate (pF)
4
VG = 1.8V
2.5
VG = 2.1V
32
30
28
VG = 1.8V
VG = 1.5V
26
VG = 1.5V
2
Qmin
Qmax
38
36
24
22
1.5
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
Fig. 2.5-1c
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
†
E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-10
Accumulation Mode NMOS Gate Capacitor
G
B
Capacitance
Cox
Cox
n+
n+
Inversion
Depletion
Accumulation
VG-VD,S,B
060207-05
Conditions:
• Remove p+ drain and source and put n+ bulk contacts instead.
• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.
• Reasonably linear capacitor for values of VGB > 0,
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-11
;;;
Accumulation Mode Capacitor – Continued
Best results are
Shown in depletion mode.
obtained when the
drain-source are on
Cov
Bulk
Cw
ac ground.
p+
+
Rs
n
Rw
;;;
;;;;
D,S
G
Cov
Cox
Rd
Rd
Cd
Cd
n- LDD
D,S
B
n+
G
n- well
p substrate/bulk
Fig. 2.5-5
Experimental Results (Q at 2GHz, 0.5μm CMOS)†:
Cmin
CGate (pF)
3.6
VG = 0.9V
3.2
VG = 0.3V
40
VG = 0.6V
VG = 0.6V
35
2.8
VG = 0.9V
30
VG = 0.3V
2.4
Qmin
Qmax
45
QGate
Cmax
4
2
25
0
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
0
3.5
0.5
1
1.5
2
2.5
Drain/Source Voltage (V)
3
3.5
Fig. 2.5-6
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
CMOS Analog Circuit Design
© P.E. Allen - 2006
†
Chapter 2. – Section 4 (12/12/06)
Page 2.4-12
CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORS
Polysilicon-Oxide-Polysilicon (Poly-Poly) Capacitors
LOCOS Technology:
A
B
A very linear capacitor
IOX
with minimum bottom
Polysilicon II
IOX
IOX
plate parasitic.
Polysilicon I
FOX
FOX
substrate
VDD
DSM Technology:
A very linear capacitor with
larger bottom plate parasitic.
A
B
p+
n+
Shallow
Trench
Isolation
Shallow
Trench
Isolation
n-well
060207-06
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-13
Metal-Insulator-Metal (MiM) Capacitors
In some processes, there is a thin dielectric between a metal layer and a special metal
layer called “capacitor top metal”. Typically the capacitance is around 1fF/μm2 and is at
the level below top metal.
Protective Insulator Layer
Metal Via
Intermediate
Oxide
Layers
Vias connecting top
plate to top metal
Capacitor Top Metal
Capacitor
dielectric
Capacitor bottom plate
Vias connecting bottom
plate to lower metal
Vias connecting bottom
plate to lower metal
Top
Metal
Second level
from top metal
Third level
from top metal
Fourth level
from top metal
060530-01
Good matching is possible with low parasitics.
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 4 (12/12/06)
Page 2.4-14
Metal-Insulator-Metal Capacitors – Lateral and Vertical Flux
Capacitance between conductors on the same level and use lateral flux.
Fringing field
Top view:
Metal
Metal
Metal 3
+
-
+
-
Metal 2
-
+
-
+
Metal 1
+
-
+
-
Side view:
Fig2.5-9
These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-15
More Detail on Horizontal Metal Capacitors†
Some of the possible metal capacitor structures include:
1.) Horizontal parallel plate
(HPP).
030909-01
2.) Parallel wires (PW):
Lateral View
030909-02
Top View
†
R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3,
March 2002, pp. 384-393.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-16
Horizontal Metal Capacitors - Continued
3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
030909-04
Lateral View
CMOS Analog Circuit Design
Top View
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-17
Horizontal Metal Capacitors - Continued
Experimental results for a CMOS process with 3 layers of metal, Lmin =0.5μm, tox =
0.95μm and tmetal = 0.63μm for the bottom 2 layers of metal.
Structure Cap. Density
(aF/μm2)
VPP
PW
HPP
158.3
101.5
35.8
Caver. Std. Dev.
(fF)
(pF)
18.99
103
33.5
315
6.94
427
Q @ Rs () Breakfres.
Caver. (GHz) 1 GHz
down (V)
0.0054 3.65
14.5
0.57
355
0.0094 1.1
8.6
0.55
380
0.0615 6.0
21
1.1
690
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24μm,
tox = 0.7μm and tmetal = 0.53μm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure
(1 pF)
VPP
VB
HPP
MIM
Cap.
Density
(aF/μm2)
1512.2
1281.3
203.6
1100
Cap.
Caver. Area
2
(pF) (μm ) Enhanc
ement
1.01 670
7.4
1.07 839.7
6.3
1.09 5378
1.0
1.05 960.9
5.4
Std.
Dev.
(fF)
5.06
14.19
26.11
-
Q @ Breakfres.
(GHz) 1 GHz down
(V)
0.0050 >40
83.2
128
0.0132 37.1 48.7
124
0.0239 21
63.8
500
11
95
-
Caver.
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 4 (12/12/06)
Page 2.4-18
12
Number of dice
Horizontal Metal Capacitors - Continued
Histogram of the capacitance distribution for
the above case (1 pF):
HPP
VPP
PW
10
8
6
4
2
Experimental results for a digital CMOS
0
process with 7 layers of metal, Lmin =
0.24μm, tox = 0.7μm and tmetal = 0.53μm for
the bottom 5 layers of metal (all capacitors = 10pF):
96
Cap.
Density
(aF/μm2)
VPP
VB
HPP
1480.0
1223.2
183.6
11.46 7749
10.60 8666
10.21 55615
8.0
6.6
1.0
MIM
1100
10.13 9216
6.0
73.43 0.0064
73.21 0.0069
182.1 0.0178
-
98
σc
100
102
104
-
106
030909-05
Caver
Std.
Cap.
Caver. Area
2
C
Dev.
Enhanc
(pF) (μm )
aver.
ement (fF)
Structure
(10 pF)
CMOS Analog Circuit Design
94
Q @ Breakfres.
1
(GHz) GHz down
(V)
11.3
11.1
6.17
26.6
17.8
23.5
125
121
495
4.05
25.6
-
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-19
DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORS
Capacitor Errors
1.) Dielectric gradients
2.) Edge effects
3.) Process biases
4.) Parasitics
5.) Voltage dependence
6.) Temperature dependence
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-20
Capacitor Errors - Oxide Gradients
Error due to a variation in dielectric thickness across the wafer.
Common centroid layout - only good for one-dimensional errors:
Common centroid layout
No common centroid layout
2C
C
C
2C
060207-07
An alternate approach is to layout numerous repetitions and connect them randomly to
achieve a statistical error balanced over the entire area of interest.
Improved matching of three components, A, B, and C:
CMOS Analog Circuit Design
A
B
C
A
B
C
A
B
C
C
A
B
C
A
B
C
A
B
B
C
A
B
C
A
B
C
A
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-21
Capacitor Errors - Edge Effects
There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.
C
A
B
Improved matching achieve by matching the surroundings of A and B.
C
A
B
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-22
Process Bias on Capacitors
Consider the following two capacitors:
Δx
L1
C1
Δx
Δx
L2
If L1 = L2 = 2μm, W2 = 2W1 = 2μm
and x = 0.1μm, the ratio of C2 to C1
W1
can be written as,
C2 (2-.2)(4-.2) 3.8
C1 = (2-.2)(2-.2) = 1.8 = 2.11 5.6% error in matching
Δx
C2
W2
041022-03
How can this matching error be reduced?
The capacitor ratios in general can be expressed as,
2 x
C2 (L2-2x)(W2-2x) W21 - W2 W2 2x
2x W2 2x 2x
=
=
1
1
+
W2 W1 W11 - W2 + W1 C1 (L1-2x)(W1-2x) W1 2x W1
1
W1 Therefore, if W2 = W1, the matching error should be minimized. The best matching
results between two components are achieved when their geometries are identical.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-23
Replication Principle
Based on the previous result, a way to minimize the matching error between two or more
geometries is to insure that the matched components have the same area to periphery
ratio. Therefore, the replication principle requires that all geometries have the same areaperiphery ratio.
Correct way to match the previous capacitors (the two C2 capacitors are connected
together):
Δx
Δx
Δx
Δx
Δx
If L1 = L2 = 2μm, W2 = L2
C2
L1
C1
2W1 = 2μm and x =
0.1μm, the ratio of C2
W2
W1
to C1 can be written as,
C2 2(2-.2)(2-.2) 2·1.8
C1 = (2-.2)(2-.2) = 1.8 = 2 0% error in matching
L2
C2
W2
Δx
041022-04
The replication principle works for any geometry and includes transistors, resistors as
well as capacitors.
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 4 (12/12/06)
Page 2.4-24
Capacitor Errors - Relative Accuracy
Capacitor relative accuracy is proportional to the area of the capacitors and inversely
proportional to the difference in values between the two capacitors.
For example,
0.04
Relative Accuracy
Unit Capacitance = 0.5pF
0.03
Unit Capacitance = 1pF
0.02
0.01
Unit Capacitance = 4pF
0.00
CMOS Analog Circuit Design
1
2
4
8
16
Ratio of Capacitors
32
64
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-25
Capacitor Errors - Parasitics
Parasitics are normally from the top and bottom plate to ac ground which is typically the
substrate.
Top Plate
Top
plate
parasitic
Desired
Capacitor
Bottom
plate
Bottom Plate
parasitic
060702-08
Top plate parasitic is 0.01 to 0.001 of Cdesired
Bottom plate parasitic is 0.05 to 0.2 Cdesired
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-26
Layout Considerations on Capacitor Accuracy
Decreasing Sensitivity to Edge Variation:
Fringing
Field
Fringing
Field
?
?
Sensitive to alignment errors in the
upper and lower plates and loss of
capacitance flux (smaller capacitance).
Insensitive to alignment errors and the
flux reaching the bottom plate is larger
resulting in large capacitance. 060207-09
A structure that minimizes the ratio of perimeter to area (circle is best).
Bottom Plate
Top
Plate
060207-10
CMOS Analog Circuit Design
Reduced bottom plate parasitic.
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-27
Accurate Matching of Capacitors†
Accurate matching of capacitors depends on the following influence:
1.) Mismatched perimeter ratios
2.) Proximity effects in unit capacitor photolithography
3.) Mismatched long-range fringe capacitance
4.) Mismatched interconnect capacitance
5.) Parasitic interconnect capacitance
Long-range fringe capacitance:
?
? ?
?
Shield to collect long-range fringe fields
061216-04
Obviously there will be a tradeoff between matching and speed.
†
M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-State
Circuit, vo. 29, No. 5, May 1994, pp. 611-616.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-28
Shielding Capacitors
The key to shielding is to determine and control the electric fields.
Consider the following noisy conductor and its influence on the substrate:
Increased Parasitic Capacitance
Noisy Conductor
Noisy Conductor
Separate
Ground
Shield
Substrate
Substrate
060118-10
Use of bootstrapping to reduce capacitor bottom plate parasitic:
Top Plate
Cpar
Bottom Plate
Substrate
+1
2Cpar
2Cpar
Shield
Substrate
060316-02
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-29
Definition of Temperature and Voltage Coefficients
In general a variable y which is a function of x, y = f(x), can be expressed as a Taylor
series,
y(x = x0) y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···
where the coefficients, ai, are defined as,
df(x) |
1 d2f(x) |
a1 = dx x=x0 , a2 = 2 dx2 x=x0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature or voltage
coefficients depending on whether x is temperature or voltage.
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1
df(T) |
TCF(T=T0) = f(T=T0) dT T=T0 parts per million/°C (ppm/°C)
or more simply,
1 df(T)
TCF = f(T) dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
CMOS Analog Circuit Design
Chapter 2. – Section 4 (12/12/06)
© P.E. Allen - 2006
Page 2.4-30
Capacitor Errors - Temperature and Voltage Dependence
MOSFET Gate Capacitors:
Absolute accuracy ±10%
Relative accuracy ±0.2%
Temperature coefficient +25 ppm/C°
Voltage coefficient -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors:
Absolute accuracy ±10%
Relative accuracy ±0.2%
Temperature coefficient +25 ppm/C°
Voltage coefficient -20ppm/V
Metal-Dielectric-Metal Capacitors:
Absolute accuracy ±10%
Relative accuracy ±0.6%
Temperature coefficient +??? ppm/C°
Voltage coefficient -???ppm/V
Accuracies depend upon the size of the capacitors.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 4 (12/12/06)
Page 2.4-31
Future Technology Impact on Capacitors
What will be the impact of scaling down in CMOS technology?
• The capacitance can be divided into gate capacitance and overlap capacitance.
Gate capacitance varies with external voltage changes
Overlap capacitances are constant with respect to external voltage changes
As the channel length decreases, the gate capacitance becomes less of the total
capacitance and consequently the Cmax/Cmin will decrease. However, the Q of the
capacitor will increase because the physical dimensions are getting smaller.
• For UDSM, the gate leakage current will eliminate gate capacitors from being useful.
Best capacitor for future scaled CMOS?
Polysilicon-polysilicon or metal-metal (too much leakage current in gate capacitors)
Best varactor for future scaled CMOS?
The standard mode CMOS depletion capacitor because Cmax/Cmin is larger than
that for the accumulation mode and Q should be sufficient. The pn junction will be
more useful for UDSM.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-1
SECTION 2.5 – RESISTORS
Types of Resistors Compatible with CMOS Technology
1.) Diffused and/or implanted resistors.
2.) Well resistors.
3.) Polysilicon resistors.
4.) Metal resistors.
n-well Resistor
n+
n+
Shallow
Trench
Isolation
n-well
060214-01
CMOS Analog Circuit Design
p+
Shallow
Trench
Isolation
L
Polysilicon Resistor
Diffused Resistor
n+
Shallow
Trench
Isolation
L
L
n-well
Substrate
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-2
Characterization of Resistors
1.) Value
L
R= A
Area = A
Area = A
L
nt
Curre
AC and DC resistance
2.) Linearity
Does V = IR?
Velocity saturation of carriers
L
t
Curren
050217-02
i
Linear Resistor
Velocity saturation
Breakdown
Voltage
3.) Power
P = VI = I2R
4.) Current
Electromigration
5.) Parasitics
Metal
R
R
060211-01
050304-04
R
Cp
2
Cp
060210-01
v
Cp
2
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-3
MOS Resistors - Source/Drain Resistor
Metal
SiO2
First Level Metal
p+
FOX
FOX
Tungsten
Plug
p+
n- well
Intermediate
Oxide Layer
p+
L
Tungsten
Plug
STI
STI
n-well
p- substrate
060214-02
Older LOCOS Technology
Diffusion:
Ion Implanted:
10-100 ohms/square
500-2000 ohms/square
Absolute accuracy = ±35%
Absolute accuracy = ±15%
Relative accuracy=2% (5μm), 0.2% (50μm) Relative accuracy=2% (5μm), 0.15% (50μm)
Temperature coefficient = +1500 ppm/°C
Temperature coefficient = +400 ppm/°C
Voltage coefficient 200 ppm/V
Voltage coefficient 800 ppm/V
Comments:
• Parasitic capacitance to substrate is voltage dependent.
• Piezoresistance effects occur due to chip strain from mounting.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-4
Polysilicon Resistor
Metal
Polysilicon resistor
First Level Metal
Tungsten Plug
FOX
p- substrate
p+Substrate
Older LOCOS Technology
060214-03
30-100 ohms/square (unshielded)
100-500 ohms/square (shielded)
Absolute accuracy = ±3 0%
Relative accuracy = 2% (5 μm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient 100 ppm/V
Comments:
• Used for fuzzes and laser trimming
• Good general resistor with low parasitics
© P.E. Allen - 2006
CMOS Analog Circuit Design
Chapter 2. – Section 5 (12/12/06)
Page 2.5-5
N-well Resistor
Metal
First Level Metal
n+
FOX
FOX
n- well
L
FOX
Tungsten
Plug
Tungsten
Plug
Intermediate
Oxide Layer
n+
STI
n+
L
STI
n-well
p- substrate
060214-04
LOCOS Technology
p-substrate
1000-5000 ohms/square
Absolute accuracy = ±40%
Relative accuracy 5%
Temperature coefficient = 4000 ppm/°C
Voltage coefficient is large 8000 ppm/V
Comments:
• Good when large values of resistance are needed.
• Parasitics are large and resistance is voltage dependent
• Could put a p+ diffusion into the well to form a pinched resistor
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-6
Metal as a Resistor
Illustration:
Intermediate
Oxide
Layers
A
L1
L5
Tungsten Plug
Tungsten Plug
L2
B
L4
L3
Salicide
Second
Level
Metal
First
Level
Metal
Substrate
060214-05
Resistance from A to B = Resistance of segments L1, L2, L3, L4, and L5 with some
correction subtracted because of corners.
Sheet resistance:
50-70 m/ ± 30% for lower or middle levels of metal
30-40 m/ ± 15% for top level metal
Watch out for the current limit for metal resistors.
Contact resistance varies from 5 to 10.
Tempco +4000 ppm/°C
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-7
Thin Film Resistors
A high-quality resistor fabricated from a thin nickel-chromium alloy or a siliconchromium mixture.
Uppermost metal layer:
Protective Insulator Layer
Intermediate
Oxide
Layers
Thin Film Resistor
L
Top
Metal
Second
level
from
top metal
W
060612-01
Performance:
Sheet resistivity is approximately 5-10 ohms/square
Temperature coefficients of less than 100 ppm/°C
Absolute tolerance of better than ±0.1% using laser trimming
Selectivity of the metal etch must be sufficient to ensure the integrity of the thin-film
resistor beneath the areas where metal is etched away.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-8
Resistor Layout Techniques
Metal
Metal
LOCOS
Technology
FOX
FOX
FOX
Substrate
FOX
Active area (diffusion) Well diffusion
Active area (diffusion)
Metal
DSM
Tungsten
Technology Plug
Metal
Tungsten Plug
Intermediate Oxide
Intermediate Oxide
Substrate
Substrate
Substrate
Active area (diffusion)
Contact
FOX
Substrate
Active area or Polysilicon
W
Well diffusion
Active area
Active area (diffusion)
Well diffusion
W
Contact
Cut
Cut
L
Metal 1
Metal 1
L
Diffusion or polysilicon resistor
Well resistor
CMOS Analog Circuit Design
060219-01
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-9
Extending the Length of Resistors
Snaked Resistors:
L3
L1
L2
L4
L4
L4
L4
L4
L2
060220-01
Corner corrections:
0.5
1.45
1.25
Fig. 2.6-16B
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-10
Extending the Length of Resistors
Series Resistors:
L1
W
060220-02
Resistor Ending Influence:
0.5
0.3
0.1
050416-02
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-11
Process Bias Influence on Resistors
Process bias is where the dimensions of the fabricated geometries are not the same as the
layout data base dimensions.
Process biases introduce systematic errors.
Consider the effect of over-etchingAssume that etching introduces a process bias of 0.1μm. Two resistors designed to
have a ratio of 2:1 have equal lengths but the widths are different by a factor of two.
3.8μm
1.8μm
10μm
4μm
2μm
041020-01
The actual matching ratio due to the etching bias is,
R2 W1 4-0.2 3.8
R1 = W2 = 2-0.2 = 1.8 = 2.11
5.6% error in matching
Use the replication principle to eliminate this error.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-12
Etch Rate Variations – Polysilicon Resistors
The size of the area to be etched determines the etch rate. Smaller areas allow less
access to the etchant while larger areas allow more access to the etchant. This is
illustrated below:
B
Dummy
A
Slower
Etch Rate
Slower
Etch Rate
C
A
B
C
Dummy
Slower
Etch Rate
041025-04
The objective is to make A = B = C. In the left-hand case, B is larger due to the slower
etch rates on both sides of B. In the right-hand case, the dummy strips have caused the
etch rates on both sides of A, B and C to be identical leading to better matching.
It may be advisable to connect the dummy strips to ground or some other low impedance
node to avoid static electrical charge buildup.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-13
Diffusion Interaction – Diffused Resistors
Problem:
Consider three adjacent p+ diffusions into a n epitaxial region,
Areas of diffusion interaction
A
p+
B
p+
Contours of
constant doping
C
p+
n-epi
041025-05
If A, B, and C are resistors that are to be matched, we see that the effective concentration
of B is larger than A or C because of diffusion interaction. This would cause the B
resistor to be smaller even though the geometry is identical.
Solution: Place identical dummy resistors to the left of A and right of C. Connect the
dummy resistors to a low impedance to prevent the formation of floating diffusions that
might increase the sensitivity to latchup.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-14
+
+
+
+
+
Resistor Segment
+
Resistor Segment
+
+
Resistor Segment
Resistor Segment
Resistor Segment
Resistor Segment
Cold
Resistor Segment
Two possible resistor
layouts with regard to
the thermoelectric
effect:
Resistor Segment
Thermoelectric Effects
The thermoelectric effect, also called the Seebeck effect, is a potential difference that is
developed between two dissimilar materials that are at different temperatures. The
potential developed is given as,
V = S·T
where,
S = Seebeck coefficient ( 0.4mV/°C)
T = temperature difference between the two metals
Thus, a temperature difference between the contacts to a resistor and the resistor of 1°C
can generate a voltage of 0.4mV causing problems in certain circuits (bandgap).
Hot
-
Thermoelectric potentials add
CMOS Analog Circuit Design
Thermoelectric potentials cancel 041026-07
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-15
High Sheet Resistivity Resistor Layout
High sheet resistivity resistors must use p+ or n+ in order to make contacts to metal.
Thus, there is plenty of opportunity for the thermoelectric effect to cause problems if care
is not taken. Below are three high sheet resistor layouts with differing thermoelectric
performance.
n+ resistor
head Cold
Vertical misalignment
causes resistor errors
n diffused
resistor
n+ resistor
head
Hot
Sensitive to
thermoelectric
effects.
CMOS Analog Circuit Design
Resistor layout that
minimizes thermoelectric
effect and misalignment
Sensitive to
misalignment.
041027-01
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-16
Future Technology Impact on Resistors
What will be the impact of scaling down in CMOS technology?
• If the size of the resistor remains the same, there will be little impact.
• If the size scales with the technology, the contacts and connections to the resistors will
have more influence on the resistor.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 5 (12/12/06)
Page 2.5-17
MOS Passive RC Component Performance Summary
Component Type
Range of
Values
Absolute Relative Temperature Voltage
Accuracy Accuracy Coefficient Coefficient
10%
0.1%
20ppm/°C ±20ppm/V
MOSFET gate Cap.
6-7 fF/μm2
Poly-Poly Capacitor
0.3-0.4 fF/μm2
20%
0.1%
25ppm/°C
±50ppm/V
Metal-Metal Capacitor
0.1-1fF/μm2
10%
0.6%
??
??
Diffused Resistor
10-100 /sq.
35%
2%
1500ppm/°C 200ppm/V
Ion Implanted Resistor 0.5-2 k/sq.
15%
2%
400ppm/°C 800ppm/V
30-200 /sq.
30%
2%
1500ppm/°C 100ppm/V
1-10 k/sq.
40%
5%
8000ppm/°C 10kppm/V
Top Metal Resistor
30 m/sq.
15%
2%
4000ppm/°C
??
Lower Metal Resistor
70 m/sq.
28%
3%
4000ppm/°C
??
Poly Resistor
n-well Resistor
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-1
SECTION 2.6 – INDUCTORS
Characterization of Inductors
1.) Value of the inductor
Spiral inductor†:
2r
L μ0n2r = 4x10-7n2r 1.2x10-6n2r
n=3
L
2.) Quality factor, Q = R
060216-02
1
3.) Self-resonant frequency: fself = LC
†
H.M Greenhouse, “Design of Planar Rectangular Microelectronic Inductors,” IEEE Trans. Parts, Hybrids, and Packaging, vol. 10, no. 2, June
1974, pp. 101-109.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-2
IC Inductors
What is the range of values for on-chip inductors?
;;;;;;
;;;;;;
;;;;;;
12
Inductor area is too large
Inductance (nH)
10
8
6
ωL = 50Ω
4
Interconnect parasitics
are too large
2
0 0
10
20
30
40
Frequency (GHz)
50
Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz.
1
1
L= 2 2 =
= 5nH
4 fo C (2·109)2·5x10-12
Note: Off-chip connections will result in inductance as well.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-3
Candidates for inductors in CMOS technology are:
1.) Bond wires
2.) Spiral inductors
3.) Multi-level spiral
4.) Solenoid
Bond wire Inductors:
β
β
d
Fig.6-6
• Function of the pad distance d and the bond angle • Typical value is 1nH/mm which gives 2nH to 5nH in typical packages
• Series loss is 0.2 /mm for 1 mil diameter aluminum wire
• Q 60 at 2 GHz
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-4
Planar Spiral Inductors in CMOS Technology
I
;;;;;
W
SiO2
I
ID
I
S
I
Nturns = 2.5
Silicon
Fig. 6-9
Typically: 3 < Nturns < 5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow
through the center.
Loss Mechanisms:
• Skin effect
• Capacitive substrate losses
• Eddy currents in the silicon
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-5
Planar Spiral Inductors on a Lossy Substrate
Top Metal
Top Metal
W
Next Level
Metal
S
Vias
Oxide
Oxide
Next Level
Metal
D
Silicon Substrate
N turns
030828-01
D
• Spiral inductor is implemented using metal layers in CMOS technology
• Topmost metal is preferred because of its lower resistivity
• More than one metal layer can be connected together to reduce resistance or area
• Accurate analysis of a spiral inductor requires complex electromagnetic simulation
• Optimize the values of W, S, and N to get the desired L, a high Q, and a high selfresonant frequency
• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-6
Inductor Modeling
Model:
Cp
L
Cox
2
Cox
2
C1
Rs
R1
C1
030828-02
R1
37.5μ0N2a2
L 11D-14a
ox
Cox = W·L· tox
L
Rs W(1-e-t/)
R1 ox
Cp = NW2L· tox
2
C1 WLCsub
WLCsub
2
where
μ0 = 4x10-7 H/m (vacuum permeability)
= conductivity of the metal
a = distance from the center of the inductor to the middle of the windings
L = total length of the spiral
t = thickness of the metal
= skin depth given by = 2/Wμ0
Gsub(Csub) is a process-dependent parameter
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-7
Inductor Modeling – Continued
Definition of the previous components:
Rs is the low frequency resistive loss of a metal and the skin effect
Cp arises from the overlap of the cross-under with the rest of the spiral. The lateral
capacitance from turn-to-turn is also included.
Cox is the capacitance between the spiral and the substrate
R1 is the substrate loss due to eddy currents
C1 is capacitance of the substrate
Design specifications:
L = desired inductance value
Q = quality factor
fSR = self-resonant frequency. The resonant frequency of the LC tank represents the
upper useful frequency limit of the inductor. Inductor operation frequency should be
lower than fSR, f < fSR.
ASITIC: A software tool for analysis and simulation of CMOS spiral inductors and
transformers.
http://formosa.eecs.berkeley.edu/~niknejad/asitic.html
CMOS Analog Circuit Design
Chapter 2. – Section 6 (12/12/06)
© P.E. Allen - 2006
Page 2.6-8
Guidelines for Designing CMOS Sprial Inductors†
D – Outer diameter:
• As D increases, Q increases but the self-resonant frequency decreases
• A good design generally has D < 200μm
W – Metal width:
• Metal width should be as wide as possible
• As W increases, Q increases and Rs decreases
• However, as W becomes large, the skin effects are more significant, increasing Rs
• A good value of W is 10μm < W < 20μm
S – Spacing between turns:
• The spacing should be as small as possible
• As S and L increase, the mutual inductance, M, decreases
• Use minimum metal spacing allowed in the technology but make sure the interwinding capacitance between turns is not significant
N – Number of turns:
• Use a value that gives a layout convenient to work with other parts of the circuit
†
Jaime Aguilera, et. al., “A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Applications,” Applied Microwave &
Wireless, pp. 56-65, Oct. 2001.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-9
Design Example
A 2GHz LC tank is to be designed as a part of LC oscillator. The C value is given as 3pF.
(a) Find value of L. (b) Design a spiral inductor with L value (± 5% range) from (a) using
ASITIC. Optimize design parameters, W, S, D and N to get a high Q (Qmin = 5). Show L,
Q, fSR value obtained from simulation. (c) Show the layout. (d) Give a lumped circuit
model.
Solution
(a) LC tank oscillation frequency is given as 2GHz.
1
1
1
-9
L=
=
osc =
9 2
-12 = 2.1110
2
,
osc C (2 2 10 ) (3 10 )
LC
L = 2.11nH is desired.
(b) L = 2.11nH(± 5%) is used as input parameter. Several design parameters are tried
to get high Q and fSR values. Final design has
• Parameters: W = 19um, S = 1um, D = 200um, N = 3.5
• Resulting inductor: L = 2.06nH, Q = 7.11, fSR = 9.99GHz @ 2GHz
This design is acceptable as Q > Qmin and f < fSR .
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-10
Design Example-Continued
(c.) ASITIC generates a layout automatically. It can be
saved and imported to use in other tools such as Cadence,
ADS and Sonnet.
(d) Analysis in ASITIC gives the following model.
2.06nH
123fF
4.51
3.5
128fF
-3
The model is usually not symmetrical and this can be used for differential configuration
where none of the two ports are ac-grounded.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-11
Reduction of Capacitance to Ground
Comments concerning implementation:
1.) Put a metal ground shield between the inductor and the silicon to reduce the
capacitance.
• Should be patterned so flux goes through but electric field is grounded
• Metal strips should be orthogonal to the spiral to avoid induced loop current
• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to keep the series resistance low.
3.) Use the metal with the lowest resistance
and farthest away from the substrate.
4.) Parallel metal strips if other metal levels
are available to reduce the resistance.
Example CMOS Analog Circuit Design
Chapter 2. – Section 6 (12/12/06)
© P.E.
Fig. Allen
2.5-12 - 2006
Page 2.6-12
Multi-Level Spiral Inductors
Use of more than one level of metal to make the inductor.
• Can get more inductance per area
• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.
• Multi-level spiral inductors suffer from contact resistance (must have many
parallel contacts to reduce the contact resistance).
• Metal especially designed for inductors is top level approximately 4μm thick.
Q = 5-6, fSR = 30-40GHz. Q = 10-11, fSR = 15-30GHz1. Good for high L in small area.
1
The skin effect and substrate loss appear to be the limiting factor at higher frequencies of self-resonance.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-13
Inductors - Continued
Self-resonance as a function of inductance. Outer dimension of inductors.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Page 2.6-14
Transformers
Transformer structures are easily obtained using stacked inductors as shown below for a
1:2 transformer.
Method of reducing the
inter-winding capacitances.
Measured 1:2 transformer voltage gains:
4 turns
CMOS Analog Circuit Design
8 turns
3
© P.E. Allen - 2006
Chapter 2. – Section 6 (12/12/06)
Transformers – Continued
A 1:4 transformer:
Structure-
Page 2.6-15
Measured voltage gain-
Secondary
(CL = 0, 50fF, 100fF, 500fF and 1pF.
CL is the capacitive loading on the
secondary.)
CMOS Analog Circuit Design
Chapter 2. – Section 6 (12/12/06)
© P.E. Allen - 2006
Page 2.6-16
Summary of Inductors
Scaling? To reduce the size of the inductor would require increasing the flux density
which is determined by the material the flux flows through. Since this material will not
change much with scaling, the inductor size will remain constant.
Increase in the number of metal layers will offer more flexibility for inductor and
transformer implementation.
Performance:
• Inductors
Limited to nanohenrys
Very low Q (3-5)
Not variable
• Transformers
Reasonably easy to build and work well using stacked inductors
• Matching
Not much data exists publicly – probably not good
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-1
SECTION 2.7 – FURTHER CONSIDERATIONS OF CMOS
TECHNOLOGY
PARASITIC BIPOLAR TRANSISTORS
E
B
VC
LC
LC
A Lateral Bipolar Transistor
p+ p+
n+
p+
n-well CMOS technology:
• It is desirable to have the lateral
STI
collector current much larger than the
n-well
vertical collector current.
• Lateral BJT generally has good
060221-01
matching.
Vertical
STI
Lateral Collector
• The lateral BJT can be used as a
Collector
photodetector with reasonably good
Emitter
efficiency.
STI
Substrate
Base
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
A Field-Aided Lateral BJT
Use minimum channel length to
enhance beta:
ßF 50 to 100 depending on the
process
Page 2.7-2
VC
STI
B
LC
E
LC
n+
p+
p+
pp++
Keeps carriers from
flowing at the surface
and reduces 1/f noise
n-well
STI
Substrate
060221-02
Vertical
Collector
STI
Lateral Collector Emitter
Base
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-3
HIGH VOLTAGE CMOS TRANSISTORS
Extended Voltage MOSFETS
The electric field from the source to drain in the channel is shown below.
Electric
Field
Emax
Area = Vp
Area = Vd
0
;;;;
;;;;;;;;;
;;;;;;;;;;;;
;;;;
;;;;;;;;;
;;;;;;;;;;;;
;;;;;;;;;;;;
xp
Pinch-off region
Source
depletion
region
Source n+
Channel
Distance, x
xd
Drain n+
Drain
depletion
region
Substrate depletion region
p - substrate
040920-01
The voltage drop from drain to source is,
VDS = Vp + Vd = 0.5(Emaxxp + Emaxxd) = 0.5Emax(xp + xd)
Emax and xp are limited by hot carrier generation and channel length modulation
requirements whereas these limitations do not exist for xd.
Therefore, to get extended voltage transistors, make xd larger.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-4
Methods of Increasing the Drain Depletion Region
Lightly-Doped Drains (LDD):
;; ;; ;;
;; ;; ;;
Sidewall Spacer
Sidewall Spacer
Poly
n+ source
n+ drain
n S/D diffusion
p substrate
040921-01
• The lateral dimension of the lightly doped area is not large enough to stand higher
voltages.
• The oxide at the drain end is too thin to stand higher voltages
Double Diffused Drains (DDD):
Uses the difference in diffusivity between arsenic and phosphorus.
;;
;;;
;;
;; ;;; ;;
Sidewall Spacer
Sidewall Spacer
Poly
Arsenic n+
Phosphorus n
Arsenic n+
Phosphorus n
p substrate
040921-02
• Same problems as for the LDD structure
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-5
Lateral DMOS (LDMOS) Using CMOS Technology
The LDMOS structure is designed to provide sufficient lateral dimension and to prevent
oxide breakdown by the higher drain voltages.
Drain
Gate
;;;;;;
n+ S/D
Source/Bulk
p+
body
n+ S/D
;;;;;;;
Gate
n+ S/D
p epi
;;
;;
Oxide
Drain
n+ S/D
p epi
n well
p substrate
p+
p-
p
n-
n+
n
Poly 2
Poly 1
Nitride Salicide
Metal
040921-03
• Structure is symmetrical about the source/bulk contact
• Channel is formed in the p region under the gates
• Drain voltage can be 20-30V
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-6
LATCHUP IN CMOS TECHNOLOGY
What is Latchup?
Latchup is the regenerative process that can occur in a pnpn structure (SCR-silicon
controlled rectifier) formed by a parasitic npn and a parasitic pnp transistor.
Anode
Anode
V
iPNPN
DD
iPNPN
p
n
p
vPNPN
1/Slope =
Limiting To avoid latchup
Resistance vPNPN < VS
Triggering by
increasing V
Hold Current, IH
DD
n
Cathode
Cathode
Avalanche
Breakdown
Hold
Voltage, VH
Body diode
(CMOS)
Sustaining
voltage, VS
vPNPN
050414-01
Important concepts:
• To avoid latchup, vPNPN VS
• Once the pnpn structure has latched up, the large current required by the above i-v
characteristics must be provided externally to sustain latchup
• To remove latchup, the current must be reduced below the holding current
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-7
Latchup Triggering
Latchup of the SCR can be triggered by two different mechanisms.
1.) Allowing vPNPN to exceed the sustaining voltage, VS.
2.) Injection of current by a triggering device (gate triggered)
VDD
Pad
Anode
Gate
Current
pnp
Gate
Injector
npn
Gate
SCR
SCR
050414-03
Injector
Gate
Current
Pad
Cathode
Note: The gates mentioned above are SCR junction gates, not MOSFET gates.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-8
How does Latchup Occur in an IC?
Consider an output driver in CMOS technology:
vIN
vOUT
VDD
VDD
vIN
vOUT
p+
p
p-
n-
n
n+
Oxide Poly 1 Poly 2 Nitride Salicide Metal
050416-02
Assume that the output is connected to a pad.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-9
Parasitic Bipolar Transistors for the n-well CMOS Inverter
vIN
vOUT
VDD
Rw3
LT2
Rs2
Rs1 LT1
Rw4
VT2
Rs3
p+
n-
p-
p
n+
n
Rw2
VT1 Rw1
Rs4
Oxide Poly 1 Poly 2 Nitride Salicide Metal
050416-03
Parasitic components:
Lateral BJTs LT1 and LT2
Vertical BJTs VT1 and VT2
Bulk substrate resistances Rs1, Rs2, Rs3, and Rs4
Bulk well resistances Rw1, Rw2, Rw3, and Rw4
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-10
Current Source Injection
Apply a voltage compliant current source to the output pad (vOUT > VDD).
vIN vOUT
Voltage Compliant
Current Source
VDD
LT2
Rs
p+
Voltage
Compliant
Current
Source
p
LT1
p-
n-
n
n+
Rw
LT1
CMOS Analog Circuit Design
Oxide Poly 1 Poly 2 Nitride Salicide Metal
iin
Rs
LT1
VT1
VT2
Injector
VT1 Rw
VT2
+fb
loop
SCR
VDD
Rw
050416-04
VT1 iout
06022-01
Loop gain:
iout
Rw Rs iin = P1Rw+rP1 N1Rs+rN1
Rw
Rs P1Vt
R +
R +N1Vt
w IP1 s IP2 = P1N1
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-11
Current Sink Injection
Apply a voltage compliant current sink to the output pad (vOUT < 0).
vIN vOUT
Voltage Compliant
Current Sink
VDD
Rw3
LT2
Rs
p+
LT1
n-
p-
p
n
n+
Oxide Poly 1 Poly 2 Nitride Salicide Metal
Rw
Voltage
Compliant
Current
Sink
iin
VT1
LT1
LT2
Injector
VT1 Rw
VT2
+fb
loop
VDD
Rs
LT1
050416-07
VT1 iout
Rw
060222-02
Loop gain:
iout
Rw Rs iin = P1Rw+rP1 N1Rs+rN1
Rw
Rs P1Vt
R +
R +N1Vt
w IP1 s IP2 = P1N1
Receiver
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-12
Latchup from a Transmission Gate
The classical push-pull output stage is only one of the many configurations that can lead
to latchup. Here is another configuration:
Transmission
Gate
Internal
Core
Circuits
Internal Core
Circuitry
Clk
Pad
VDD
Pad
VDD
VDD
Clk
Injectors
Driver
Receiver
Transmission Gate
050416-09
p+
p
p-
n-
n
n+
Clock Driver
Oxide Poly 1 Poly 2 Nitride Salicide Metal
The two bold solid bipolar transistors in the transmission gate act as injectors to the npnpnp parasitic bipolars of the clock driver and cause these transistors to latchup. The
injector sites are the diffusions connected to the pad.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-13
Preventing Latch-Up
1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.
3.) Surround the transistors with guard rings. Guard rings reduce transistor betas and
divert collector current from the base of SCR transistors.
n+
p-channel transistor
guard bars
VDD
FOX
p+
n-channel transistor
guard bars
VSS
FOX
FOX
FOX
FOX
FOX
p-well
FOX
n- substrate
Figure 190-10
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-14
What are Guard Rings?
Guard rings are used to collector carriers flowing in the silicon. They can be designed to
collect either majority or minority carriers.
Guard rings in n-material:
n+ guard ring
Collects
majority
carriers
Guard rings in p-material:
p+ guard ring
Collects
minority
carriers
VDD
p+ guard ring
Collects majority
carriers
p
p-
n-
n
n+
VDD
Decreased bulk
resistance
Decreased bulk
resistance
p+
n+ guard ring
Collects
minority
carriers
p+
p
p-
n-
n
n+
051201-01
051201-02
Also, the increased doping level of the n+ (p+)guard ring in n (p) material decreases the
resistance in the area of the guard ring.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-15
Example of Reducing the Sensitivity to Latchup
Start with an inverter with no attempt to minimize latchup and minimum spacing between
the NMOS and PMOS transistors.
vIN
vOUT
VDD
Rw
Rs
Note minimum separation
p+
n-
p-
p
n
n+
Oxide Poly 1 Poly 2 Nitride Salicide Metal
050427-03
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-16
Example of Reducing the Sensitivity to Latchup by using Guard Rings
Next, place guard rings around the NMOS and PMOS transistors (both I/O and logic) to
collect most of the parasitic NPN and PNP currents locally and prevent turn-on of
adjacent devices.
vIN
p+ guard
ring
vOUT
VDD
n+ guard
ring
VDD
Rw
Rs
Note increased separation
p+
p
p-
n-
n
n+
Oxide Poly 1 Poly 2 Nitride Salicide Metal
050427-04
• The guard rings also help to reduce the effective well and substrate resistance.
• The guard rings reduce the lateral beta
Key: The guard rings should act like collectors
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-17
Example of Reducing the Sensitivity to Latchup by using Butted Contacts
Finally, use butted source contacts to further reduce the well resistance and reduce the
substrate resistance.
vIN
p+ guard
ring
vOUT
VDD
n+ guard
ring
Rw
Rs
p+
p
CMOS Analog Circuit Design
Chapter 2. – Section 7 (12/12/06)
VDD
p-
n-
n
n+
Oxide Poly 1 Poly 2 Nitride Salicide Metal
050427-05
© P.E. Allen - 2006
Page 2.7-18
Guidelines for Guard Rings
• Guard rings should be low resistance paths.
• Guard rings should utilize continuous diffusion areas.
• More than one transistor of the same type can be placed inside the same well inside the
same guard ring as long as the design rules for spacing are followed.
• Only 2 guard rings are required between adjacent PMOS and NMOS transistors
• The well taps and/or the guard ring should be laid out as close to the MOSFET source
as possible.
• I/O output NMOSFET should use butted composite for source to bulk connections
when the source is electrically connected to the p-well tap. If separate well tap and
source connections are required due to substrate noise injection problems, minimize the
source-well tap spacing. This will minimize latch up and early snapback of the output
MOSFETs with the drain diffusion tied directly (in metal) to the bond pad.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-19
ESD IN CMOS TECHNOLOGY
What is Electrostatic Discharge?
Triboelectric charging happens when 2 materials come in contact and then are separated.
An ESD event occurs when the stored charge is discharged.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-20
ESD and Integrated Circuits
• ICs consist of components that are very sensitive to excess current and voltage above
the nominal power supply.
• Any path to the outside world is susceptible to ESD
• ESD damage can occur at any point in the IC assembly and packaging, the packaged
part handling or the system assembly process.
• Note that power is normally not on during an ESD event
050727-01
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-21
ESD Models and Standards
• Standard tests give an indication of the ICs robustness to withstand ESD stress.
• Increased robustness:
- Reduces field failures due to ESD
- Demanded by customers
t=0
• Simple ESD model:
+
i(t)
RLim
VSE
- VSE = Charging Voltage
- Key parameters of the model:
o Maximum current flow
o Time constant or how fast the ESD
discharges
o Risetime of the pulse
−C
Current
event
Imax
Time constant (τ)
≈ RLimC
Risetime
0
0
t
050707-02
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-22
ESD Models
• Human body model (HBM): Representative of an ESD
event between a human and an electronic component.
050423-02
• Machine model (MM): Simulates the ESD event when a
charged “machine” discharges through a component.
040929-03
• Charge device model (CDM): Simulates
the ESD event when the component is
charged and then discharges through a pin.
The substrate of the chip becomes charged
and discharges through a pin.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-23
ESD Influence on Components
An ESD event typically creates very high values of current (1-10A) for very short periods
of time (150 ns) with very rapid rise times (1ns).
Therefore, components experience extremely high values of current with very little power
dissipation or thermal effects.
Resistors – become nonlinear at high currents and will breakdown
Capacitors – become shorts and can breakdown from overvoltage (pad to substrate)
Diodes – current no longer flows uniformly (the connections to the diodes represent the
ohmic resistance limit)
Transistors – ESD event is only a two terminal event, the third terminal is influenced by
parasitics and many parameters out of control
• MOSFETs – the parasitic bipolar experiences snapback under an ESD event
• BJTs – will experience snapback under ESD event
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-24
Objective of ESD Protection
• There must be a safe low impedance path between every combination of pins to sink the
ESD current (i.e. 1.5A for 2kV HBM)
• The ESD device should clamp the voltage below the breakdown voltage of the internal
circuitry
• The metal busses must be designed to survive 1.5A (fast transient) without building up
excessive voltage drop
VDD
• ESD current must be steered away from sensitive
circuits
Limiting
Resistor
Sensitive
Circuits
• ESD protection will require area on the chip (busses
and timing components)
CMOS Analog Circuit Design
VSS
ESD
Power
Rail
Clamp
041008-01
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-25
ESD Protection Architecture
Rail based protection
VDD
Local
Clamp
Local
Clamp
Internal
Circuits
Input
Pad
ESD
Power
Rail
Clamp
Output
Pad
Local
Clamp
Local
Clamp
040929-06
VSS
Local clamp based protection
Local clamps – Designed to pass ESD current without loading the internal (core) circuits
ESD power rail clamps – Designed to pass large amount of current with a small voltage
drop
ESD Events:
Pad-to-rail (uses local clamps only)
Pad-to-pad (uses either local or local and ESD power rail clamps)
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-26
ESD Breakdown Clamp Example
A normal MOSFET that uses the parasitic lateral BJT to achieve a snapback clamp.
Normally, the MOSFET has the gate shorted to the source so that drain current is zero.
S
G
D
- +
vDS
n+
Shallow
Trench
Isolation
p-substrate
041217-04
iC
Rsub
B
B
Device destruction
iDS
Negative TC
p+
n+
iSub
iDS
Shallow
Trench
Isolation
Positive TC
Second Breakdown
Snapback Region
First Breakdown
Avalanche
Region
Linear Region
Saturation Region
Vt2
vDS
Vt1
Issues:
• If the drain voltage becomes too large, the gate oxide may breakdown
• If the transistor has multiple fingers, the layout should ensure that the current is
distributed evenly.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-27
Non-Breakdown Clamp Example
Merrill Clamp:
VDD
Speed-up
Capacitor
R
Trigger
Circuit
Inverter
Driver
C
VSS
NMOS
Clamp
041001-03
Operation:
• Normally, the input to the driver is high, the output low and the NMOS clamp off
• For a positive ESD event, the voltage increases across R causing the inverter to turn on
the NMOS clamp providing a low impedance path between the rails
• Cannot be used for pads that go above power supply or are active when powered up
• For power supply turn-on, the circuit should not trigger (C holds the clamp off during
turn-on)
Also, forward biased diodes serve as non-breakdown clamps.
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-28
Current
Current
IV Characteristics of Good ESD Protection
Goal: Sink the ESD current and clamp the voltage.
ITarget
ITarget
ESD Clamp
Protected
Device
Protected
Device
Voltage
Case 2 - Protected Device Fails
Voltage
Current
Current
Case 1 - Okay
ITarget
ESD Clamp
ESD Clamp
Protected
Device
Voltage
Case 3 - Okay
ITarget
ESD Clamp
Protected
Device
Voltage
Case 4 - Protected Device Fails
050507-04
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 7 (12/12/06)
Page 2.7-29
Target
Iesd
Current
Increasing
Merrill NMOS
W
NMOS Vt
Max operating voltage
Comparison Between the Merrill Clamp and the Snapback Clamp
Increasing the Merrill clamp MOS width will reduce the clamp voltage.
Increasing
snapback W
Vc3
Holding
voltage
Vc2
Vc1
Voltage
Trigger
voltage
Note that the Merrill clamp does not normally exceed the absolute maximum voltage.
Merrill clamps should be used with EPROMs to avoid reprogramming during an ESD
event
CMOS Analog Circuit Design
Chapter 2. – Section 7 (12/12/06)
© P.E. Allen - 2006
Page 2.7-30
ESD Practice
General Guidelines:
• Understand the current flow requirements for an ESD event
• Make sure the current flows where desired and is uniformly distributed
• Series resistance is used to limit the current in the protected devices
• Minimize the resistance in protecting devices
• Use distributed (smaller) active clamps to minimize the effect of bus resistance
• Understand the influence of packaging on ESD
• Use guard rings to prevent latchup
Check list:
• Check the ESD path between every pair of pads
• Check for ESD protection between the pad and internal circuitry
• Check for low bus resistance
- Current: Minimum metal for ESD 40 x Electromigration limit
- Voltage: 1.5A in a metal bus of 0.03/square of 1000μm long and 30μm wide
gives a voltage drop of 1.5V
• Check for sufficient contacts and vias in the ESD path (uniform current distribution)
CMOS Analog Circuit Design
© P.E. Allen - 2006
Chapter 2. – Section 8 (12/12/06)
Page 2.8-1
SECTION 2.8 – SUMMARY
Review
• Importance of technology on circuit design – technology establishes the boundaries and
constraints for the circuit design
• Basic IC processes – defines the physical aspects of components and the nonideal
behavior
• pn junctions – fundamental component of integrated circuits
• Transistors – physical aspects that define performance and parasitics
• Passive components – resistors, capacitors and inductors define gains and time
constants of circuit performance
• Parasitic components used as components (BJT)
• Latchup and ESD considerations
Key Focus
The design of analog integrated circuits is a co-design process between electrical and
physical. Better understanding of the technology will allow the circuit objectives of a
design to be better achieved.
CMOS Analog Circuit Design
© P.E. Allen - 2006