OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer
Check for Samples: LMV115
FEATURES
DESCRIPTION
•
The LMV115 is a 30MHz buffer specially designed to
minimize the effects of spurious signals from the base
band chip to the oscillator. The buffer also minimizes
the influence of varying load resistance and
capacitance to the oscillator and increases the drive
capability.
1
2
•
•
•
•
•
•
(Typical 2.8V Supply; Values Unless Otherwise
Specified)
Low Supply Current: 0.3mA
2.5V to 3.3V Supply
AC Coupling Possible Without External Bias
Resistors.
Includes Shutdown Function External
Oscillator
SC70-6 Pin Package 2.1 x 2mm
Operating Temperature Range −40°C to 85°C
The input of the LMV115 is internally biased with two
equal resistors to the power supply rails. This allows
AC coupling on the input.
The LMV115 offers a shutdown function to optimize
current consumption. This shutdown function can also
be used to control the supply voltage of an external
oscillator. The device is in shutdown mode when the
shutdown pin is connected to VDD.
APPLICATIONS
•
•
•
Cellular Phones
GSM Modules
Oscillator Modules
The LMV115 comes in SC70-6 package. This space
saving product reduces components, improves clock
signal and allows ease of placement for the best form
factor.
Schematic Diagram
OUT
OSCILLATOR
CCOUPLING
VDD
GND
1 IN
3
OUT
CL
2
6
RL
VDD
GND
GND
5
SHUTDOWN
4
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1) (2)
ESD Tolerance
2000V (3)
Human Body Model
150V (4)
Machine Model
−
+
Supply Voltage (V – V )
3.6V
Output Short Circuit to V+
See (5) (6)
Output Short Circuit to V−
See (5) (6)
−65°C to +150°C
Storage Temperature Range
Junction Temperature (7)
+150°C
Mounting Temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Infrared or Convection (20 sec.)
235°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human Body Model (HBM) is 1.5kΩ in series with 100pF.
Machine Model, 0Ω in series with 200pF.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C
Infinite Duration; Short circuit test is a momentary test. See Note 7.
The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) -TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
OPERATING RATINGS (1)
Supply Voltage (V+ – V−)
Temperature Range
2.5V to 3.3V
(2) (3)
−40°C to +85°C
Package Thermal Resistance (2) (3)
(1)
(2)
(3)
SC70-6
414°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) -TA) / θJA. All numbers apply for packages soldered directly onto a PC board.
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA . There is no ensured parametric performance as indicated in the electrical tables
under conditions of internal self-heating where TJ > TA. See APPLICATION SECTION for information on temperature de-rating of this
device.
2.8V ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.8V, V− = 0V, VCM = V+/2, shutdown = 0.0V, and RL = 50kΩ
to V+/2, CL = 5pF to V+/2 and CCOUPLING = 1nF.Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
SSBW
Small Signal Bandwidth
VOUT < 0.5VPP; −3dB
31
MHz
GFN
Gain Flatness < 0.1dB
f > 50kHz
2.8
MHz
FPBW
Full Power Bandwidth (−3dB)
VOUT = 1.0VPP (+4.5dBm)
9
MHz
0.1VSTEP (10-90%)
11
Time Domain Response
tr
Rise Time
tf
Fall Time
ts
Settling Time to 0.1%
0.1VSTEP
95
OS
Overshoot
0.1VSTEP
24
%
SR
Slew Rate
See (3)
18
V/μs
(1)
(2)
(3)
2
11
ns
ns
All limits are specified by testing or statistical analysis.
Typical Values represent the most likely parametric norm.
Slew rate is the average of the positive and negative slew rate.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
2.8V ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.8V, V− = 0V, VCM = V+/2, shutdown = 0.0V, and RL = 50kΩ
to V+/2, CL = 5pF to V+/2 and CCOUPLING = 1nF.Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
Distortion and Noise Performance
HD2
2nd Harmonic Distortion
VOUT = 500mVPP; f = 100kHz
−41
dBc
HD3
3rd Harmonic Distortion
VOUT = 500mVPP; f = 100kHz
−43
dBc
THD
Total Harmonic Distortion
VOUT = 500mVPP; f = 100kHz
−38
dBc
en
Input-Referred Voltage Noise
f = 1MHz
27
nV/√Hz
Isolation
Output to Input
See also TYPICAL PERFORMANCE
CHARACTERISTICS
>40
dB
Static DC Performance
ACL
Small Signal Voltage Gain
VOUT = 100mVPP
0.90
0.85
VOS
Output Offset Voltage
TC VOS
Temperature Coefficient Output
Offset Voltage
See (4)
102
ROUT
Output Resistance
f = 10kHz
61
f = 25MHz
330
PSRR
Power Supply Rejection Ratio
V+ = 2.8V to V+ = 3.3V
IS
Supply Current
No Load; Shutdown = 2.8V
41
38
No Load; Shutdown = 0V
0.998
1.10
1.11
V/V
3.5
35
55
mV
μV/°C
Ω
42
dB
0.0
2.00
314
450
520
μA
Miscellaneous Performance
RIN
CIN
ZIN
VO
IO
ISC
Input Resistance
Input Capacitance
Input Impedance
Shutdown = 2.8V
65
Shutdown = 0V
64
Shutdown = 2.8V
1.82
Shutdown = 0V
1.50
f = 25MHz; Shutdown = 2.8V
2.38
f = 25MHz; Shutdown = 0V
2.47
Output Swing Positive (5)
RL = 50kΩ to V+/2
Output Swing Negative
RL = 50kΩ to V+/2
Linear Output Current
No Load; VOUT = V+ − 1.1V (Sourcing)
−90
−35
−206
−
No Load; VOUT = V + 1.1V (Sinking)
100
50
205
No Load; Sourcing to V+/2
−90
−35
−186
100
50
191
Output Short-Circuit Current (6)
1.90
1.65
No Load; Sinking from V /2
RON
(4)
(5)
(6)
Switch in ON Position
pF
kΩ
2.16
1.05
+
kΩ
1.35
1.30
V
μA
μA
21
40
45
Ω
Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature
change.
Positive current corresponds to current flowing into the device.
Infinite Duration; Short circuit test is a momentary test. See Note 7 under Absolute Maximum Ratings.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
3
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
CONNECTION DIAGRAM
6
1
VDD
IN
2
GND
3
OUT
TOP VIEW
5
SHUTDOWN
4
SUPPLY FOR
EXTERNAL
OSCILLATOR
Figure 1. SC70-6 - Top View
4
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, V = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified.
+
Frequency Response Over Temperature
60
6
3
30
3
0
0
0
-30
-3
GAIN
-60
-6
-90
-9
PHASE
-120
-12
VS = 2.8V
-15
-150
PIN = -15dBm
-18
RL = 50k:
CL = 5pF
-24
100k
1M
10M
-40°C
-3
-6
-9
85°C
-12
VS = 2.8V
-15
PIN = -15dBm
-18
RL = 50k:
-210
-21
CL = 5pF
-240
-24
100k
-180
-21
GAIN NORMALIZED (dB)
25°C
PHASE (°)
GAIN NORMALIZED (dB)
Frequency and Phase Response
6
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 2.
Figure 3.
Phase Response Over Temperature
Gain Flatness 0.1dB
1
60
0
PHASE (°)
-30
-60
-90
-40°C
85°C
-120
-150
-180
-210
VS = 2.8V
25°C
PIN = -15dBm
GAIN NORMALIZED (dB)
30
0.5
+0.1dB
0
PIN = -15dBm
RL = 50k:
RL = 50k:
CL = 5pF
CL = 5pF
-1
-240
100k
1M
10M
100k
100M
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
Figure 4.
Figure 5.
Full Power Bandwidth
Transient Response Positive
1480
6
3
1460
0
1440
-3
VOUT (mV)
GAIN NORMALIZED (dB)
VS = 2.8V
-0.1dB
-0.5
-6
-9
-12
-15
-18
-21
1420
1400
1380
VS = 2.8V
PIN = +4dBm
1360
RL = 50k:
1340
STEP = 100mVPP
CCOUPLING = 0
CL = 5pF
1320
-24
100k
1M
10M
100M
FREQUENCY (Hz)
0
20 40 60 80 100 120 140 160 180 200
TIME (ns)
Figure 6.
Figure 7.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
5
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
−
+
TJ = 25°C, V = 2.8V, V = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified.
Transient Response Negative
Harmonic Distortion vs. VOUT @ 100kHz
0
1480
STEP = 100mVPP
1460
RL = 50k:
-20
DISTORTION (dBc)
1440
VOUT (mV)
VS = 2.8V
-10
CCOUPLING = 0
1420
1400
1380
1360
-30
-40
-50
3
-60
2
-70
4
1340
THD
CL = 5pF
f = 100kHz
th
0
-90
200 300 400 500 600 700 800 900 1000
20 40 60 80 100 120 140 160 180 200
VOUT (mVPP)
Figure 8.
Figure 9.
Harmonic Distortion vs. VOUT @ 500kHz
Harmonic Distortion vs. VOUT @ 1MHz
0
0
VS = 2.8V
-10
RL = 50k:
THD
-20
CL = 5pF
f = 500kHz
DISTORTION (dBc)
DISTORTION (dBc)
-30
-40
-50
3
-60
-70
2
4
th
nd
rd
HD
HD
VS = 2.8V
RL = 50k:
-30
-40
-50
3
-60
2
-70
HD
THD
CL = 5pF
f = 1MHz
4
th
HD
HD
HD
-80
-90
200 300 400 500 600 700 800 900 1000
-90
200 300 400 500 600 700 800 900 1000
VOUT (mVPP)
VOUT (mVPP)
Figure 10.
Figure 11.
Voltage Noise
0
300
VS = 2.8V
-10
250
500kHz
-20
5MHz
-30
-40
1MHz
-50
100kHz
VS = 2.8V
-60
RL = 50k:
-70
VOLTAGE NOISE (nV/ Hz)
TOTAL HARMONIC DISTORTION (dBc)
nd
rd
-80
THD vs. VOUT for Various Frequencies
200
150
100
50
CL = 5pF
-80
200 300 400 500 600 700 800 900 1000
VOUT (mVPP)
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 12.
6
HD
HD
TIME (ns)
-20
HD
-80
1320
-10
nd
rd
Figure 13.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
−
+
TJ = 25°C, V = 2.8V, V = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified.
ROUT vs. Frequency
Input Impedance vs. Frequency
350
70
60
250
50
IMPEDANCE (k:)
ROUT (:)
VS = 2.8V
300
200
150
100
50
-
SD = V
40
+
SD = V
30
20
10
VS = 2.8V
0
100
1
1k
100k
10k
10M 30M
1M
1k
100k
10k
FREQUENCY (Hz)
1M
10M
50M
FREQUENCY (Hz)
Figure 14.
Figure 15.
Isolation Output to Input
VOUT vs. IOUT (Sinking)
90
2.8
2.4
-40°C
-40°C
70
2.0
25°C
VOUT (V)
ISOLATION NORMALIZED (dB)
VIN = -15dBm
80
60
25°C
85°C
50
1.6
85°C
1.2
40
0.8
30
0.4
20
0.0
VIN = 1.1V
1k
10k
100k
1M
10M
50M
0
50
100
FREQUENCY (Hz)
150
200
250
IOUT (PA)
Figure 16.
Figure 17.
VOUT vs. IOUT (Sourcing)
ISC Sourcing vs. VSUPPLY
2.8
0
VIN = 1.7V
85°C
25°C
2.4
-50
25°C
IOUT (PA)
VOUT (V)
2.0
1.6
85°C
1.2
-100
-150
-40°C
0.8
-40°C
-200
0.4
VOUT = VS/2, VIN - VOUT = +0.5V
0.0
-250
-250
-200
-150
-100
-50
0
IOUT (mA)
2
2.5
3
3.5
4
4.5
5
VSUPPLY (V)
Figure 18.
Figure 19.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
7
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
−
+
TJ = 25°C, V = 2.8V, V = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified.
ISC Sinking vs. VSUPPLY
VOS vs. VSUPPLY for 3 Units
40
250
85°C
TJ = 25°C
UNIT 2
225
20
200
0
150
UNIT 3
VOS (mV)
IOUT (PA)
175
25°C
125
-40°C
100
-20
UNIT 1
-40
75
-60
50
VOUT = VS/2
25
-80
VIN - VOUT = -0.5V
-100
0
2
2.5
3
3.5
4
5
4.5
2
2.5
3
4
3.5
4.5
5
VSUPPLY (V)
VSUPPLY (V)
Figure 20.
Figure 21.
VOS vs. VSUPPLY for Unit 1
VOS vs. VSUPPLY for Unit 2
40
40
20
20
0
0
-20
VOS (mV)
VOS (mV)
-40°C
25°C
85°C
-40
-20
85°C
-40
-60
-60
-80
-80
-100
-40°C
25°C
-100
2
2.5
3
4
3.5
4.5
5
2
2.5
3
VSUPPLY (V)
4
3.5
4.5
5
4.5
5
VSUPPLY (V)
Figure 22.
Figure 23.
VOS vs. VSUPPLY for Unit 3
ISUPPLY vs. VSUPPLY
40
400
20
350
85°C
300
-20
ISUPPLY (PA)
VOS (mV)
0
-40°C
25°C
85°C
-40
-60
250
25°C
-40°C
200
150
100
-80
50
-100
0
RL = NO LOAD
2
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
VSUPPLY (V)
VSUPPLY (V)
Figure 24.
8
2
Figure 25.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
−
+
TJ = 25°C, V = 2.8V, V = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified.
PSRR vs. Frequency
Small Signal Pulse Response
50
1500
45
1480
1460
40
VOUT (mV)
PSRR (dB)
1440
35
30
25
1420
1400
1380
1360
20
15
VS = 2.8V
RL = 50k:
RBIAS = NONE
10
1340
VIN = 100MVPP
f = 1MHz
1320
CCOUPLING = 0
1300
100
1k
10k
100k
0
1M
200
FREQUENCY (Hz)
400
600
800
1000 1200
TIME (ns)
Figure 26.
Figure 27.
Large Signal Pulse Response
2.5
2.3
2.1
VOUT (V)
1.9
1.7
1.5
1.3
1.1
VIN = 1VPP
f = 100kHz
0.9
CCOUPLING = 0
0.7
VOFFSET = +100mV
0.5
0
1
2
3
4
5
6
7
8
9
10
TIME (Ps)
Figure 28.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
9
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
APPLICATION SECTION
GENERAL
The LMV115 is specially designed to minimize the effects of spurious signals from the base band chip to the
oscillator. Beside this the influence of varying load resistance and capacitance to the oscillator is minimized,
while increasing the drive capability. The input of the LMV115 is internally biased with two equal resistors to the
power supply rails, and makes AC coupling possible without external bias resistors at the input. The LMV115 has
excellent gain phase margin. The LMV115 offers a shutdown pin that can be used to disable the device in order
to optimize current consumption and also has a feature to control the supply voltage to an external oscillator.
When the shutdown pin is connected to VDD the device is in shutdown mode.
SWITCHED POWER SUPPLY CONNECTION
The LMV115 features an enable/disable function for an external oscillator by controlling its supply voltage (pin 4).
See also the Schematic Diagram on the front page. During normal operating mode, pin 4 is connected to the
positive supply rail via an internal switch. The resistance between the positive supply rail and pin 4, RON, is
specified in the electrical characterization table. Oscillators with a supply current up to several milliamps can
easily be powered from pin 4. During shutdown, pin 4 is switched to the negative supply rail. The simplified
schematic for this part of the device is shown in Figure 29
PIN 6 VDD
PIN 4
SUPPLY FOR
EXTERNAL
OSCILLATOR
PIN 5
SHUTDOWN
PIN 2 GND
Figure 29. Supply For External Oscillator
INPUT CONFIGURATION
The input of the LMV115 is internally biased at mid-supply by a divider of two equal resistors. With the LMV115
in shutdown mode, the internal resistor connected to the VDD is shortened to the negative power supply rail via a
switch. This makes the power consumption in ‘off’ mode almost zero, but causes a small difference for the input
impedance between the on and off modes. Both resistors are 110kΩ so the resulting input impedance will be
approximately 55kΩ. The input configuration allows AC coupling on the input of the LMV115. A simplified
schematic of the input is shown in Figure 30.
10
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
VDD
R1
VEE
RBIAS
EXTERNAL
R2
VEE
Figure 30. Dual Supply Mode
PSRR
If an AC signal is applied to one of the supply lines, while the input is floating, the signal at the input pin is half
the signal at the supply line, causing the same signal at the output of the buffer. This will result in a PSRR of only
6dB (see Figure 30).
In a typical application the input is driven from a low ohmic source that means the disturbance at the supply lines
is attenuated by the series resistors of 110k and the source impedance. In case the buffer is connected to a 50Ω
source, the resulting suppression will be 20*log [(R1 + RBIAS)/RBIAS] = 67dB for signals at the supply line. The
PSRR can also be measured correctly for this type of input by shorten the input to mid-supply. Due to the
internal structure it is not recommended to measure with the input connected to ground. To measure correctly the
PSRR, two signals are applied to both VDD and VEE but with 180° phase difference (see Figure 30). In this case,
both signals are subtracted and there will be no signal at the input. The resulting disturbance at the output is now
only caused by the signals at the supply lines.
INPUT AND OUTPUT LEVEL
Due to the internal loop gain of 1, the output will follow the input. The output voltage cannot swing as close to the
supply rail as the input voltage. For linear operation the input voltage swing should not exceed the output voltage
swing. The restrictions for the output voltage can be examined by the two curves in Figure 31. The curve VOUT
(V) shows the response of the output signal versus the input signal and the curve VOUT – VIN (V) shows the
difference between the output and the input signal.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
11
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
2.8
0.08
2.45
0.06
2.1
0.04
1.75
0.02
VOUT
1.4
0
1.05
-0.02
VOUT - VIN
0.7
VOUT - VIN (V)
VOUT (V)
+50mV
-0.04
0.35
-0.06
-50mV
0
-0.08
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
VIN (V)
Figure 31. VOUT – VIN
In Figure 31 the input signal is swept between both supply rails (0V - 2.8V). The linear part of the plot ‘VOUT vs.
VIN’ covers approximately the voltage range between 1.0V and 2.0V. If a difference of 50mV between output and
input is acceptable, the output range is between 1.05V and 2.15V (see curve VOUT - VIN). Alternatively the
output voltage swing can be determined by using Figure 32. In the plot ‘Gain vs. VIN’ it can be seen that the gain
is flat for input voltages from 1.15V till 2.1V. Outside this range the gain differs from 1. This will introduce
distortion of the output signal.
2.8
2
1.8
2.45
1.6
VOUT
2.1
1.2
1.4
1
0.8
1.05
0.6
GAIN
0.7
GAIN (V/V)
VOUT (V)
1.4
1.75
0.4
0.35
0.2
0
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
VIN (V)
Figure 32. Gain
Another point is the DC bias voltage necessary to get the optimum output voltage swing. As discussed above,
the output voltage swing can be 1VPP, but if the two internal bias resistors are used, the DC bias will be 1.4V,
which is half of the supply voltage of 2.8V. In this situation the output swing will exceed the lower limit of 1.15V,
so it is necessary to introduce a small DC offset of 200mV to make use of the full output swing range of the
output stage.
12
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
DRIVING RESISTIVE AND CAPACITIVE LOADS
The maximum output current of the LMV115 is about 200μA which means the output can drive a maximum load
of 1V/200μA = 5kΩ. Using lower load resistances will exceed the maximum linear output current. The LMV115
can drive a small capacitive load, but make sure that every capacitor directly connected to the output becomes
part of the loop of the buffer and will reduce the gain/phase margin, increasing the instability at higher capacitive
values. This will lead to peaking in the frequency response and in extreme situations oscillations can occur. A
good practice when driving larger capacitive loads is to include a series resistor to the load capacitor. A to D
converters present complex and varying capacitive loads to the buffer. The best value for this isolation resistance
is often found by experimentation.
SHUTDOWN MODE
LMV115 offers a shutdown function that can be used to disable the device and to optimize current consumption.
Switching between the normal mode and the shutdown mode requires connecting the shutdown pin either to the
negative or the positive supply rail. If directly connected to one of the supply rails, the part is specified in the
correct mode. But if the shutdown pin is driven by other output stages, there is a voltage range in which the
installed mode is not certainly set and it is recommended not to drive the shutdown pin in this voltage range. As
can be seen in Figure 33 this hysteresis varies from 1V to 1.6V. Below 1V the LMV115 is securely ‘ON’ and
above 1.6V securely ‘OFF’ while using a supply voltage of 2.8V.
VDD SWITCHED @ PIN 4 (V)
2
1.5
1
SWITCHING
POINT LOW
TO HIGH
0.5
0
-0.5
-1
SWITCHING
POINT HIGH
TO LOW
-1.5
-2
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
SHUTDOWN VOLTAGE @ PIN 5 (V)
Figure 33. Hysteresis
PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT VALUES SELECTION
For a good high frequency design both the active parts and the passive ones should be suitable for the purpose
they are used for. Amplifying high frequencies is possible with standard through-hole components, but for
frequencies above several hundreds of MHz the best choice is using surface mount devices. Nowadays designs
are often assembled with surface mount devices for the aspect of minimizing space, but this also greatly
improves the performance of designs, handling high frequencies. Another important issue is the PCB, which is no
longer a simple carrier for all the parts and a medium to interconnect them. The board becomes a real part itself,
adding its own high frequency properties to the overall performance of the circuit. It is good practice to have at
least one ground plane on a PCB giving a low impedance path for all decoupling and other ground connections.
In order to achieve high immunity for unwanted signals from outside, it is important to place the components as
flat as possible on the PCB. Be aware that a long lead can act as an inductor, a capacitor or an antenna. A pair
of leads can even form a transformer. Careful design of the PCB avoids oscillations or other unwanted behavior.
Another important issue is the value of components, which also determines the sensitivity to pick-up unwanted
signals. Choose the value of resistors as low as possible, but avoid using values that causes a significant
increase in power consumption, while loading inputs or outputs to heavily.
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
13
OBSOLETE
LMV115
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
www.ti.com
TI suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing
and characterization.
Device
Package
Evaluation Board PN
LMV115
SC70-6
LMV115/117 Eval Board
This free evaluation board is shipped when a device sample request is placed with TI.
14
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
OBSOLETE
LMV115
www.ti.com
SNOSA81B – DECEMBER 2003 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LMV115
15
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated