Buck Converter Losses
Under the Microscope
By Alan Elbanhawy, Director, Computing and Telecommunications Segments, Advanced Power Systems Center, Fairchild
Semiconductor, San Jose, Calif.
In synchronous stepdown converters, the
parasitic inductances associated with pc-board
traces and device packaging affect power losses,
while limiting MOSFET switching speeds.
he synchronous buck converter in
Fig. 1 is the most popular topology in
the PC market. The race between the
top MOSFET companies is heating up
with the rush to design new devices
that are faster and better suited to meet the demands of
the microprocessor makers. These customers require higher
switching frequencies for their core dc-dc converters to
achieve wider control-loop bandwidth and lower converteroutput impedance at lower cost. It is also well known that
faster switching frequencies introduce higher losses unless
MOSFET parameters, such as gate-drain charge (Qgd and
Qsw) and drain-source on-resistance RDS(ON), are optimized
for such applications.
Nevertheless, gate charge and on-resistance are not the
only parameters that create dc-dc converter losses. The in-
ductances associated with device packaging and pc-board
traces also contribute to converter losses in the synchronous buck converter. To understand these loss mechanisms
requires simulation as well as testing of actual prototypes.
Both of these parasitic parameters play a pivotal role in
determining the power loss in the converter and ultimately
how fast we can switch MOSFETs. Armed with an understanding of how stray inductances contribute to converter
losses, we can devise ways to overcome their effects.
T
R1
3
+
Q1
1
0
2
1
L1
2
1 uH
R2
-
-
Fig. 2 shows the switching waveforms of an actual voltage regulator module (VRM). Ch1 is the gate-ground voltage of the high-side (HS) MOSFET Q1 in Fig. 1; Ch2 is the
source-ground voltage of the HS MOSFET Q1 in the same
figure. The trace M1 in Fig. 2 is the calculated Ch1-Ch2
representing the gate-source voltage of the HS MOSFET,
and Ch3 and Ch4 are the drain currents of Q2 and Q1.
In this particular test, we had to use a current loop in
both the sources of Q1 and Q2 of Fig. 1 (partially represented by L2 and L3) to enable current measurements. This
clearly alters the circuit performance by introducing large
inductances in the circuit. Although this is not the real circuit, it helps us understand the loss mechanism during turn
off of these MOSFETs. Later on, we will introduce a
“noninvasive” way to measure the current without disturbing the circuit too much.
In Fig. 2, the trace M1 clearly shows a plateau of about
2.5 V after the gate voltage has turned off, as can be seen in
Ch1. During this plateau, which lasts for about 100 ns, the
drain currents of both the HS and the low-side (LS)
MOSFETs change states. The HS MOSFET turns off and
the drain current (Ch4) returns to zero, while the LS
MOSFET turns on and the drain current (Ch3) reaches
the inductor current. This is where the circuit performs
in a way contrary to the current understanding of how
L2
-
+
V3
12 Vdc
2
V1
V2
+
The High-side MOSFET
2
Q2
C1
R3
0.06
100 u
L3
0
0
Fig. 1. Simplified schematic of a buck converter.
Power Electronics Technology
February 2005
24
www.powerelectronics.com
BUCK CONVERTER LOSSES
loops, the current will take shorter
time to reach its final level. We will
show that in simulation results where
we can probe without disturbing the
circuit. Notice that the source-ground
voltage goes negative.
The rate of change of the drain
current
¶Idrain
¶t
(where I drain is the drain current
and t is time) will generate a backward
voltage =
L·
pulling the source voltage in a
negative direction with respect to the
gate. This action, in turn, makes the
gate voltage positive with respect to
the source, hence allowing current to
continue to flow though the gate voltage is firmly held to ground. Since the
current transition is by large a linear
transition then
Fig. 2. Switching waveforms from VRM.
L·
Fig. 3. Switching waveforms from VRM.
the synchronous buck converter
performs.
On closer examination, this phenomenon can be clearly explained.
When the HS MOSFET gate-ground
voltage falls from V CC + V GDrive to
ground, the drain current will start
falling from its current level toward
the off state of 0 A. (VCC is the input
voltage and VGDrive is the gate-drive
Power Electronics Technology
February 2005
¶Idrain
¶t
voltage). Notice that Ch2 (sourceto-ground voltage) falls to ground
within 15 ns to 20 ns, giving the false
impression that the switching transition is completed within this time. In
reality, the drain currents take about
100 ns to complete the transitions.
Also remember that the 100 ns is
large because of the source loops. In
actual circuits where there are no
26
¶Idrain
= Constant.
¶t
In other words, this plateau has a
fixed level with time until the current
completes its transition. This negative
source voltage plateau will now allow
the drain current to continue to flow
until the current reaches zero.
We are used to a MOSFET being
fully ON when the current is flowing,
but closer examination of Fig. 3 reveals that the drain current is flowing
in the HS MOSFET while the voltage
across it is VCC. Why is that? It is crucial that we examine the MOSFET
performance at this plateau to further
understand what is happening.
The MOSFET is in a balancing
situation where the voltage
L·
¶Idrain
¶t
causes the source to go negative
enough for the MOSFET to barely
supply the current for the transition,
which is clear from the fact that
L·
¶Idrain
@ 2.5V
¶t
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BUCK CONVERTER LOSSES
Fig. 4. Gate-voltage plateau time is proportional to load current.
a mere 1 V above the gate-source
threshold voltage. The channel is
not fully enhanced; therefore, the
MOSFET operates as a current source
where the current level is maintained
by the negative feedback of the voltage plateau. Having the MOSFET op-
erating as a regulated current source,
albeit during the current transition
only, means the voltage across the
drain source will sustain the full VCC
voltage across it causing higher losses.
To further complicate matters, the
fall time of the drain current is de-
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pendant on its magnitude (i.e., the
larger the current, the larger the fall
time, which leads to the conclusion
that the losses are not linear with current as it has been assumed so far).
Fig. 4 shows this dependency clearly.
In Fig. 4 (a), the trace M1 is the gate-
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Power Electronics Technology
February 2005
BUCK CONVERTER LOSSES
When
L·
the plateau will reach zero voltage
and the MOSFET turns off completely. Simulation results in Fig. 5
using the schematic in Fig. 6 confirm
the lab test findings. In Fig. 5, the
simulation scans the value of the
source inductance between 0.1 nH
and 5.1 nH for the same load current.
Clearly, the current fall time is dependant on the parasitic source inductance further aggravating the total
losses
Fig. 5. Simulation results that confirms the test results.
R2
1
1
0
10
20
Parasitic Inductance Effect
on MOSFET Turn-on
V3
12 Vdc
Now that we have explained a new
switching loss mechanism in the HS
MOSFET during turn off, let’s investigate what is the loss during the turnon transition. The situation here is
completely different because L2 in
Fig. 1 does not carry any current at
the start of the turn-on cycle. This
means that the voltage
-
U1
0
FDS6694
V5
-
V-
V+
+
+
V+
50
30
-
25 Vdc
2
3
2
+
L5
2 nH
5
V1=0
V2=10
TD= 1 ns
TR= 5 ns
TF= 5 ns
PW= 425 ns
PER=3 us
0
V-
2
L2
45 nH
1
L·
1
2
L1
2
10 uH
L3
2 nH
R3
C1
100 uF
3
1
0
V+
R1
.06
0
10
20
U2
1
50
30
FDS6688
3
2
V2
V1=0
+
V2=12
TD= 480 ns
TR= 5 ns
TF= 5 ns
PW= 2.46 us
PER=3 us
25 Vdc
V4
+
VL4
45 nH
0
1
0
Fig. 6. Schematic for Fig. 7.
source voltage of the HS MOSFET at
no-load and in Fig. 4 (b), the trace M1
shows gate-source voltage of the HS
MOSFET at 12.5-A load current. This
Power Electronics Technology
February 2005
¶Idrain
= 0,
¶t
leads to the equality
TurnOffLosses = Idrain × VCC × fs ×
K × Idrain = K × Idrain2 × VCC × fs.
(1)
28
¶Idrain
¶t
now is positive and will tend to
make the source move in the positive
direction opposing the gate drive’s attempt to force the gate-source voltage
to be equal to the gate-drive voltage.
This is not a difficult situation to correct, because we can raise the gatedrive voltage to the level sufficient to
execute clean and fast switching
within the MOSFET VGSS limits. In this
case, the current will follow the gate
drive.
The losses during turn on are
much smaller than those during turn
off. This is because during turn on,
the total inductance in the loop will
carry a substantial amount of the total input voltage VCC. This loop comprises V CC trace inductance, HS
MOSFET with its lead inductance, the
pc-board trace inductance between
the HS and the LS MOSFET, the LS
MOSFET with its lead inductance and
the pc-board inductance between the
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BUCK CONVERTER LOSSES
Fig. 7. LS MOSFET turn-off and turn-on waveforms.
source of the LS MOSFET and the return of VCC.
Fig. 3 illustrates that point. Ch1 is
the source-ground voltage, Ch2 is VCC,
Ch3 and Ch4 are the drain currents
of MOSFETs Q1 and Q2, respectively.
The trace M1 representing the drainto-source voltage drop across the
HS MOSFET will hover around an
intermediate value between 0 V and
V cc while the current is switching
on from zero to the output inductor
current.
This intermediate voltage across
the inductances may be calculated
from the equation
n
Ln·
1
¶Idrain
¶t
where
n
Ln
1
is the sum of all the inductances in
that loop.
Note that individual voltages
within the above summing equation
may be positive or negative, depending on the position in the circuit. This
means the voltage drop across the
MOSFET during turn on may be calculated from the equation:
n
VCC -
Ln·
1
¶Idrain
¶t
and the losses may be calculated
from the equation
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1
· Vcc2 Ł
n
Ln·
1
¶Idrain
· Idrain· tr· fs
¶t ł
(2)
where tr is the current rise time.
This equation represents a much
lower loss because of several factors.
One is that the rise time tr is a much
smaller value since the opposing
effect of
L·
¶Idrain
= Constant
¶t
may be overcome by raising the
gate voltage to accommodate this turn
on voltage plateau. Another difference
between turn-on and turn-off performance is that in the turn-on transition, the HS MOSFET is actively being driven by the gate driver; and
hence, we have fast transition controlled to a large degree by the gate
driver and to a lesser degree by the
source parasitic inductance. Conversely, in the turn-off transition the
HS MOSFET is passively driven on by
the
L·
¶Idrain
¶t
back-EMF effect and “regulated” to
operate as a current source. In addition, the voltage drop from drain to
source of the HS MOSFET is a small
fraction of Vcc as can be calculated
from Equation 2.
The Low-side MOSFET
The loss mechanism for the LS
29
MOSFET agrees so far with the current understanding of their behavior.
As HS MOSFET turns off, the inductor current starts commutating into
the body diode of the LS MOSFET
and the drain-source voltage of the LS
MOSFET switches from VCC to one
diode drop, as seen on Fig. 7(b). As
the gate voltage of the LS MOSFET
turns on after the dead time, the drain
current will continue to rise until it
reaches the inductor current and the
HS MOSFET turns off.
The slow rise time of the current
can be directly attributed to the HS
and LS source inductors because the
inductors will resist any sudden
change in current. Because the current
flows from the source to the drain of
the LS MOSFET, the voltage developed across the source parasitic
inductance (lead and pc-board trace
inductance) actually assists the turnon cycle.
It appears that the parasitic inductance of the HS MOSFET determines
the current transition here, as described before. When the LS MOSFET
is turned off, the current will flow
in its body diode until the HS
MOSFET starts turning on, the voltage developed across the parasitic
inductance will force the gate-source
voltage into a negative value. Since the
gate is held at the ground, this will
help keep the LS MOSFET off during
this transition.
The graphs shown in Fig. 7 present
Power Electronics Technology
February 2005
BUCK CONVERTER LOSSES
1
2
+
M1
L2 & L4 are the
package lead
inductance and
PCB trace
inductance
1
2
M2
Vcc
-
1
L
because of the inaccuracies of the
current dividers used.
Noninvasive Current
Measurement
2
+
CL
-
L1 & L3 are
large loop for
current probe
0
0
Fig. 8. Wiring technique to minimize lead inductance while enabling current measurement.
no surprises, and hence, the losses in
the LS MOSFET appear to continue
to be mostly conduction or ohmic
losses since the drain-source voltage
is always held low while the current is
switching on and off. The measured
currents in the HS and LS MOSFETs
do not exactly match in these graphs
Current measurement in highfrequency dc-dc converters is difficult,
because inserting a loop to measure
current or a sense resistor will alter
the original conditions. This led us
to propose the use of the circuit in
Fig. 8.
In this approach, we use two parallel loops of wire (L1& L2 and L3 &
L4). L1 and L3 are loops that are
barely long enough to accommodate
the scope current probe, while L2
and L4 are a very short wire (e.g.,
the MOSFET package lead plus the
pc-board trace inductance). In this
way, we have created a current divider where the majority of the current flows in the short wire (L2 and
L4) without disturbing the circuit
much while a much smaller portion
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BUCK CONVERTER LOSSES
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which is roughly the ratio between
the two areas occupied by the two
loops. Fig. 9 shows the method used
to measure a sample of the current
with the least disturbance of the original circuit.
The current understanding of HS
MOSFET switching must include the
effects of the circuit parasitic inductances and their effects on the switching performance of the synchronous
buck dc-dc converter and other
topologies. These parasitic inductances are namely the package lead
inductance and the pc-board trace
inductances.
The HS MOSFET source parasitic
inductance has several effects on
switching performance. First, the HS
MOSFET will continue to conduct
current even after the gate voltage
reaches 0 V (ground level). This is due
to the negative back EMF of the para-
sitic inductance pulling the source to
a negative level with respect to the
gate, allowing the current to flow
freely. A second effect is that the drain
current fall time is proportional to
the current level. This leads to losses
proportional to Idrain2, and thus much
larger switching losses even with the
best MOSFETs. Thirdly, the drain
current fall time is proportional to
the parasitic inductance value. This
puts a limit on the maximum power
efficiency available from the dc-dc
converter regardless of how fast the
HS MOSFET is.
In order to reach high switching
speeds, certain component characteristics must be obtained. MOSFETs
must have low Qgd and Qsw. Packages
must facilitate the connection of
the gate driver directly between the
gate and the source using non current-carrying leads or pc-board
traces. A ball grid array (BGA) is an
excellent package for this purpose.
Furthermore, gate drivers must provide a true differential gate-source
drive signal, low source and sink resistance, and very fast rise and fall
times.
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