IR HiRel Space Product update
MEWS26
October 24, 2013
Tiva Bussarakons
Max Zafrani
International Rectifier Globally
• 8 Manufacturing Centers, ► 11 Design Centers
■ Global Service and Technical Assistance Centers
► Skovlunde,
► Reigate, U.K.
Denmark
■
■ Frankfurt,
Germany
■ Shenzen,
China
• ► San Jose, CA
• St Paul, MN
ISO14001
ISO9001
MILPRF38534
MILPRF19500
JANS
ISO9001
MILPRF38534
• Newport, Wales, UK
TS16949
ISO14001
ISO9001
► ■ Japan
► Rhode Island
■ Shanghai,
China
► Provence, France
•Leominster, MA
► Durham, NC
► Irvine, CA
► Pavia, Italy
■ Singapore
• Tijuana,
• ► ■ El Segundo, CA
TS16949,
ISO9001, JANS,
ISO14001
• Temecula, CA
TS16949
JANS
ISO14001
• Mesa, AZ
TS16949
ISO9001
ISO14001
Mexico
TS16949,
ISO9001
ISO14001
2
HiRel Product Technologies
• DC/DC converters
o
o
o
o
o
5W to >250W output power, higher power with parallel operations
Converter efficiency of up to 92%
PCB assembly style and enclosed aluminum housing available
DSCC class H and K SMDs
Single, dual, triple, and quad outputs
• Hybrids/Modules
o
o
o
o
o
o
o
Application specific hybrids ie: Solid State Relays, AC Switches, etc
Custom packaging ie: hermetic and near hermetic
Extended temperature range, extensive screening operation
Rad Hard Low Drop Out Regulators
Half bridges
H-bridges
3-Phase bridges
• Discrete Semiconductors
o RAD-Hard MOSFETs and MOSFET Drivers
o Logic Level RAD-Hard MOSFETs
o Hermetic MOSFETs and IGBTs
o Schottky Rectifiers
3
Development History of IR’s Rad-Hard MOSFETs
1989
1998
2002
2005
2013
R7
R8
1st generation radhard MOSFETs with
excellent total dose
performance
2nd generation
• Reduced RDS(on)
• Reduced QG
• Improved SEGR/SEB
3rd generation
• Best in class RDS(on)
• Improved SEE SOA
• Shape die to better fit
packages for optimum
RDS(on)/QG
performance
1st logic level gate drive
• Developed specifically
for POL buck
regulators and
synchronous
rectification to
improve efficiency
• Comparable TID/SEE
to R6
Logic level gate drive
Developed with further
reduction in RDS(on) and
gate charge for low
voltage POL and
synchronous rectification
designs with comparable
TID and SEE performance
to R6
N: 100 to 500V
P: 60 to 200V
N: 30V to 250V
P: 60 to 200V
N: 100 to 600V
N: 60 to 250V
P: 60V
N: 20V to 60V
Hexagon cells
5 µm feature size
Stripe planar technology
1.5 µm feature size
Stripe planar technology
0.6 µm feature size
Stripe planar technology
0.6 µm feature size
Trench technology
0.5 µm feature size
R5 , R6 AND R7 TECHNOLOGY
(Stripe planar technology)
5 µm
1.5 µm
0.6 µm
0.5 µm
4
Rad-Hard MOSFET Voltage vs Generation
BVDSS
600V
500V
400V
BVDSS
N-Channel
P-Channel
- 200V
R6
Gen4
Gen4
R5
- 100V
250V
R7
R5 R7
100V
- 60V
60V
R8
30V
‘89
>>
‘02
Gen4
• 30V to 500V
• 100K to 1000K Rads
R5
• 30V to 250V
• 100K to 1000K Rads
R6
• 100V to 600V
• 100K to 300K Rads
‘06
‘08
‘13
R7 Logic Level
• 60V to 250V
• 100K to 300K Rads
R8 Trench
• 20V to 60V
• 100K to 300K Rads
- 30V
‘89
>>
‘02
Gen4
• -60V to -200V
• 100K to 1000K Rads
R5
• -30V to -200V
• 100K to 1000K Rads
‘06
‘08
‘13
R6 (Dev)
• -60V to -200V
• 100K to 300K Rads
R7 Logic Level
• -60V to -100V
• 100K to 300K Rads
5
Radiation Hardened MOSFETs
Three New Discrete Products from IR
• R8 - New Rad-Hard MOSFETs
• SMD 0.2 - New Low Power Package
• SupIR SMD-2 - New High Power Package
Extended Performance Characterization
• Extended SOA curves for linear applications
6
R8
New Rad-Hard MOSFET for POL Applications
Rad-Hard N Channel MOSFET Trench Technology
FEATURES:
 20 V BVDSS
 ±12V BVGSS
 100 Krads to 300 Krads TID
 SEE immune with LET of 81 MeV-cm2/mg
 Logic level gate drive similar to R7
 RDS(on) -- 12 mΩ typ./15 mΩ max.
 QG -- 18 nC typ./24 nC max.
 Available in SMD 0.2, the industry’s smallest
surface-mount power package and TO-39
o IRHLNM87Y20
o IRHLF87Y20
Part Number
TID
Package
BVDSS
ID
RDS(on) max
QG max
ƟJC
IRHNM87Y20SCS
100Krads
SMD 0.2
20V
17A
15 mΩ
24 nC
3.5 °C/W
IRHNM83Y20SCS
300Krads
SMD 0.2
20V
17A
15 mΩ
24 nC
3.5 °C/W
IRHLF87Y20SCS
100Krads
TO-39
20V
12A
32 mΩ
27 nC
8.0 °C/W
IRHLF83Y20SCS
300Krads
TO-39
20V
12A
32 mΩ
27 nC
8.0 °C/W
7
R8
Typical Single Event Effects (SEE) Performance
• Tests performed at Brookhaven National Laboratory
LET
Energy
Range
MeV/(mg/
cm2)
MeV
µm
VGS = 0V
VGS = -1V
Br
36.93
298
38.2
18
18
I
59.72
320
31
18
18
12
8
Au
81.43
332
27.5
18
18
12
6
VGS = -3V
VGS = -5V VGS =-10V
8
4
IRHLC87Y20 Typical SEE SOA
25
20
VDS (V)
ION
VDS (V)
15
BR
10
I
5
AU
0
0
2
4
6
VGS (V)
8
10
12
8
R8 Typical POL Application
• Designed for Point of Load (POL) voltage regulators, general purpose switching and linear
voltage regulator applications
9
R8
•
Increases Efficiency Performance, R8 vs. R5
R8 offers efficiency improvement over R5 (refer to efficiency plots below)
o 1.2V output: 3.9 to 6.0%
o 3.3V output: 1.5 to 3.1%
•
R5: IRHNJ57Z30, 30V - RDS(on) = 20 mΩ max, QG = 65 nC max
•
R8: IRHNM87Y20, 20V - RDS(on) = 15 mΩ max, QG = 24 nC max
3.1%
1.5%
3.9%
6.0%
10
Selection of Hermetic Packages
Low Power: 0.6W to 29W
NEW
TO-39
MO-036
UB
LCC-6
SMD-0.2
(NM/U8)
LCC-18
High Power: 75W to 300W
SMD-0.5
TO-257
Also: Low
Ohmic/Tab-less
SMD-1
TO-254
Also: Low
Ohmic/Tab-less
LCC-28
NEW
SMD-2
SupIR SMD-2™
(NX)
11
New SMD 0.2 Package for Low Power MOSFETs
A space qualified compact surface mount package only from IR for low power
applications
NEW
• Industry’s smallest surface mount
power package
SMD 0.5
• 50% smaller than SMD 0.5
• 75% lighter (only 0.25 g)
• Aluminum nitride (AlN) case
SMD 0.2
• R5 and R7 250V devices are in
qualification
• Patented design (U.S. Patent No.
7,508,506 B2)
1.0 g
0.25g
0.2”
(5 mm)
0.3”
(8 mm)
0.3”
(8 mm)
0.4”
(10 mm)
DLA JANS Qualified Devices
• JANSR2N7503U8 (IRHNM57110SCS), R5, 100V, N Channel
• JANSR2N7506U8 (IRHNM597110SCS), R5, 100V, P Channel
• IRHNM77110SCS (JANSR2N7609U8), R7, 100V, N Channel – in process
12
New SMD 0.2 Package Construction
Lid – Kovar or ceramic
Cu Metalization
O-Ring - Kovar
Wall/Bottom
- AlN
Top View
Internal View
Bottom View
0.305”L x0.21”W x 0.10”H
13
New SupIR SMD-2™ Package
SupIR SMD-2™ - Latest packaging Innovation
from International Rectifier for Space Grade
Rad-Hard Power MOSFETs and Power
Rectifiers
NEW
SupIR SMD-2™
FEATURES:
• JANS qualified IAW MIL-PRF-19500
• Improved performances compared to the
nearest packaging solutions, SMD-2
package with a carrier
SMD-2
SMD-2 with Carrier
Carrier
 35% smaller, 0.376 in2 vs. 0.583 in2
1.127”
 45% lighter. 2.8 g vs. 5.1 g
0.710”
0.417”
 Lower thermal resistance by 0.25°C/W
(37%)
 Lower package resistances by 30%,
0.68 Ω vs. 0.97 Ω
0.530”
 Lower parasitic inductance by 76%,
0.52 µH vs. 2.19 µH
 Yield a higher current rating, 82A vs.
0.528”
56A
• Facilitates assembly design and reduces
costs
37% Foot Print Reduction
• Accommodates the largest IR’s size 6 die
+
=
14
SupIR SMD-2™ - Package Construction/Qualification
Lid - Kovar
Frame –
Alumina,
94%
Seal Ring Kovar
Lead – OFHC Cu
Base –
85% W/ 15% Cu
Products Qualification
• HFB60HNX20SCS, 35ns, 200V, 60A -- released
• IRHNX67160SCS, R6, 100V – in process
• IRHNX67164SCS, R6, 150V – in process
• IRHNX67260SCS, R6, 200V – in process
• IRHNX67264SCS, R6, 250V – in process
JANS Qualified IAW MIL-PRF-19500
• X-ray, Wire Bond Pull, Die shear, Leak
testing
• PIND
• RGA
• Salt atmosphere
• 300C bake
• Barometric pressure (500V @ 33 Torr)
• 500 temperature cycles (-55C to 150C,
air to air)
• Solderability
• Thermal shock 15 cycle (-55C to 125C,
liquid to liquid)
• Terminal strength
• Moisture resistance
• Shock, vibration, constant acceleration
• Resistance to soldering heat
• S level qualified – HFB60HNX20SCS
• Available soon
15
SupIR SMD-2™ In-Circuit Benefits Example
IR DC-DC converter
EGA Series
High efficiency 300W EPC for
GaN SSPA
SupIR-SMD-2™
• Primary H-bridge with four MOSFETs and a
secondary Hy-Bridge (current doubler) stage
with two MOSFETs for synchronous rectification
• SMD-2 with leads can only dissipate about 2W
• SMD-2 would require parallelling MOSFETs which
has a penalty in switching losses and in the
snubber size needed to dampen the energy from
the stray inductance of the transformer that may
cause excess stress to the MOSFET due to their
output capacitance
• SupIR SMD-2™ can dissipate 4W, no need for
parallel:
 6 MOSFETs instead of 12
16
Benefits of SupIR SMD-2™
SupIR SMD-2™ vs. SMD 2 with Leads
Benefits of SupIR SMD-2™
• 2x power dissipation
• 6 MOSFETs instead of 12
EGA Efficiency (Vin 50V, V1=50V)
Efficiency
95.0%
• 1.4% increase in efficiency
lower cost
• 18 cm² smaller
90.0%
• 40 g lighter PCB-area
• less circuit complexity
85.0%
• higher reliability
+25°C
-40°C
-20°C
80.0%
+75°C
75.0%
0
1
2
3
4
5
6
7
V1 Current [A]
Load condition: V1: 50V, V2: +8V 0A, V3: -8V 0A
17
Systems
GIDEP SYSTEM
CENTRAL DATABASE for Information
and Data Exchange
GIDEP DATABASE STRUCTURE
Failure Experience
Data
(FED)
- Product Alert
- Product Advisory
Diminishing
Manufacturing
Sources &
Material
Shortages
(DMSMS)
- EOL
- Last Time Buy
Product
Information Data
- Product Change Notice
- Process Change Notice
18
Systems
GIDEP SYSTEM
Issued GIDEP
INFORMATION
AND DATA
records are
posted and
accessible on
IR Web Site:
http://www.irf.com/product-info/hi-rel/alerts.html
19
SOA Curve and Linear Mode Operation
Where is it safe to operate the MOSFET in
the Id, Vds and pulse width domain?
The straight SOA lines assume that power
dissipation is uniform under all power
conditions
However power dissipation is not uniform
in the MOSFET under all power conditions
Local thermal runaway in the MOSFET’s
linear mode of operation limits the SOA
20
How is the new method done?
Better method of assigning SOA
Dr. P. Spirito [1] et. Al. suggest —
As transconductance increases
(e.g. in shorter channel lengths,
from planar to trench devices [2]):
1.
the drain current temperature
dependence can become positive like
power BJTs
2.
the likelihood of hot spots (thermal
instability) increases
3.
and the SOA degrades
21
Transfer Curves Per Generation
Shorter Channel Length
Stronger Temperature Dependence of Drain Current
Greater Propensity for Severe Thermal Instability
22
R5 200V P-Channel Spirito versus Actual (new DC curves)
Measured
Curve
Spirito Curve
23
Preventing Linear Mode failure
• Use older generation MOSFETs with
lower gain when possible
• Select devices with low ZTC point
• Make sure that the MOSFET Zero
Temperature Coefficient (ZTC) point is
low or operate above it
Safe
ZTC
Un-Safe
• Avoid operation near the SOA boundary
• Choose smaller of two devices as it will
be less sensitive to thermal current
focusing
24