z Reading
B. Razavi Chapter 10.
z Introduction
In this lecture, we deal with the stability and frequency compensation of linear feedback systems to the extent necessary to understand design issues of analog feedback circuits. Beginning with a review of stability criteria and the concept of phase margin, we study frequency compensation, introducing various techniques suited to different op amp topologies. We also analyze the impact of frequency compensation on the slew rate of twostage op amps.
Analog-Circuit Design 10-1 Ching-Yuan Yang / EE, NCHU
1

z General considerations
Y
=
H ( s )
‡ Close-loop transfer function:
X 1 + β H ( s if β H ( s = j ω 1) = − 1, the gain goes to infinity,
) and the circuit can amplify is own noise until it eventually begins to oscillate at frequency
ω 1.
‡ Barkhausen’s Criteria:
| β H ( s = j ω 1) | = 1
∠ β H ( s = j ω 1) = − 180 o .
The total phase shift around the loop at ω
1 is 360 o because negative feedback itself introduces 180 o of phase shift. The 360 o phase shift is necessary for oscillation since the feedback must add in phase to the original noise to allow oscillation buildup. By the same token, a loop gain of unity (or greater) is also required to enable growth of the oscillation amplitude.
Analog-Circuit Design 10-2 Ching-Yuan Yang / EE, NCHU
z A negative feedback system may oscillate at ω 1 if
(1) the phase shift around the loop at this frequency is so much that the feedback becomes positive .
(2) the loop gain is still enough to allow signal buildup.
Unstable system Stable system
Analog-Circuit Design 10-3 Ching-Yuan Yang / EE, NCHU
2

Root locus :
(a)
Pole frequency s
P
= j ω
P
+ σ
P
σ
P
> 0, unstable with growing amplitude
σ
P
= 0, unstable with constantamplitude oscillation
(b)
Analog-Circuit Design
(c)
10-4
σ
P
< 0, stable
Ching-Yuan Yang / EE, NCHU
z Assuming H ( s ) = A
0
/(1 + s / ω
0
), β is less than or equal to unity and does not depend on the frequency, we have
Y
X
( )
=
1 +
H (
β H s )
( s )
=
1 +
1
ω
0
+
A
0
β A
0 s
(
1 + β A
0
) z Bode plots of loop gain: Root locus: s
P
= − ω
0
(1 + β A
0
)
20dB/dec
0.1
ω
0
10 ω
0
Analog-Circuit Design 10-5
A single pole cannot contribute a phase shift greater than 90o and the system is unconditionally stable for all non-negative valuesof β .
Ching-Yuan Yang / EE, NCHU
3

z Assuming the open-loop transfer function
H ( s ) =

1 +
ω s p 1
A
0





1 +
ω s p 2 z Bode plots of loop gain:
Analog-Circuit Design
‡
‡
The system is stable because | β H | drops to below unity at a frequency for which ∠ β H < − 180 o .
To reduce the amount of feedback, we decrease
β , obtaining the gray magnitude plot in the figure.
For a logarithmic vertical axis, a change in β translates the magnitude plot vertically. Note that the phase plot does not change.
‡ The stability is obtained at the cost of weaker feedback.
10-6 Ching-Yuan Yang / EE, NCHU
z Assuming the open-loop transfer function
H ( s ) =
A
0 z Bode plots of loop gain:
 1 +
ω s p 1

 1 +
ω s p 2

 1 +
ω s p 3
Analog-Circuit Design
If the feedback factor β decreases, the circuit becomes more stable because the gain crossover moves toward the origin while the phase crossover remains constant.
10-7 Ching-Yuan Yang / EE, NCHU
4

z Close-loop frequency and time response
Small margin Large margin
Analog-Circuit Design 10-8 Ching-Yuan Yang / EE, NCHU
z Phase margin (PM) is defined as where ω
1
PM = 180 o + ∠ β H ( ω = ω
1
) is the gain crossover frequency.
z Example
|
A two-pole feedback system is designed such that |
ω
P 1
| << | ω
P 2
| .
β H ( ω = ω
P 2
) | = 1 and
Analog-Circuit Design 10-9
Since ∠ β H reaches − 135 o at
ω = ω
P 2
, the phase margin is equal to 45 o .
Ching-Yuan Yang / EE, NCHU
5

z For PM = 45 o , at the gain crossover frequency ∠ β H ( ω
1
) = − 135 o and
| β H ( ω
1
) | = 1, yielding Y
X
=
1 + 1 ⋅
H ( exp j
(
ω
−
1
) j 135 ° )
=
H
0 .
29
(
− j ω
1
)
0 .
71 j
It follows that
Y
X
=
1
β
⋅
0 .
29
1
− 0 .
71 j
≈
1 .
3
β
The frequency response of the feedback system suffers from a 30% peak at ω = ω
1
.
z Close-loop frequency response for 45 o phase margin:
Analog-Circuit Design 10-10 Ching-Yuan Yang / EE, NCHU
z Close-loop time response for 45 o , 60 o , and 90 o phase margin: z For PM = 60 o , Y ( j ω
1
)/ X ( j ω
1
) = 1/ β , suggesting a negligible frequency peaking.
This typically means that the step response of the feedback system exhibits little ringing, providing a fast settling. For greater phase margins, the system is more stable but the time response slows down. Thus, PM = 60 o is typically considered the optimum value.
z The concept of phase margin is well-suited to the design of circuits that process small signals. In practice, the large-signal step response of feedback amplifiers does not follow the illustration of the above figure. For large-signal applications, time-domain simulations of the close-loop system prove more relevant and useful than small-signal ac computations of the open-loop amplifier.
Analog-Circuit Design 10-11 Ching-Yuan Yang / EE, NCHU
6

z Example:
Unity-gain buffer: PM ≈ 65 o , unity-gain frequency = 150 MHz.
However, the large-signal step response suffers from significant ringing.
z The large-signal step response of feedback amplifiers is not only due to slewing but also because of the nonlinear behavior resulting from large excursions in the bias voltages and currents of the amplifier. Such excursions in fact cause the pole and zero frequencies to vary during the transient, leading to a complicated time response. Thus, for large-signal applications, time-domain simulations of the close-loop system prove more relevant and useful than small-signal ac computations of the open-loop amplifier.
Analog-Circuit Design 10-12 Ching-Yuan Yang / EE, NCHU
z Typical op amp circuits contain many poles. For this reason, op amps must usually be “compensated,” that is, the open-loop transfer function must be modified such that the closed-loop circuit is stable and the time response is well-behaved.
z Stability can be achieved by minimizing the overall phase shift, thus pushing the phase crossover out .
Moving PX out
:
‡ This approach requires that we attempt to minimize the number of poles in the signal path by proper design.
‡ Since each additional stage contributes at least one pole, this means the number of stages must be minimized, a remedy that yields low voltage gain and/or limited output swings.
Analog-Circuit Design 10-13 Ching-Yuan Yang / EE, NCHU
7

z Stability can be achieved by dropping the gain thereby pushing the gain crossover in .
Discussion :
‡ This approach retains the low frequency gain and the output swings but it reduces the bandwidth by forcing the gain to fall at lower frequencies.
Moving GX in
Analog-Circuit Design 10-14 Ching-Yuan Yang / EE, NCHU
z Determine the poles of the circuit:
We identify a number of poles in the signal paths: path 1 contains a high-frequency pole at the source of M
3
, a mirror pole at node A , and another high-frequency pole at the source of M
7
, whereas path 2 contains a high-frequency pole at the source of M
4
. The two paths share a pole at the output.
‡ Dominant pole: the closest to the origin.
ω p , out
= 1/( R out
C
3-dB bandwidth .
L
), usually sets the open-loop
‡ Nondominant poles:
( mirror pole )
ω
ω p , A
= g m 5
/ C
A
, the closest pole to the origin after ω p , out where C
A p , N
= g m 7
Since g m
= C
GS 5
/ C
N
= 2 I
,
D
ω p , X
/ | V
GS
+ C
GS 6
+ C
DB 5
+ 2 C
GD 6
= g m 3
/ C
X
= g m 4
/ C
Y
− V
TH
| , if M
4 and
=
M
7
ω
+ C
DB 3 p , Y
.
are
.
+ C
GD 3
. designed to have the same overdrive, they exhibit
Pole locations : the same transconductance. From square-law characteristics, we have
W
4
/ W
7
= µ p
/ µ n
≈ 1/3. Thus, nodes N and X ( Y ) see roughly equal small-signal resistances but node N suffers from much more capacitance.
Analog-Circuit Design 10-15 Ching-Yuan Yang / EE, NCHU
8

z Bode plots of loop gain for op amp: using β = 1 for the worst case.
‡ The mirror pole ω p , A typically limits the phase margin because its phase contribution occurs at lower frequencies than that other nondominant poles .
Analog-Circuit Design 10-16 Ching-Yuan Yang / EE, NCHU
z Translating the dominant pole toward origin to compensate the op amp:
‡ Assuming ω p , A
> 10 ω p , out
, we must force the loop gain crossover point moves toward the origin. We can simply lower the frequency of the dominant pole
( ω p , out
) by increasing the load capacitance.
‡ The key point is that the phase contribution of the dominant pole in the vicinity of the gain or phase crossover points is close to
90 o and relatively independent of the location of the pole. That is, translating the dominant pole toward the origin affects the magnitude plot but not the critical part of the phase plot.
Analog-Circuit Design 10-17 Ching-Yuan Yang / EE, NCHU
9

z How much the dominant pole must be shift down?
Assume (1) the 2 nd nondominant pole
( ω p , N
) is quite higher than the mirror pole so that the phase shift at ω = ω is equal to − 135 o , and (2) PM = 45 o .
p , A
‡ C
L
→ ( ω / ω by a factor of
’
ω p , out
) C p , out
/ ω
L
’
. The load p , out
.
‡ The unity-gain bandwidth of the compensated op amp is equal to the frequency of the nondominant pole .
‡ To achieve a wideband in a feedback system employing an op amp, the first nondominant pole must be as far as possible. z Although
R does
A higher
ω not
R
= ( R out
C
L
) − 1 , increasing compensate the op amp. results in a greater gain, portion of the characteristics.
Analog-Circuit Design 10-18 Ching-Yuan Yang / EE, NCHU
Z out
= (
1 + g m 5 r o 5
)
Z
N
+ r o 5
≈ (
1 z C
N
+ g
Z m 5
N r o
= C
GS 5
=
5
) r r o 7 o 7
C r o 7
N s
+
|| ( C
N
+
C
1 s
SB 5
) − 1
+ +
, where body effect is neglected. We have
,and
C
Z
GD 7 out C
+
1
L s
C
DB 7
=
[ (
1 + g m 5
( r
1 o 5
+
) r g o 7 m 5
C r
L o 5
+
) r r o 7 o 7
C
N
] s + 1 z A pole with τ = (1 + g m 5 r o 5
) r o 7
C
L
+ r o 7
C
N
, where (1 + g m 5 r o 5
) r o 7
C
L is simply due to the low-frequency output resistance of the cascode. The pole in the PMOS cascode is merged with the output pole, thus creating no addition pole. It merely lowers the dominant pole by a slight amount.
z For g m r o
>> 1 and C
L
> C
N
, then τ ≈ g m 5 r o 5 r o 7
C
L
.
Analog-Circuit Design 10-19 Ching-Yuan Yang / EE, NCHU
10

z We identify three poles at X (or Y ), E (or F ) and A (or B ).
A pole at X (or Y ) lies at relatively high frequencies. Since the small-signal resistance seen at E is quite high, even the capacitances of resistance is lower but the value of circuit exhibits two dominant poles.
C
L
M
3
, M
5 and M can create a pole relatively close to the origin. At node A , the small-signal
9 may be quite high. Consequently, the z One of the dominant poles must be moved toward the origin so as to place the gain crossover well below the phase crossover. If the magnitude of is to be reduced, the available bandwidth is limited to approximately ω
ω low value. Furthermore, this required dominant pole translates to a very large compensation capacitor.
p , A p , E
, a
Analog-Circuit Design 10-20 Ching-Yuan Yang / EE, NCHU
z In a two-stage amp as shown in Fig.(a), the first stage exhibits a high output impedance and the second stage provides a moderate gain, thereby providing a suitable environment for Miller multiplication of capacitors.
z In Fig.(b), we create a large capacitance at E , the pole is ω p , E
=
R out 1
[
C
E
+
As a result, a low-frequency pole can be established with a moderate capacitor value, saving considerable chip area.
1
(
1 + A v 2
)
C
C
] z In addition to lowering the required capacitor value, Miller compensation entails a very important property: it moves the output pole away from the origin. ( pole splitting )
Analog-Circuit Design 10-21 Ching-Yuan Yang / EE, NCHU
11

z Pole splitting as a result of Miller compensation.
z Discussion z Two poles: (based on the assumption | ω p ,1
| << | ω p ,2
| )
ω p 1
≈
R
S
[ (
1 + g m 9
R
L
)(
C
C
+ C
GD 9
)
1
+ C
E
]
+ R
L
(
C
C
+ C
GD 9
+ C
L
)
Simplified circuit of a two-stage op amp:
R
S
= the output resistance of 1 st stage.
ω p 2
≈
R
S
[ (
1
R
S
+ g m 9
R
L
[
R
L
(
C
C
)(
+
C
C
+
C
GD 9
C
GD 9
)
C
E
+
)
+
(
C
E
C
C
+
]
+ R
L
C
GD 9
(
C
C
)
C
L
+
+
C
GD 9
C
E
C
L
+
]
C
L
)
R
L
= r o9
|| r o11 z For C
C
For C
C
= 0 and relatively large C
L
, ω p ,2
≠ 0 and C
C
+ C
GD 9
>> C
E
, ω p ,2
≈ 1/( R
L
C
L
).
≈ g m 9
/( C
E
+ C
L
).
Typically C
E
<< C
L
, we conclude that Miller compensation increases the magnitude of the output pole ( ω p ,2
) by a factor of g m 9
R
L
, a relatively large value.
z Miller compensation moves the interstage pole toward the origin and the output pole away from the origin, allowing a much greater bandwidth than that obtained by merely connect the compensation capacitor from one node to ground.
Analog-Circuit Design 10-22 Ching-Yuan Yang / EE, NCHU
z Effect of right half plane zero
‡ The circuit contains a right-half-plane zero at
ω z
= g m 9
/( C
C
+ C
GD 9
) because C
C
+ C
GD 9 forms a “parasitic” signal path from the input to the output.
‡ A zero in the right hand plane contributes more phase shift, thus moving the phase crossover toward the origin. Furthermore, from Bode approximations, the zero slows down the drop of the magnitude, thereby pushing the gain crossover away from the origin. As a result, the stability degrades considerably.
‡ For two-stage op amps, typically | ω p 1
| < | ω z
| < | ω the zero introduces significant phase shift while p 2
| , preventing the gain from falling sufficiently.
The right-half-plane zero is a serious issue because g m is relatively small and C
C is chosen large enough to position the dominant pole properly.
Analog-Circuit Design 10-23 Ching-Yuan Yang / EE, NCHU
12

z Addition of R z to move the right hand plane zero.
‡ The zero is given by .
g
− m
1
9
ω ≤ 0.
‡ We may move the zero well into the left plane so as to cancel the first nondominant pole. That is
C
C
(
1 g
− m
1
9
− R z
)
=
C
−
L g m
+
9
C
E
⇒ R z
=
C
L
+ g m
C
E
+
9
C
C
C
C ≈
C
L g m
+ C
C
9
C
C
, because C
E
<< C
L
+ C
C
.
• Drawbacks:
1. It is difficult to guarantee the relationship of the above equation, especially if C
L is unknown or variable.
2. The actual implementation of R z is variable. R z is typically realized by a MOS transistor in the triode region.
Analog-Circuit Design 10-24 Ching-Yuan Yang / EE, NCHU
z Generation of V b for proper temperature and process tracking.
‡ If I
1 is chosen with respect to I
D 9 such that
V
GS 13
Since
= V
GS 9
, then V
GS 15 g m 14
= µ p
C ox
( W / L )
= V
GS 14
.
14
( V
GS 14
− V
TH 14
) and R on 15
= [ µ p
C ox
( W / L )
15
( V
GS 15
− V
TH 15
)] − 1 , we have R on 15
= g
( W m 14
/
( W
L )
14
/ L )
15
For pole-zero cancellation to occur,
( W / L )
14 g m 14
( W / L )
15
=
C
L
+ C g m 9
C
C
C and hence ( W / L )
15
= ( W / L )
14
( W / L )
9
I
D 9
I
D 14
C
C
C
C
+ C
L
If C
L is constant, it can be established with reasonable accuracy because it contains only the ratio of quantities.
Analog-Circuit Design 10-25 Ching-Yuan Yang / EE, NCHU
13

z Method of defining g m 9 with respect to R
S.
Goal:
R z
=
C g
L
+ m 9
C
C
C
C
⋅⋅⋅⋅⋅⋅⋅⋅ (A)
‡ The technique incorporates M b 1
M b 4 along with R
S to generate
Thus, g m 9
∝ I
D 9
∝
I b
∝ R
− 2
S
I
D 11
∝ R
S
− 1
Proper ratioing of R
Z and R
S therefore ensures (A) is valid even with temperature and process variations
Analog-Circuit Design 10-26 Ching-Yuan Yang / EE, NCHU
‰ One-stage op amps: ‰ Two-stage op amps: z In one-stage op amps, a higher load capacitance brings the dominant pole closer to the origin, improving the phase margin (albeit making the feedback system more overdamped).
z In two-stage op amps, since Miller compensation establishes the dominant pole at the output of the first stage, a higher load capacitance presented to the second stage moves the second pole toward the origin, degrading the phase margin.
z Illustrated in the figure is the step response of a unity-gain feedback amplifier, suggesting that the response approaches an oscillatory behavior if the load capacitance seen by the two-stage op amp increases.
Analog-Circuit Design 10-27 Ching-Yuan Yang / EE, NCHU
14

‰ Positive slewing: ‰ negative slewing: z The positive slew rate equals I
SS currents: I
SS then V
X and I
1
. If M
5
/ C
C
. During slewing, M is not wide enough to sustain drops significantly, possibly driving M
1
I
5
SS must provide two
+ I
1 in saturation, into the triode region.
z During negative slew rate, I
1 must support both I
SS and I
D 5
. For example, if I
1
= I
SS
, then V
X rises so as to turn off M
5
. If I
1
< I
SS
, then M
3 triode region and the slew rate is given by I
D 3
/ C
C
.
enters the
Analog-Circuit Design 10-28 Ching-Yuan Yang / EE, NCHU
z Two-stage op amp with right half plane zero due to C
C
: z Addition of a source follower to remove zero:
Equivalent circuit :
Source follower
Analog-Circuit Design
† Since C
GS of M
2 is typically much less than C
C expect the right frequencies.
, we
†
V out
V in
− g m 1
V
1
=
= V out
(
R −
L
1
V out
1
+ g m 2
−
C
V
1
1
C s
+
+ C
L s
I in
=
)
Ö
V
1
V
1
R
S
= g
− V out m 1
R
L
R
L
C
L
C
C
( 1 + g m 2
R
S
) s 2
−
+ g m 1
R
[
( 1 +
L
R
S g m 1
( g m 2
+ C g m 2
R
L
R
S
C s )
) C
C
(
1 + R
L
C
L s
Zero in the left hand plane
+ g m 2
R
L
C
L
] s
)
+ g m 2
† Assume
(1 + g m 1
ω g p 1 m 2
R
<<
L
R
S
ω p 2
) C
C
, since typically 1 + g m 2
>> g m 2
R
L
C
L
, we have
R
ω p 1
≈ g m 1
R
L
1
R
S
C
C and
ω p 2
≈ g
C m 1
L
(Note ω p 2
:
1
S
R
L
C
L
>> 1 ,
→ g m 1
C
L
)
10-29 Ching-Yuan Yang / EE, NCHU
15

ƒ Equivalent circuit : z The primary issue is that the source follower limits the lower end of the output voltage to V
GS 2
+ V
I 2
. In the CG topology, C
C and the CG stage M convert the output voltage swing to a current, returning the result to the
2 z gate of M
1
V out
+ g m
C
C
2
V
2 s
=
.
− V
2
, g m 1
V
1
+ V out


1
R
L
+ C
L s


= g m 2
V
2 and ,
S g m 2
V
2
V out
I in
=
R
L
C
L
C
C s 2 +
[ (
1 + g
− g m 1
R m 1
R
S
S
) g m
R
L
2
R
( g m
L
C
C
2
+
+
C
S
C
C s
+
) g m 2
R
L
C
L
] s + g m 2
Using approximations, ω p 1
≈
1 g m 1
R
L
R
S
C
C and ω p 2
≈ g m 2
R
S
C
L g m 1 .
Analog-Circuit Design 10-30 Ching-Yuan Yang / EE, NCHU
Positive slewing:
Negative slewing: z For positive slewing, M
2 and I
1 must support I
SS
, requiring I
1 turning M
1
≥ I
SS
+ I
D 1 off, and if I
. If I
1
1 is less, then V
P
< I
SS
, M
0 drops, and its tail current source must enter the triode region, yielding a slew rate equal to I
1
/ C
C
.
z For negative slewing, and I
D 2
. As I
SS
I
2 must support both I
SS flows into node P , V
P tends to rise, increasing I
D 1
. Thus, M
1 absorbs the current produced by I
3 through C
C
, tuning off M
2 and opposing the increase in V
P
. We can therefore consider P a virtual ground node.
z For equal positive and negative slew rates, I
3
(and hence I
2
) must be as large as I
SS
, raising the power dissipation.
Analog-Circuit Design 10-31 Ching-Yuan Yang / EE, NCHU
16

Analog-Circuit Design 10-32 Ching-Yuan Yang / EE, NCHU
17