Modeling Methodology for On-Chip Coplanar Transmission Lines over the Lossy Silicon Substrate
David Goren, Rachel Gordin, Michael Zelikson
IBM Haifa Labs
Haifa University, Mount Carmel, Haifa, 31905 Israel
email: davidg@il.ibm.com
Abstract
This paper presents a wideband modeling methodology for
on-chip coplanar single and coupled transmission lines over
the conductive silicon substrate. Cost effective, semi analytical
models have been developed, being purely based on explicit
expressions. Silicon substrate induced loss and dispersion
effects are considered, as well as the skin and proximity
effects, while accounting for thick metals. The models have
been verified against both numerical computations (full wave
HFSS and quasi-static SI2D and EM2D solvers) and hardware
measurements (40 GHz VNA measurements on dedicated test
sites).
Introduction
Models of on-chip coplanar single and coupled
transmission line (T-line) structures have been developed as
part of an interconnect-aware analog and mixed signal (AMS)
design methodology [1,3]. The methodology comprises of
identifying a relatively small number of critical interconnect
lines at early stages of the design flow, their modeling and
incorporation into the netlist as “on-chip transmission line
devices”. These on-chip T-line components are of predefined
topologies consisting of single and coupled microstrip and
coplanar structures [2,3]. Each topology is designed to meet
closed environment conditions [1-3], enabling high
predictability of the critical interconnect behavior. T-line
devices are supplied as parameterized schematic and layout
cells (Pcells), together with their simulation models, as an
integral part of given silicon chip technology design kit. DRC
(Design Rule Checking) and LVS (Layout Versus Schematic)
compliance is guaranteed by construction.
In this paper we focus on the general modeling
methodology for the coplanar on-chip T-line structures, which
is being constantly studied and developed.
General modeling considerations.
Each simulation model consists of a multisegment RLC
network, which captures the T-line behavior, by means of R(f),
L(f), C(f) and G(f) per unit length (shown in Fig. 1) in the full
bandwidth of interest, namely from DC till the cut-off
frequency of the transistors in the given chip technology for
which the models are provided. The advantages of this
approach over the "frequency domain plus convolution"
methods is in its inherent passivity, and the inherent
migratability between different circuit level simulation
environments. However, a comprehensive modeling
methodology is required for reliable building of these
Figure 1. General frequency dependent RLCG representation
of a transmission line. R(f) and L(f) form the Z element, while
C(f) and G(f) form the Y element.
"frequency dependent" multisegment RLC networks, as
outlined below. 20 repeated segments are practically used per
one on-chip wavelength at the cut-off frequency for obtaining
the desired waveform accuracy. Closed-form, semi-analytical
expressions are used for all the network parameters. Previous
work [3] shows that the influence of properly shielded
discontinuities (such as bends) may be neglected up to
110[GHz] in many practical cases. Model order reduction
techniques may be applied to further reduce the network
complexity, if needed.
The proposed modeling methodology is based on breaking
the electromagnetic problem into a serial problem (for
calculating R(f) and L(f) of Fig. 1, namely the Z element) and
a parallel problem (for calculating C(f) and G(f) of Fig. 1,
namely the Y element). This division, while known to be
possible for the case of low loss substrates, can be generalized
at certain conditions also for the case high loss silicon
substrates, as shown below.
Fig. 2 presents the cross-sections of the currently
supported coplanar line topologies, which include single and
two coupled wires. Structures are symmetrical and include
grounded side shield lines. One condition to be satisfied for
these structures is that the cross-sectional dimensions are two
orders of magnitude smaller than the shortest wavelength,
which is maintained in our structures even at 100GHz. The
second condition states that the coplanar structures are excited
in their proper designed mode, namely exciting the signal
line(s) with respect to the two side ground shielding lines. This
means that the two side shielding wires have the same ground
potential, and that most of the return current (namely the
longitudinal current, in the direction of the T-line) flows in the
side shielding wires rather than in the silicon substrate.
It follows from semi-analytical calculations that the return
current in the silicon substrate is negligible under almost all
practical conditions, even for the worst case of ideal contacts
between the ground metals and the silicon substrate at the near
and far ends of the coplanar structure (The on-chip coplanar
T-line structure does not contain in itself any substrate
contacts).
T-line case of Fig. 2b by considering the corresponding cross
(mutual) elements.
Modeling the serial (Z) element
The only requirement from the Z element network is to
reconstruct the physical R(f) and L(f) behavior throughout the
bandwidth of interest. This general physical behavior is given
in Fig. 3. At low frequencies, the current distribution in the
metal lines is uniform, namely the resistance of the T-line is
the Ohmic DC resistance (signal line + return path metals),
and the inductance per unit length is the low frequency limit
inductance, for which cost-effective expressions were
developed and reported in [2]. At the high frequency limit, the
inductance reaches the high frequency limit inductance L as
shown in Fig. 3. The resistance does not saturate at high
Figure 2. Cross-sections of the coplanar T-line
structures. Fig. 2a shows the single coplanar structure
while Fig. 2b shows the coupled coplanar structure.
frequencies, but approaches an asymptotic
f behavior.
The substrate return current may be significant only when the
skin depth in the silicon goes down to the order of the T-line
cross sectional dimensions – which usually happens only at
frequencies far beyond the practical range of interest. It is
shown in the conference slides supplement, that the frequency
at which we start to have a meaningful return path in the
silicon substrate (up to 10% of the overall current) for the
structure of Fig. 2a is (where w, s, t and h are defined in Fig. 2
and Si is the substrate resistivity):
Fc
2t
si
40
0
s
2
0.7 s ln(1 5 w s )
w 2( h t )
(1)
To illustrate this claim, let us consider an example of a Tline, and check under which conditions FC falls below 100
GHz. The T-line dimensions are: w=s=ws=6 m, t=0.3 m,
h=0.3 m. In accordance to Eq. 1, an FC below 100 GHz
implies that the silicon bulk resistivity is below 0.05 cm.
This value is far below what is used in practice. Full wave
HFSS simulations [4] verify that up to 50[GHz] the return
current is indeed negligible for a 1[Ohm cm] silicon substrate.
In the frequency range of interest, substrate effects
manifest themselves through transverse rather than
longitudinal currents, leading to signal attenuation and
frequency dependent capacitance. An adequate term for this
behavior would therefore be "transverse ground", namely the
existence of transverse currents and not longitudinal currents.
Accordingly, we may term FC as "transverse ground cut-off
frequency". Below this frequency, the finite resistivity and the
dielectric (polarization) properties of silicon affect the Y
element without affecting the Z element. This claim is
supported by HFSS simulations [4] showing that both R(f) and
L(f) plots, for the last worst case example, remain the same
from DC to 50 GHz when the silicon resistivity is changed
from 1 cm to 13.5 cm. We note that a similar approach
was used for lower bandwidths (up to 10 GHz) by Alina
Deutsch in [5].
Both the Y element and the Z element networks given in
the sections below were generalized for the coupled coplanar
Figure 3. Physical behavior of the Z element parameters
We define the transition frequency between the low and
high frequency regions of the Z element behavior as the skin
depth initial frequency, obtained by equating the skin depth to
a measure of the T-line cross sectional dimensions.
Ever since the Wheeler comprehensive network [6] for the
Z element, several networks have been published (references
are given in [1]). We have developed a different Z element
network given in Fig. 4, which has been found to be both costeffective and simple to use.
Figure 4. A proposed equivalent network for the Z element of
a transmission line.
The number of RL lumps being used depends on the
required bandwidth above the skin depth initial frequency.
The network parameters are calculated using the high and low
frequency asymptotic behavior of R(f) and L(f) and the
transition frequency FC, which are calculated independently. In
particular, the high frequency inductance matrix is calculated
using static capacitance matrix [7], which is obtained in
absence of silicon substrate. Though this "high frequency
limit" is beyond the transverse ground cut-off frequency FC,
this method of calculation is still correct provided that FC is
larger than the bandwidth of interest.
The practical necessity to model the Z element at the full
bandwidth given by Fig. 3 depends on the ratio between the
required bandwidth and the skin depth initial frequency. For
the upper wide and thick (large w and t) signal lines, the skin
depth initial frequency may be well below the transistors cutoff frequency, and the complete bandwidth of Fig. 3 should be
modeled by the Z element network. For lower bandwidths, a
lower order (less RL lumps) Z element network may be used.
Modeling the parallel (Y) element
In the simpler case of microstrip on-chip T-lines [1-3] with
metallic bottom shield, the Y element reduces to a constant
capacitance in the practical bandwidth of interest. This follows
since the inverse of the dielectric relaxation time constant in
the metals is much higher than the desired bandwidth, and the
cross sectional dimensions are much smaller than the shortest
wavelength. However, in the coplanar structures of Fig 2, the
silicon substrate may have a strong effect on the Y element. It
is assumed that the silicon substrate is "grounded at infinity",
namely that far away from the coplanar structure the potential
of the conducting silicon substrate is zero. This last condition
is what we have in practical designs, assuming the mandatory
existence of silicon substrate ground contacts, though in many
practical cases there is no back ground metallization contact
to the silicon substrate.
The only requirement from the Y element network is,
again, to reconstruct the physical C(f) and G(f) behavior
throughout the full bandwidth of interest. This general
physical behavior is described in Fig. 5. At low frequencies,
the silicon behaves like a perfectly grounded metal, yielding
the maximal static capacitance C(0)=C0 and zero losses. At the
high frequency limit, capacitance reaches its minimal value,
C( )=C , obtained by assuming that the silicon substrate
behaves as a perfect dielectric (zero conductivity). However,
the parallel conductance, which represents the T-line signal
loss due to the substrate, reaches its maximal value G( )=G .
Figure 5. Physical behavior of the Y element parameters.
The transition frequency between these low and high
frequency limits is the relaxation frequency, defined by:
Frel
si
2
si
(2)
Where si is the conductivity of silicon and si is its
dielectric constant.
Several Y element networks [8-10] have been given in the
literature for wires over silicon. We have developed a
generalized Y element network, shown in Fig. 6:
Figure 6. A proposed equivalent network for the Y element of
a transmission line.
This last network can be formally obtained for the
geometry of Fig. 2a, by integrating over the electric field flux
tubes flowing from the signal line to the side metallic ground
shielding, directly (forming the capacitance Coxo), or through
the silicon substrate (forming the 1..n GC lumps). Every such
GC lump in this network satisfies the relation:
Gsii
2 Frel Csii
(3)
By choosing proper element values, the general network of
Fig. 6 can describe the physical behavior of Fig. 5 within any
desired accuracy. The partial information of the exact Co, C
and G is sufficient to determine a first order Y element
network (n=1). Any additional value of {C(f),G(f)} at an
intermediate frequency f, allows to increase the order of the Y
element network by one. A simple way to further approximate
the first order Y element network is by using the full static
capacitance matrix (both the signal to metal shield and signal
to conducting substrate partial capacitances) to determine both
Coxo and Cox(= Cox1). The first order network still describes
the full bandwidth behavior of Fig. 5. A further simplification
is still possible, by eliminating Coxo or by eliminating Csi, but
with reduced accuracy.
It is important to note, that even if Frel is much higher than
the required bandwidth, there may be T-lines with dimensions,
for which both C and G vary significantly over the bandwidth
of interest.
Experimental results
A dedicated test site was designed with 4500 m long
coplanar and microstrip T-lines, and silicon substrate
resistivity of 1 to 2 cm. Agilent 8517 (2-port, 40 GHz) and
Agilent 8720ES (4-port, 20 GHz) Vector Network Analyzers
have been used for obtaining S-parameter data, making use of
on-chip structures de-embedding. Balanced 40 GHz coplanar
probes were used with SOLT calibration. On-chip T-line
models were simulated in S-parameter mode using the
SPECTRE simulator (assuming 1 cm silicon). Results are
shown in Fig. 7 for a single coplanar case (w=s=ws=5 m,
t=4 m, h=16 m) and in Fig. 8 for a coupled coplanar case
(w=d=ws=s=0.6 m, t=0.32 m, h=1.1 m) for differential
mode. A Fabry-Perot like resonant cavity is formed when the
non 50
T-lines are loaded on both sides by the 50
measurement equipment, leading to some inaccuracies in the
S11 phase plots around the resonance point, where the
amplitude of the reflected wave is minimal.
Acknowledgments
We would like to thank the IBM Burlington design
automation team (Youri V Tretiakov, Sue E Strang, Donald
Jordan, Raminderpal Singh, Carl Dickey, and David Harame)
our partners in the on-chip T-line project, for enabling the
models productization and countless helpful discussions. We
thank Jay Rascoe from IBM Burlington and Anastasia Barger
from IBM Haifa for performing the measurements. Many
thanks to Alina Deutsch from IBM Yorktown for her support
and numerous discussions. The Authors would like to thank
Dr. Avri Frenkel from Ansoft corporation for numerous
discussions and guidance while using HFSS for the
challenging coplanar over substrate problems.
Figure 7. Single coplanar T-line (Fig 2a) results. Solid:
40[GHz] VNA measurement, Dashed: T-line model.
Figure 8. Coupled coplanar T-line (Fig 2b) results. Solid:
20[GHz] 4-port VNA measurement (odd mode), Dashed: Tline model (odd mode).
Conclusions
Comprehensive modeling methodology for on-chip
transmission lines over a lossy substrate is presented. The
developed models represent frequency behavior of T-lines by
means of multisegment RLC scalable networks. The networks
allow for accuracy vs. computation efficiency trade-offs, while
maintaining correct asymptotic behavior at both high and low
frequency limits. In the frame of the model development, it
was shown that in most practical situations the substrate
longitudinal return currents are negligible, while the transverse
currents have a major effect on the T-line Y element
parameters. The model is compared by means of S-parameters
to hardware measurement results up to 40GHz. This modeling
methodology is being used for a large variety of silicon chip
technology design kits, while supporting all possible
metallization stack combinations.
References
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Methodology for Analog and Mixed Signal Design,
Based on High Bandwidth (Over 40 GHz) On-chip
Transmission Line Approach", DATE02, Paris 2002.
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Transmission Lines in High-Speed A&MS Design –
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Bandwidth Transmission Line Devices", will be
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