Copyright © 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on
Circuits and Systems, 27 - 30 May 2007. This material is posted here with permission of
the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of
any of Institute of Microelectronics’ products or services. Internal or personal use of this
material is permitted. However, permission to reprint/republish this material for
advertising or promotional purposes or for creating new collective works for resale or
redistribution must be obtained from the IEEE by writing to pubs-permission@ieee.org.
Low-Power Digitally Controlled CMOS Source
Follower Variable Attenuator
T. Hui Teo, Wooi Gan Yeoh
Institute of Microelectronics
Singapore
E-mail: teehui@ime.a-star.edu.sg
Abstract— A low-power source follower variable attenuator
(SFVA) is proposed and implemented using standard 0.18µm
CMOS. Using a PMOS source follower, a bandwidth of 200MHz
is achieved with 500µA current from a 1.8V single supply.
Accurate attenuation can be varied with a digital control signal.
Dc coupling at the input is made possible with a self-biasing
technique. A single stage SFVA with a 2-bit control is demonstrated for 0dB to 6dB attenuation. The number of control bit
and attenuation is expandable. The active area is merely 120µm
× 60µm which is very cost effective.
I. I NTRODUCTION
Gain control is required in the communication system to
achieve the optimum dynamic range, especially in wireless
transceiver, where power received at different distance can be
in the order of magnitude different. Accurate control is always
accomplished by automatic gain control (AGC). In AGC
loop, variable gain and attenuation circuit is needed. With
increasing driving force from high data rate and portability,
higher bandwidth of receiving and transmitting signal need to
be processed with low power. Thus, wide-band and low-power
AGC is required.
There are a few traditional ways of implementing variable
attenuator. Attenuator using resistive network is preferred if
a low input impedance is desired. However, if high input
impedance is required, a power hungry input buffer is normally employed. Variable attenuation of resistive network is
frequently achieved through digital switching [1]. Variant of
resistive network using FET transistor as resistor was also
reported [2]. Using this technique, analog and digital tuning
can be adopted. However, this circuit faces the same problem
of resistive network. To resolve the low input impedance problem in resistive network, source degeneration transconductance
cell can be used as variable attenuator [3]. In deep submicron CMOS, the ratio of transistor’s output impedance and
transconductance is much lower than that of the long channel
device’s. In this case, the attenuation accuracy is poor regardless high current is consumed to get a high transconductance.
At low frequency range, active-R variable attenuator using
operational-amplifier is preferred for its high accuracy and
ease of implementation [4]. The only drawback here is that
the bandwidth of active-R variable attenuator is very much
limited by the operational-amplifier bandwidth. The higher
the required bandwidth, the larger the power consumption for
the operational-amplifier is needed. In CMOS, the bandwidth
1-4244-0921-7/07 $25.00 © 2007 IEEE.
of the operational-amplifier is always limited by its low
transconductance. These prevent the usage of active-R variable
attenuator in low-power, wide-band applications.
In certain applications, such as ultra-wide-band (UWB) [5],
[6], wide IF bandwidth is required. For stringent low-power
applications, power hungry circuitries are not preferred. In
the circuit context, it is almost impossible to achieve lowpower, low-voltage, and wide-bandwidth at the same time. In
CMOS analog circuits, the only candidate that fulfills these
requirements is the source follower, which is normally used as
a buffer. Source follower has a high input impedance and a low
output impedance. Thus, it can achieve a very high bandwidth
with low power. In this work, we show the implementation of
a source follower as a variable attenuator that could achieve
low-power, low-voltage and wide-bandwidth performance simultaneously, [7].
This paper is organized as follow; basic theory and circuit
implementation of the SFVA are described in Section II. The
measured results are presented in Section III, which shows
the performance of the SFVA. Conclusion is then drawn in
Section IV.
Fig. 1.
Basic structure of the SFVA.
II. A NALYSIS A ND C IRCUIT I MPLEMENTATION
In this section, the fundamental idea of deriving the design
equation is given. Based on the design equation, the circuit
structure is then developed.
The basic structure of the SFVA is shown in Fig. 1. PMOS
version is used to illustrate the circuit concept only. The circuit
can be realized with NMOS which could definitely provide
wider bandwidth. The relationship of the input voltage and
229
output voltage in Fig. 1 can be simplified as,
Vout
Vin
=
Rk gm1M
2
Rk gm1M + gm1M
2
1
(1)
with gm and R are the transconductance of the input devices
and equivalent output impedance of the devices respectively.
If the equivalent output impedance is sufficiently large, (1) can
be approximated as,
Vout
Vin
≈
=
1
gmM2
+ gm1M
1
gmM1
.
gmM1 + gmM2
1
gmM2
(2)
Since both of the devices operate in the saturation region,
the transconductance is proportional to its aspect ratio, gm ∝
W
L . In summary, the attenuation of the SFVA can be expressed
in terms of device geometries as,
G =
(W
L )M1
W
( L )M1 + ( W
L )M2
(3)
with W
L is the aspect ratio for the input device M1 and control
device M2 . In this expression, it is assumed that the dc value
of Vin and Vbias are the same. Note that the attenuation is
process, temperature and supply independent. The accuracy is
mainly determined by the device matching.
control devices. Thus, the SFA can be dc coupled directly.
The usage of the RC filter also brings another advantage of
reducing the dc offset. The control devices are cross-coupled
to cancel the dc components from the input signal. If the SFVA
is to be used in a direct conversion transceiver, the RC filter
actually serves the two purposes above without trading off with
any other performances. Note that this self biasing circuit does
not consume any current. The RC can be easily implemented
with MOS resistor and MOS capacitor. The RC value is not
important at all as far as they provide an appropriate biasing.
The goal of this design is to provide a variable attenuation.
The attenuation can be achieved either with an analog or
a digital technique. In the analog technique, Vbias is varied to control the attenuation. In most modern AGC loop,
digital technique is preferred. Switches are thus introduced
for attenuation variation. The switches are controlled by the
digital signal. In this case, two differential SFVAs are also
proposed, as depicted in Fig. 3. The control switches, S1 and
S2 are used for attenuation control. The purpose of including
complementary switches, S1 and S2 , is to turn off the control
device when it is not in the attenuation control mode. This is
to improve the attenuation control accuracy and prevent the
signal feed-through through the switch since large incoming
signal is expected for most of the attenuator. The difference
of these two topologies is that the control switches are either
connected in series or parallel.
The attenuation of the differential SFVA is given by,
(W
L )M1p
G =
(W
L )M1p
(4)
N
X
W
+
Tx ·( )Mxn
L
x=1
Tx = 0, 1
x = 1, 2, 3, . . . N
with subscript x indicating the number of switches in the
SFVA. In the series switch implementation, attenuation control
of the second switch depends on the first one, but the attenuation control by parallel switches is independent of each other.
Thus, different combination of switches can be utilized for
various attenuation control.
Fig. 2.
TABLE I
T RANSISTOR SIZING OF 2- BIT SFVA
Basic differential structure of the SFVA.
In most of the integrated circuit implementation, differential circuit is more commonly used. A differential structure
of SFVA can be constructed as depicted in Fig. 2. In this
implementation, it is assumed that the dc bias is determined by
the previous stage which is the common application of source
follower. This actually poses a critical issue in the control
devices (M2p , M2n ) biasing. This is because the Vgs of the
input devices and control devices need to be the same. The
problem can be easily solved if ac coupling is adopted. Then
the biasing voltage of the input devices can be set by a voltage
biasing circuit. In other case, if dc coupling is desired, a lowpass RC filter is employed as shown in Fig. 2. The RC filter
extracts the dc value of the incoming signals and biases the
)
m( W
L
M1p , M1n
5.00
)
6( 0.18
M2p , M2n
)
4( 5.00
0.18
M3p , M3n
)
2( 5.00
0.18
III. M EASURED R ESULTS AND D ISCUSSION
In this section, a practical design of SFVA is given. The
performance of the SFVA is also evaluated to prove the design
concept described in Section II.
A SFVA with parallel switch control was implemented
in 0.18µm CMOS. For limited area constraint, only 2-bit
switches control were realized. The circuit in Fig. 4 is implemented. PMOS version of SFVA is implemented as a test
vehicle. Since NMOS has a higher speed behavior, higher
230
Fig. 4.
Differential SFVA with 2-bit control implemented with parallel
switches.
performance of the SFVA can be achieved if NMOS version is
implemented. The switches, resistor and capacitor are realized
with MOS switches, MOS resistors, and MOS capacitors.
The aspect ratios of the input and control devices are listed
in Table I. The devices are constructed based on a unit
transistor with a unit aspect ratio of 5.00/0.18. In this case,
the attenuation of the SFVA can be estimated directly from the
number of unit transistor. Matching of the devices is improved
using unit aspect ratio.
(a)
TABLE II
G AIN CONTROL OF 2- BIT SFVA
S2
0
0
1
1
0
1
0
1
Gain(dB)
Simulated Measured
-0.405
-0.4
-2.805
-2.8
-4.642
-4.6
-6.105
-6.0
IIP3
(dBm)
16.5
17.0
17.0
18.0
3dB Bandwidth
(MHz)
150
180
200
210
y = 60 µ m
S1
x = 115 µ m
(b)
Fig. 5.
Fig. 3. Differential SFA, (a) with series switches, (b) with parallel switches.
Snapshot of 2-bit SFVA core layout.
The measured gain control of the SFVA with respect to
the control switches is tabulated in Table II. Note that the
231
2
Magnitude, dB
simulated values are very well matched with the measured
ones. This indicates that the proposed circuit performs as
expected. The linearity of the SFVA is also measured with twotones in-band signals. It can be seen that very high linearity
is achieved. The SFVA also achieves a very high bandwidth
of more than 150MHz. It is driving 2pF capacitors in this
experiment. Although the SFVA achieves high linearity and
high bandwidth, it consumes about 500µA from a 1.8V supply
voltage includes the biasing circuitries. It is worth to mention
that this SFVA occupies a very small area of 120×60 µm2
only, as shown in Fig. 5. This active area is less than a typical
10kΩ on-chip resistor layout.
Fig. 6 shows the micro-photograph of the SFVA test chip
that includes an internal output buffer. The test chip is packaged with SOIC-8 for evaluation purpose. The core circuit
can be integrated into the AGC loop without output buffer.
The measured magnitude responses of the SFVA controlled
by the two switches are shown in Fig. 7. Due to the limitation
of the measurement setup, the measured frequency responses
are degraded by the both the internal and external buffer.
The external buffer are required to drive a 50Ω matched
equipment. The cut-off frequencies are indirectly estimated
from the measured results and verified with simulation. The
pass-band attenuation has been summarized in Table II.
The overall performance and characteristics of the SFVA
are tabulated in Table III. Note that the SFVA can actually
achieve high performances with low power and only occupies
a small active area.
0
S2 S1 = 00
-2
S2 S1 = 01
-4
S2 S1 = 10
-6
-8
1M
Fig. 7.
S2 S1 = 11
10M
Frequency, Hz
100M
Measured frequency response of the 2-bit SFVA.
IV. C ONCLUSION
A low-power, low-voltage, wide-band, and small-area variable attenuator is proposed and implemented in a low-cost
0.18µm CMOS technology. Similar circuit structure can be
implemented using an emitter follower. Thus, the proposed
circuit is not limited to CMOS implementation only. Based
on these characteristics, this SFVA can serve as a high
performance general purpose variable attenuator. AGC loops
can easily adopt this SFVA in its gain control path.
ACKNOWLEDGMENT
The authors would like to thank Integrated Circuits and
Systems Laboratory staff for various support and technical
discussion. The authors would also like to thank Dr. Wong
King Wah for invaluable input in manuscript preparation.
R EFERENCES
Fig. 6.
Micro-photograph of the 2-bit SFVA test chip.
TABLE III
M EASURED PERFORMANCE SUMMARY OF 2- BIT SFVA
Technology
Supply Voltage
Drain Current
Active Area
3-dB Bandwidth
IIP3
Attenuation
(2 bits)
0.18µm CMOS
1.8V
500µA
120µm ×60µm
150MHz to 210MHz
16dBm
0dB to 6dB
[1] O. Kobayashi and K. Gotoh, “Variable attenuator for attenuating gain of
analog signal in accordance with digital signal,” U.S. Patent 5 351 030A,
September 27, 1994.
[2] D. A. Fisher and D. M. Dobkin, “A temperature-compensated linearizing
technique for mmic attenuators utilizing gaas mesfets as voltage-variable
resistors,” IEEE MTT-S International Microwave Symposium Digest, pp.
781–784, May 1990.
[3] J. J. F. Rijns, “CMOS low-distortion high-frequency variable-gain amplifier,” IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 1029–1034,
1996.
[4] H. W. Urayasu and K. F. Narashino, “Variable gain amplifier circuit and
attenuator circuit,” U.S. Patent 6 137 365, October 24, 2000.
[5] R. Roovers, D. M. W. Leenaerts, J. Bergervoet, K. S. Harish, v. d. R.
C. H. Beek, G. van der Weide, H. Waite, Y. F. Zhang, S. Aggarwal, and
C. Razzell, “An interference-robust receiver for ultra-wideband radio in
SiGe BiCMOS technology,” IEEE Journal of Solid-State Circuits, vol. 40,
no. 12, pp. 2563–2572, December 2005.
[6] T. H. Teo, M. A. Arasu, W. G. Yeoh, and M. Itoh, “A 90nm CMOS
variable-gain amplifier and RSSI design for wide-band wireless network
application,” Proceedings of the 32nd European Solid-State Circuit
Conference (ESSCIRC 2006), pp. 86–89, September 2006.
[7] T. H. Teo, “Source follower variable attenuator,” Patent filing.
232