Product Specification
IXD5118
Voltage Detector with Sense Input and Adjustable Delay
FEATURES










DESCRIPTION
Accuracy ± 2% at VDF ≥ 1.5 V or ±0.03 V
Low Power Consumption
0.4 μA (Detect at VIN = 1.0 V)
0.6 µA (Release at VIN = 1.0 V)
Detect Voltage Range 0.8 V – 5.0 V in 0.1 V
increments
Operating Voltage Range 1.0 V – 6.0 V
0
Detect Voltage Temperature Drift ±100 ppm/ C
Output Configuration CMOS (Version C) or Nchannel Open Drain (N Version)
Adjustable Release Time
0
Operating Ambient Temperature - 40 + 85 C
Packages : USP-4 and SOT-25
EU RoHS Compliant, Pb Free
The IXD5118 are highly precise, low power
consumption,
CMOS
voltage
detectors,
manufactured using laser trimming technology.
Separated sense input allows the IXD5118 to monitor
other voltage source and maintain the state of
detection even if sense voltage falls to zero.
The external capacitor connected to the CD pin allows
adjusting of release delay time in a wide range.
With low power consumption and high accuracy, this
series is suitable for precision mobile equipment.
The IXD5118 in ultra small packages are ideally
suited for high-density PC boards.
The IXD5118 is available in both CMOS and Nchannel open drain output configurations.
This detector is available in USP-4 and SOT-25
packages.
APPLICATIONS





Microprocessor reset circuitry
Memory battery back-up circuits
Power-on reset circuits
Power failure detection
System battery life and charge voltage monitors
TYPICAL APPLICATION CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTIC
Output Voltage vs. Sense Voltage
IXD5118C25AGR
Ta = 250C
Pull-up
PS037301-0615
Resistor RPL used with N-channel output configuaration only
PRELIMINARY
1
Product Specification
IXD5118
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input Voltage
Output Current
CMOS Output
Output
Voltage
N-channel Open Drain
Sense Pin Voltage
CD Pin Voltage
CD Pin Current
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
SYMBOL
VIN
IOUT
RATINGS
– 0.3 ~ +7.0
10
– 0.3 ~ VIN + 0.3
– 0.3 ~ +7.0
– 0.3 ~ +7.0
– 0.3 ~ VIN + 0.3
5.0
120
250
– 40 ~ + 85
– 55 ~ +125
VOUT
VSEN
VCD
ICD
PD
TOPR
TSTG
UNITS
V
mA
V
V
V
mA
mW
0
C
C
0
All voltages are in respect to VSS
ELECTRICAL OPERATING CHARACTERISTICS
Ta = 25 0C
PARAMETER
SYMBOL
Operating Voltage
Detect Voltage
VIN
VDF
Hysteresis Width
VHYS
Detect Voltage Line
Regulation
CONDITIONS
ISS1
VSEN = VDF x 0.9
Supply Current23)
ISS2
VSEN = VDF x 1.1
IOUT1
Output Current
IOUT24)
Detect Voltage
Temperature
Characteristics
Sense Pin Resistance
Delay Pin Resistance
CD Pin Sink Current
CD Pin Threshold
Voltage
Undefined Operation
Detect Delay Time8)
Release Delay Time9)
ILEAK
VSEN = 0 V, VDS = 0.5 V
N-channel MOSFET
VSEN = 6.0 V, VDS = 0.5 V
P-channel MOSFET
IXD5118Cxxx
(P-channel)
IXD5118Nxxx
(N-channel)
VTCD
VUND4, 7)
tDF0
tDR0
MAX.
UNIT
CIRCUIT
6.0
V
V
V


%/V

µA

µA

mA

mA

µA

ppm/0C

MΩ
MΩ
µA



V

V
µs
µs



E-12)
E-22)
E-3
±0.1
VIN = 1.0 V,
VIN = 6.0 V
VIN = 1.0 V,
VIN = 6.0 V
VIN = 1.0 V
VIN = 2.0 V
VIN = 3.0 V
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
VIN = 1.0 V
VIN = 6.0 V
VSEN = VOUT = 0 V,
VIN = 6.0 V, CD - open
VSEN = VOUT = 6.0 V,
VIN = 6.0 V, CD - open
0.1
0.8
1.2
1.6
1.8
1.9
0.4
0.4
0.8
0.9
0.7
1.6
2.0
2.3
2.4
2.5
-0.30
-1.0
1.0
1.0
1.6
1.8
-0.08
-0.70
-0.20
0.20
- 40 0C ≤ TOPR ≤ 85 0C
RSEN5)
RDEL6)
ICD
TYP.
1.0
VIN = 1.0 – 6.0 V
Supply Current13)
Leakage Current
MIN.
VDF(T) = 0.8 – 5.0 V1)
VIN = 1.0 – 6.0 V
IXD5118xxxA
VIN = 1.0 – 6.0 V
IXD5118xxxB
0.40
± 100
VSEN = 6.0 V, VIN = 0 V
VSEN = 6.0 V, VIN = 5.0 V, VCD = 0 V
VIN = 1.0 V, VCD = 0.5 V
VSEN = 6.0 V, VIN = 1.0 V
VSEN = 6.0 V, VIN = 6.0 V
VSEN = VIN = 0  1.0 V
VIN = 6.0 V, VSEN = 6.0  0 V, CD - open
VIN = 6.0 V, VSEN = 0  6.0 V, CD - open
1.6
0.4
2.9
E-4
2.0
200
0.5
3.0
0.3
30
30
2.4
0.6
3.1
0.4
230
200
NOTE:
1)
2)
3)
4)
5)
6)
VDF(T) is a nominal detect voltage
Please refer to the table named Voltage Chart
Current to the sense resistor is not included
IXD5118C version only
It is calculated from the voltage value and the current value
of the VSEN
It is calculated from the voltage value of the VIN and the
current value of the CD pin
PS037301-0615
PRELIMINARY
7)
8)
9)
Maximum VOUT voltage at VIN rising from 0V to 1.0V with the
VIN pin connected to the VSEN pin
Delay time from the moment, when VSEN = VDF to the
moment, when VOUT = 0.6 V, at VSEN falling
Delay time from the moment, when VSEN = VDF + VHYS to the
moment, when VOUT = 5.4 V at VSEN rising
2
Product Specification
IXD5118
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED)
Voltage Chart
SYMBOL
NOMINAL
VOLTAGE
VDF(T)
(V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
E-11)
E-2
E-3
E-4
DETECT VOLTAGE (V)
HYSTERESIS RANGE (V)
HYSTERESIS RANGE (V)
SENSE RESISTANCE (MΩ)
VDF
VHYS
VHYS
MIN.
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.312
4.410
4.508
4.606
4.704
4.802
4.900
MAX.
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
MIN.
0.015
0.017
0.019
0.021
0.023
0.025
0.027
0.029
0.031
0.033
0.035
0.037
0.039
0.041
0.043
0.045
0.047
0.049
0.051
0.053
0.055
0.057
0.059
0.061
0.063
0.065
0.067
0.069
0.071
0.073
0.074
0.076
0.078
0.080
0.082
0.084
0.086
0.088
0.090
0.092
0.094
0.096
0.098
MAX.
0.066
0.074
0.082
0.090
0.098
0.106
0.114
0.122
0.131
0.085
0.147
0.155
0.163
0.171
0.180
0.188
0.196
0.204
0.212
0.220
0.228
0.237
0.245
0.253
0.261
0.269
0.277
0.286
0.294
0.302
0.310
0.318
0.326
0.335
0.343
0.351
0.359
0.367
0.375
0.384
0.392
0.400
0.408
MIN.
0
RSEN
MAX.
0.008
0.009
0.010
0.011
0.012
0.013
0.014
0.015
0.016
0.017
0.018
0.019
0.020
0.021
0.022
0.023
0.024
0.026
0.027
0.028
0.029
0.030
0.031
0.032
0.033
0.034
0.035
0.036
0.037
0.038
0.039
0.040
0.041
0.042
0.043
0.044
0.045
0.046
0.047
0.048
0.049
0.050
0.051
MIN.
TYP.
10
20
13
24
15
28
NOTE:
1)
When VDF(T) ≤ 1.4 V, the detection accuracy is ±30mV; when VDF(T) ≥ 1.5 V, the detection accuracy is ±2%.
PS037301-0615
PRELIMINARY
3
Product Specification
IXD5118
PIN CONFIGURATION
USP-4
(BOTTOM VIEW)
SOT-25
(TOP VIEW)
PIN ASSIGNMENT
PIN NUMBER
SSOT-24
USP-4
1
1
5
2
4
3
3
4
2
5
PIN NAME
VOUT
CD
VSEN
VIN
VSS
FUNCTIONS
Output Voltage (Detect “LOW”)
Delay Capacitor Connection
Sense Voltage Input
Power Input
Ground (USP-4 uses power dissipation pin as a Ground pin)
BLOCK DIAGRAMS
IXD5118CxxA
IXD5118NxxA
IXD5118CxxB
IXD5118NxxB
Diodes inside the circuits are ESD protection diodes and parasitic diodes.
PS037301-0615
PRELIMINARY
4
Product Specification
IXD5118
BASIC OPERATION
Operation of the IXD5118 in a typical application circuit is exlained by the timing diagram shown below.
 At initial state, the sufficiently high voltage (6.0 V MAX.) applies to the sense pin, and the delay capacitor CD is
charged to the power supply input voltage (1.0V ≤ VIN ≤ 6.0 V). While the sense pin voltage (VSEN) starts
dropping, the output voltage VOUT remains at “High” level equal VIN as long, as the detect voltage VSEN > VDF .
(Output voltage “High” level is equal pull-up voltage for IXD518N version.)
 The sense pin voltage keeps dropping and becomes equal to the detect voltage (V SEN =VDF), Comparator (see
Block Diagram) trips, a N-channel transistor M1 turns ON, discharging the delay capacitor CD, and the output
voltage changes state to the “Low” level, equal VSS.
The detect delay time tDF is defined as time from the moment, when VSEN = VDF to the moment, when VOUT
changes state to “Low” level (tDF0, when the CD pin is open).
 The output voltage maintains at the “Low” level as long as the sense pin voltage is below the release voltage
(VSEN< VDF +VHYS), and the delay capacitor CD remains discharged to the ground voltage level.
 When the sense pin voltage increases to the release voltage level (VSEN = VDF + VHYS), the N-channel transistor
M1 turns OFF, and the delay capacitor CD start charging via a delay resistor RDEL.
 The CD pin voltage (VCD) continues rising up to the CD pin threshold voltage (VTCD), because the sense pin
voltage is higher than the release voltage.
The time constant of the CD pin voltage is  = RDELCD, so the Release Delay Time (tDR) can be determined as
tDR = -RDEL × CD × ln(1-VTCD/VIN) …(1)
The Release Delay time can also be calculated with the formula (2), because RDEL = 2.0 MΩ (TYP.) and the
delay CD pin threshold voltage is VIN /2 (TYP.)
tDR = RDEL × CD × 0.69 …(2)
As an example, presuming that the delay capacitance is 0.68 μF, tDR is :
6
-6
tDR =2.0 ×10 ×0.68 ×10 ×0.69 = 938 (ms)
Note that the release delay time may be remarkably short, if the delay capacitor CD did not discharge to the
ground (VSS) level, because of short time in state .
 When the CD pin voltage reaches threshold level (VCD = VTCD), the inverter will change state of the output. As a
result, the output voltage changes into the “High” (VIN) state.
 While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitor charges up to the
input voltage level. The output voltage maintains the “High” level equal VIN.
PS037301-0615
PRELIMINARY
5
Product Specification
IXD5118
Function Chart
VSEN
STATE
L
H
CD
STATE
Any
State
L
H
Any
State
Release Delay Time Chart
1)
VOUT TRANSITION


Any
L

State
L

L

H
H

1) VOUT state is a function of VSEN and CD pins state.
VIN should be above minimum operating value.
DELAY CAPACITANCE
RELEASE DELAY
CD, μF
TIME tDR (TYP.), ms
0.010
13.8
0.022
30.4
0.047
64.9
0.100
138
0.220
304
0.470
649
1.000
1380
Delay time is calculated using equation (2)
TYPICAL
CIRCUIT
RELEASE DELAY TIME
tDR (MIN. ~ MAX.), ms
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243 ~ 364
519 ~ 778
1100 ~ 1660
APPLICATION
IXD5118C
IXD5118N
LAYOUT AND USE CONSIDERATIONS
1. The IC may malfunction if absolute maximum ratings are exceeded.
2.
3.
4.
5.
6.
7.
High impedance VIN power supply may cause IC malfunction, if VIN voltage falls below minimum operating level due
current consumption, when IC output changes state. In addition, V OUT voltage at “High” state reflects every variations of
VIN voltage.
High impedance VIN power supply may cause IC oscillations, if VIN and VSEN pins are tied together and voltage drop at
power supply’s internal resistance exceeds IC hysteresis.
If VSEN threshold voltage is less than 1.0 V, VIN and VSEN pins should be separated, and VIN pin powered from power
supply with voltage equal or above 1.0 V
Note that a rapid and high amplitude fluctuation of the VIN pin voltage, as well as a power supply noise, may cause a
wrong IC operation. The capacitor between VIN and GND pins should be used to minimize noise impact.
When there is a possibility that VIN pin voltage may fall faster than CD capacitor’s discharge time, a Schottky barrier
diode connected between the VIN and the CD pins should be used to prevent IC damage (see the Typical Application
Schematic above).
VOUT voltage In N channel open drain configuration depends on pull-up resistance, as well as on/off resistance of the
M3 MOSFET (see block diagrams above).
During detection, VOUT = VPULL / (1 + RPULL / RON), where VPULL is a pull up voltage and RON is a M3 on-resistance,
which can be calculated as VDS / IOUT1 from electrical characteristics.
For example:
-3
To get VOUT ≤ 0.1V at detect state, with RON = 0.5/0.8×10 = 625 Ω (max) at VIN = 2.0 V and VPULL = 3.0 V, pull-up
resistor value should be
RPULL = (VPULL /VOUT - 1) × RON= (3 / 0.1-1) × 625 ≥ 18 kΩ .
Note that decreasing VIN voltage increases RON resistance, so minimum expected VIN voltage should be used for
calculations..
At releasing state VOUT = VPULL/(1 + RPULL / ROFF), where ROFF = VOUT/ILEAK = 15 MΩ (min) for M3 in off state.
Therefore, in this case, pull-up resistor should be
6
RPULL = (VPULL/VOUT-1) × ROFF = (3/2.99 - 1) × 15 × 10 ≤ 50 kΩ
to get VOUT ≥ 2.99 V at VPULL = 3.0 V.
PS037301-0615
PRELIMINARY
6
Product Specification
IXD5118
TEST CIRCUITS
Circuit 
Circuit 
Circuit 
Circuit 
Circuit 
Circuit 
Circuit 
Circuit 
Circuit 
Pull-up Resistor RPL = 100 kΩ is used for IXD5118N version only
PS037301-0615
PRELIMINARY
7
Product Specification
IXD5118
TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Input Voltage
IXD5118C25Ax
IXD5118C25Ax
VSEN = 2.25 V
VSEN = 2.75 V
(2) Supply Current vs. Sense Voltage
(3) Detect Voltage vs. Ambient Temperature
IXD5118C25Ax
IXD5118C25Ax
VIN = 3.0 V
VIN = 4.0 V
(4) Detect Voltage vs. Input Voltage
IXD5118C25Ax
(5) Hysteresis Voltage vs. Ambient Temperature
IXD5118C25Ax
VIN = 4.0 V
PS037301-0615
PRELIMINARY
8
Product Specification
IXD5118
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(6) CD Pin Sink Current vs Input Voltage
IXD5118C25Ax
VSEN = 0 V, VDS = 0.5 V
(8) Output Voltage vs. Input Voltage
(7) Output Voltage vs. Sense Voltage
IXD5118C25Ax
Ta = 250C
(9) Delay Resistance vs. Ambient Temperature
IXD5118C25Ax
IXD5118C25Ax
VIN = VSEN = VPULL, RPULL = 100 kΩ
VSEN = 6.0 V, VCD = 0 V, VIN = 5.0 V
(10) Output Current vs. Input Voltage
IXD5118C25Ax
IXD5118C25Ax
VDS = 0.5 V (N-channel)
VDS = 0.5 V (P-channel)
PS037301-0615
PRELIMINARY
9
Product Specification
IXD5118
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(11) Release Delay Time vs Delay Capacitance
(12) Detect Delay Time vs. Delay Capacitance
IXD5118C25Ax
IXD5118C25Ax
Ta = 250C
Ta = 250C
(13) Leakage Current vs. Ambient Temperature
(14) Leakage Current vs. Supply Voltage
IXD5118C25Ax
IXD5118C25Ax
VIN = VSEN = 6.0 V, VOUT = 6.0 V
VIN = VSEN = 6.0 V
ORDERING INFORMATION
IXD5118-
DESIGNATOR

DESCRIPTION
Output Configuration

Detect Voltage (VDF)

Options
-(*)
Packages
(Order Unit)
SYMBOL
C
N
08 - 50
DESCRIPTION
CMOS output
N-channel open drain output
Detect Voltage Range: 1.0 V～5.0 V, e.g. 1.2 V -  = 1,  = 2
A
Hysteresis 5%
B
Hysteresis < 1%
GR-G
USP-4 (3000/Reel)
MR-G
SOT-25 (3000/Reel)
NOTE:
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.
PS037301-0615
PRELIMINARY
10
Product Specification
IXD5118
PACKAGE DRAWING AND DIMENSIONS
USP-4, Units: mm
SOT-25, Units: mm
USP-4 Reference Pattern Layout, Units: mm
USP-4 Reference Metal Mask Design
PS037301-0615
PRELIMINARY
11
Product Specification
IXD5118
MARKING
SOT-25, USP-4
 Represents output configuration and integer number of the detect
MARK
L
M
N
P
R
S
IXD5118C
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
MARK
T
U
V
X
Y
Z
voltage range
IXD5118N
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
SOT-25 (Top View)
 Represents decimal number of the detect voltage
MARK
DETECT
VOLTAGE (V)
PRODUCT SERIES
3
0
x.3
x.0
IXD5118xx3xxx
IXD5118xx0xxx
USP-4 (Top View)
Represents options
MARK
OPTIONS
A
B
Built-in delay capacitance pin with hysteresis 5% (TYP.)
Built-in delay capacitance pin with hysteresis less than 1%
PRODUCT SERIES
IXD5118xxAxx
IXD5118xxBxx
 Represents production lot number
01 to 09, 10, 11, …, 99, 0A, …, 0Z, 1A, …repeated.(G, I, J, O, Q, W excluded)
PS037301-0615
PRELIMINARY
12
Product Specification
IXD5118
Customer Support
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Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN
APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
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Document Disclaimer ©2015 Zilog, Inc. All rights reserved. Information in this publication concerning the
devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
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OTHERWISE. The information contained within this document has been verified according to the general
principles of electrical and mechanical engineering.
PS037301-0615
PRELIMINARY
13