Emitter-Coupled Spin-Transistor Logic
Joseph S. Friedman1, Yehea I. Ismail1, Gokhan Memik1, Alan V. Sahakian1, and Bruce W. Wessels1,2
1
Department of Electrical Engineering & Computer Science
2
Department of Materials Science & Engineering
Northwestern University
Evanston, IL USA
Abstract²The recent invention of magnetoresistive bipolar spintransistors makes possible the creation of new spintronic logic
families. Here we propose the first logic family exploiting these
spin-transistors, extending emitter-coupled logic (ECL) to
achieve a greater range of basis logic functions. By placing the
wire from the output stage of ECL logic elements near spintransistors in other parts of a circuit, additional basis logic
elements can be realized. These new logic elements support
greater logic minimization, resulting in enhanced speed, area,
and power characteristics. A novel magnetic shielding structure
provides this logic family with the crucial ability to cascade logic
stages. This logic family achieves a power-delay product 10 to 25
times smaller than conventional ECL, and can therefore be
exploited to increase the performance of very high-speed circuits
while broadening the range of design choices for a variety of
electronic applications.
I.
INTRODUCTION
The ability to switch a logic gate through control of electron
spin is the fundamental concept underlying spintronic logic
circuits. By using electron spin along with charge, new
avenues for manipulating signal flow become available [1]. It
is therefore possible to develop logic devices with additional
capabilities that are more efficient, leading to logic circuits
with improved characteristics [2]. In this paper we present a
very high-speed logic family exploiting a newly developed
spintronic switch. The power dissipation of circuits made from
this logic family is nearly independent of frequency, providing
an advantage over CMOS for very high-speed applications.
While electron spin has found a ready application for
computing in memory structures such as hard drives and
magnetoresistive random-access memory (MRAM), the
difficulty in cascading these devices has prevented its
incorporation in logic structures. With the exception of the
spin-diode logic family presented by the authors [3], the
capability of driving the input of one spin-based logic gate
with the output of a second spin-based logic gate has not been
shown without requiring additional control logic. This ability
to cascade gates is a fundamental requirement of logic circuits,
and is a primary challenge for spin-based logic.
Originally, Datta and Das proposed a field effect transistor
in which a gate voltage controls the spin-precession of
electrons moving between the source and drain [4]. This work
inspired the utilization of the spin degree of freedom, resulting
in several distinct techniques. One prominent technique uses a
current-carrying wire to create a magnetic field in a twoterminal device to switch between a conductive and resistive
Figure 1. Power dissipation of emitter-coupled spin-transistor logic
(ECSTL) is less than CMOS at high frequencies and ECL at all
frequencies.
state. This technique has been suggested for logic based on
magnetic tunnel junctions [5], [6] and magnetoresistive
semiconductor heterojunctions [3], and is currently in use for
MRAM [7], [8]. Magnetic quantum cellular automata logic, in
which localized spin states are used to control nearby spin
states [9], [10], and magnetic domain-wall logic, in which a
rotating magnetic field induces motion of magnetic domains in
nanowires [11], are alternative techniques that have been
demonstrated in circuits at room temperature. Logic based on
spin accumulation [12], spin-wave phase [13], and spin-torque
[14], [15], have also been proposed.
The recent invention of the magnetoresistive
semiconductor heterojunction bipolar spin-transistor makes
possible a new class of logic families [16]. As a three-terminal
device designed for large signal amplification, the ability to
exploit spin as an additional control allows for the
modification and improvement of existing logic families.
Emitter-coupled logic (ECL), a bipolar family used in very
high-speed electronics, can be modified and improved using
spin-transistors. Circuits designed with ECL and our new
ECL-based logic family dissipate minimal dynamic power,
causing the power dissipation to be nearly frequencyindependent. This is in contrast to CMOS circuits, in which
dynamic power dissipation increases proportionally with
frequency, as depicted in Fig. 1. The power dissipation of the
emitter-coupled spin-transistor logic family is significantly
c 2012 IEEE/ACM NANOARCH 2012 139
978-1-4503-1671-2 less than ECL across all frequencies. This causes a leftward
shift in the frequency at which the two design styles intersect,
making this logic family an effective technology for highspeed applications.
The improved characteristics of this logic family are
derived from exploiting the magnetic characteristics of the
spin-transistors. We have constructed emitter-coupled spintransistor logic circuits by routing the ECL differential
amplifier currents to create magnetic fields that control the
state of spin-transistors. This technique reduces current
consumption, and allows for the logic stages to be cascaded
similarly to conventional ECL circuits. The number of stages
and devices required to implement logic functions is
decreased, producing logic circuits that are superior in terms
of speed, power, and area without any significant tradeoffs. In
summary, the contributions of this work are:
x the first logic family based on magnetoresistive
semiconductor heterojunction spin-transistors,
x a spintronic logic family with cascadable stages using
a high-permeability shielding material to concentrate
a magnetic field, and
x the first logic family based on high-speed ECL
structures making use of the spin-degree of freedom.
The rest of the paper is organized as follows. The operation
of the spin-transistor is discussed in Section II and our novel
logic family is explained in Section III. In Section IV, the
logic family is evaluated, and the paper is concluded in
Section V.
II.
MAGNETORESISTIVE SPIN-TRANSISTOR
A magnetoresistive spin-transistor is produced by doping a
bipolar junction transistor (BJT) with an element such as Mn
that has a strong interaction with a magnetic field. In this
semiconductor heterojunction structure, shown as part of Fig.
2, Mn is added to the emitter of the pnp transistor. The
collector-base junction functions conventionally, while the
emitter-base junction behaves similarly to a magnetoresistive
p-n junction [17]. Therefore, the gain of the magnetic
transistor decreases with increasing magnetic field.
A. Spin-Transistor Operation
Standard BJTs are characterized by two connected p-n
junctions sharing a cathode or anode, forming, respectively, a
pnp or npn transistor. The relative voltages on the three
terminals determine the bias of the two internal diodes, and
therefore the region of operation of the transistor. When the
base-emitter junction is forward-biased, a large current flows
across this junction, which proceeds across the base-collector
junction. In conventional ECL circuits, the base-emitter
junction switches between forward and reverse bias, while the
base-collector junction always remains under reverse bias. The
transistor therefore switches between the cut-off and forwardactive regions, which are characterized by low and high
collector currents, respectively. The transistor is never
saturated, which contributes to the exceptional speed of ECL
circuits [18].
140
Figure 2. Magnetoresistive spin-transistor with Mn-doped emitter, control
wires, and high-permeability mu-metal shielding.
The pnp spin-transistor [16] is composed of III-V
semiconductor compounds with Mn-doping in the emitter. In
the presence of a magnetic field, the base-emitter junction
becomes resistive, preventing current from flowing across the
junction [19]. Therefore, in the presence of a magnetic field, a
forward-biased base-emitter junction in the spin-transistor will
behave similarly to a reverse-biased base-emitter junction in a
conventional BJT. In both cases, the transistor will not produce
large currents, and will remain cut-off rather than in the
forward-active region. A more thorough discussion of the
effect of a magnetic field on a spin-transistor can be found
elsewhere [20]. The spin-transistor has the additional
outstanding feature of a large magnetoresistance at room
temperature.
B. Control Wires
The spin-transistor can be selectively controlled by
adjacent wires, thus adding additional logical inputs. As we
suggest in Fig. 2, two control wires can be placed near the
spin-transistor, creating a magnetic field in the plane
perpendicular to the current. A high-permeability material
surrounds the wires, shielding the rest of the circuit from the
magnetic field while simultaneously amplifying the field
within the high-permeability material. The gap in the shield
results in the concentrated field penetrating the spin-transistor,
inducing sufficient magnetization within the emitter to make
the base-emitter junction highly resistive.
In a mechanism similar to that exploited by spin-diode logic
[3], the flow of current through the control wire can cause the
spin-transistor to switch from the forward-active to the cut-off
region. When there is no (or minimal) current through the
control wires, or if there are equal and opposite currents, the
spin-transistor behaves as a standard transistor, and its region
of operation is dependent on its bias conditions. If exactly one
wire carries current, or if the two wires carry current in the
same direction, the spin-transistor will be cut-off.
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
III.
EMITTER-COUPLED SPIN-TRANSISTOR LOGIC
The capabilities provided by this new spin-transistor merit a
reconsideration of BJT-based computing. Many logic families
have been invented that utilize BJTs. Each logic family has a
unique set of advantages and tradeoffs, and the choice of logic
family is therefore dependent on application-specific
requirements. In particular, ECL consumes a relatively large
amount of power, but its small delay time makes it useful for
very high-speed applications [18]. Transistor-transistor logic
(TTL), in contrast, is slower and uses less power than ECL,
and is therefore more useful for general-purpose computing.
However, TTL has been made largely obsolete by the superior
characteristics of CMOS circuits while ECL is preferred over
CMOS for very high-speed applications [21].
The recently developed spin-transistors provide new
opportunities for BJT logic families, particularly ECL. By
replacing traditional BJTs with spin-transistors, a new logic
family is created that can perform additional functions without
adding any transistors, thus increasing the efficiency of the
computing system. These new functions reduce the number of
transistors required in a circuit, thereby lowering the area,
power, and signal delay. These new functions come with no
tradeoffs; the only required change is a new set of rules for
routing the wires.
A fundamental difference from CMOS is that large currents
flow in ECL circuits during the static propagation of logical
signals. While this characteristic is an issue in terms of power
dissipation, it makes ECL quite suitable for exploiting the
potential of spin-transistors. By carefully routing a wire whose
current varies according to the logical state, it is possible to
realize more complex logical functions without adding any
additional circuitry.
A. Basis Logic Functions
The fundamental building block of ECL, as well as our
ECL-based logic family, is the differential amplifier shown in
Fig. 3. In this circuit, one transistor always operates in the
active region and the other transistor is in the cut-off region.
The relative base voltage of the two transistors determines
their state. As we have used pnp transistors, the transistor with
Figure 3. Differential amplifier with pnp transistors.
Figure 4. ECL basis logic gate with pnp transistors.
a lower base voltage is in the active region, and the transistor
with the higher base voltage is in the cut-off region. If Q1 is
cut off and Q2 is in the active region, greater current passes
through Q2 and R2 than Q1 and R1. There is therefore a
greater voltage drop across R2 than R1, resulting in a high
output voltage at V2 and a low output voltage at V1.
This differential amplifier is used with multiple inputs to
form the ECL circuits. The logical gate that can be
implemented with the fewest pnp transistors is an
AND/NAND gate, which therefore serves as the basis ECL
function. This gate, shown in Fig. 4, accepts two (or more)
inputs, and produces two outputs, the logical AND and ŃAND
of the inputs. The gate functions as follows: the base of the
reference transistor QR is held at a constant voltage VR which
ensures that QR will switch between the active and cut-off
regions depending on the behavior of the rest of the circuit. If
either or both of the inputs are '0', the corresponding input
transistor Q1 or Q2 is in the active region, and QR is cut-off.
There is therefore a large current through R IN and a small
current through RREF, causing, respectively, large and small
voltage drops across those resistors. Therefore, the ŃAND
output is '1' and the AND output is '0'. If both inputs are '1',
QR is in the active region and both Q1 and Q2 are cut-off,
resulting in an AND output of '1' and ŃAND output of '0'.
Figure 5. Emitter-coupled spin-transistor basis logic gate with two control
wires for each transistor.
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
141
Figure 6. (a) 2:1 multiplexer and (b) 4:1 multiplexer implemented with emitter-coupled spin-transistor logic.
We route the current through RIN or RREF near a spintransistor, as discussed in Section II.B, to create an additional
control signal for the spin-transistor. The general basis circuit
using this scheme is shown in Fig. 5, with two control wires
for each spin-transistor, with directions arbitrarily chosen.
There are thus two voltage inputs and six current inputs for a
total of eight inputs. The presence of a net current through the
control wires forces the spin-transistor into the cut-off region.
Each spin-transistor can therefore perform three-input logic
computation. This structure permits the computation of more
complex logic within a single stage without requiring
additional transistors. As each stage requires the same amount
of current, the use of fewer stages implies less current flow.
Since fewer transistors are required to perform a logic
function, there is increased circuit efficiency in terms of power
dissipation, propagation delay, and physical area.
B. Multiplexer
This new logic family can be used to design highly
compact circuits. Multiplexer circuits, for example, can be
reduced to a single stage. Specific implementations of the
general circuit depicted in Fig. 5 are shown in Fig. 6 which
perform (a) 2:1 and (b) 4:1 multiplexing functions. In the 2:1
multiplexer, when the Sel wire carries current, Q1 is always in
the cut-off region. When Sel does not carry current, the ŃSel
wire carries current, causing Q2 to be cut-off. Sel chooses
which spin-transistor responds to its input. The correct signal
is propagated to the output in both inverted and non-inverted
forms.
A 4:1 multiplexer can be structured in a similar way. An
additional spin-transistor is required for each additional input,
and two control wires are used for each spin-transistor. The
control wires implement a NOR function to select the spintransistor in operation; if either of a spin-transistor's control
wires carries current, that spin-transistor is cut-off. Therefore,
exactly one spin-transistor is in operation at all times, and the
selected input is propagated to the output along with its
complement.
These multiplexer circuits are far more compact than
conventional ECL multiplexer circuits, which require multiple
stages of logic and at least 20 transistors. These circuits are
also more compact than standard CMOS circuits, which
require twelve transistors and two stages, and are comparable
to CMOS transmission gate multiplexers, which represent one
of the greatest strengths of CMOS [18].
C. Full Adder
The full adder achieved with this logic family is also
highly efficient, as demonstrated in Fig. 7. This circuit
contains two distinct sections, one each for the Sum and COUT
logic. The functions have been specifically optimized for
emitter-coupled spin-transistor logic XVLQJ'H0RUJDQ¶V/DZV
Figure 7. Full adder implemented with emitter-coupled spin-transistor logic.
142
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
COUT
( A š B) › ( A š C IN ) › ( B š C IN )
(1)
( A š B) › ( A š CIN ) › ( A š B › CIN )
Sum
A † B † C IN
A š B † C IN › ( A š B † C IN ) (2)
In the center of the circuit, a voltage divider sets a reference
voltage VR for the two reference spin-transistors, QRS and
QRC. For the Sum logic, the control wires carry current in
opposite directions, and therefore implement the XOR
function. Q1 is in the active region when both A and B † CIN
are '0', and is otherwise cut-off. Q2 is in the active region
when A is '1' and B † CIN is '0'. If either or both Q1 or Q2 are
in the active region, significant current flows through R IN. This
current causes ŃSum to reach a high voltage, and Sum a low
voltage. The logic for COUT and ŃCOUT functions similarly.
This full adder is unique in its use of only a single stage of
logic to produce all of the outputs. As each stage of logic adds
WR D VLJQDO¶V SURSDJDWLRQ WLPH, the use of a single stage
provides exceptional speed characteristics. It is also compact,
using only 7 spin-transistors. This circuit compares favorably
to a standard ECL full adder, which requires 24 transistors, and
the CMOS version which requires 28 transistors. In addition,
both of these conventional circuits require multiple stages of
logic, limiting circuit speed. Emitter-coupled spin-transistor
logic therefore provides circuits with higher performance while
also decreasing power and area consumption.
In addition to being compact, this logic family can be
cascaded for application to large computing systems and scaled
to very small dimensions without adverse effects. Scaling leads
to substantial speed-up and decreased power dissipation,
presenting the opportunity for large-scale adaptation of emittercoupled spin-transistor logic.
IV.
ANALYSIS OF LOGIC FAMILY
In this section, we perform a detailed analysis of the logic
families presented in the previous section.
Figure 9. Modified Ebers-Moll BJT model with magnetic-field dependent
resistor [16].
A. Model of a Spin-Transistor
Experimental data from the device presented in [16] shows
a positive magnetoresistance in an InMnAs spin-transistor.
This magnetoresistance attenuates the current through the
spin-transistor, causing the transistor to enter the cut-off
region in the differential pairs. In the room-temperature data
provided in Fig. 8, amplification decreases with increasing
magnetic field. This transistor, an initial exploration into
magnetoresistive spin-transistors that was designed as a proofof-concept, will be improved significantly in future work. In
particular, by optimizing the fabrication technique, it is
possible to achieve much higher amplification in these spintransistors, approaching those achieved with InAs by Wicks
[22]. Additionally, by increasing the Mn concentration, it is
possible to increase the giant magnetoresistance (GMR) of the
junction, resulting in a greater change in amplification with
magnetic field. It should be noted that the GMR increases with
decreasing temperature, providing an even greater
magnetoresistive effect at low temperatures. Despite its issues,
this exploratory spin-transistor demonstrates its suitability for
advanced logic functionality.
In lieu of a complete understanding of the physical
mechanisms underlying the magnetoresistance, a modified
Ebers-Moll model [23] is used in accordance with previous
work [16]. A magnetic-field dependent resistor R(B) has been
added to the circuit shown in Fig. 9 to include the GMR effect
on the base-emitter junction. The resistance of this resistor
increases with magnetic field to match the trend shown
experimentally in Fig. 8.
B. Magnetic Field Strength
The magnetic field produced by a control wire through the
shield is determined using Ampere's Law for the structure
shown in Fig. 2,
B
Figure 8. Experimental data showing amplification of InMnAs spintransistor with 1 μA base current [16].
P r P 0 I total
,
SD
(3)
where D is the diameter of the magnetic shield, Itotal is the
magnitude of the net current in the control wires, ȝo is the
permeability of free space, and ȝr is the relative permeability
of the mu-metal shield. The boundary conditions of Maxwell's
Equations state that the strength of a magnetic field is constant
across a boundary perpendicular to the direction of the field.
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
143
This implies a field of equal strength through the spintransistor, though stray field lines and other parasitic effects
will cause attenuation. Given conservative estimates for these
parameters, the magnetic field is more than sufficient to
induce magnetoresistive behavior in the spin-transistor.
C. Circuit Simulation
Simulations based on the aforementioned spin-transistor
model and magnetic field calculation have been performed
using Synopsis HSPICE. The output voltages from the
differential amplifier are listed in Tables 1 and 2, for the 2:1
multiplexer and full adder, respectively. Unlike CMOS, these
voltages are amplified with an ECL emitter-follower stage to
complete a functional circuit. The voltage difference between
the '1' and '0' outputs is about 0.7 V in most implementations
of ECL.
The simulations show correct outputs that are always
clearly identifiable as a '1' or '0', though different combinations
of inputs produce slightly different output voltages. These
slight variations are due to the difference in the mechanisms
caused by the magnetic and electronic inputs. Additionally, it
can be seen that the presence of multiple active input transistors
results in a stronger signal than is caused by a single active
input.
TABLE I.
MULTIPLEXER SIMULATION RESULTS
Sel
0
0
0
0
1
1
1
1
TABLE II.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Out (V)
0
0
0.65
0.71
0
0.65
0
0.71
FULL ADDER SIMULATION RESULTS
CIN
0
1
0
1
0
1
0
1
Sum (V)
0
0.62
0.62
0
0.62
0
0
0.62
COUT (V)
0.02
0.04
0.04
0.64
0.08
0.62
0.62
0.62
D. Scaling
As the magnetic field created by the control wires is
inversely proportional to the shield diameter, this technology
is suitable for scaling. A constant
I total
ratio produces a
D
constant magnetic field, making it possible to decrease the
current, and therefore the power, with scaling. This behavior is
in contrast to conventional circuit technologies based purely
on electron charge, which are difficult to scale to ever smaller
dimensions.
144
E. Computing Implications
As demonstrated in Section III, logic circuits designed
with this emitter-coupled spin-transistor logic family can
execute logical functions using 20% to 30% of the number of
devices required for conventional ECL while drawing the
same amount of current per device. In this new logic family as
well as conventional ECL, the delay and power dissipation of
a computing circuit are proportional to the number of logic
stages. Therefore, a speedup of 3x to 5x is achievable, along
with a decrease in power consumption of 70% to 80%,
resulting in a decrease in power-delay product by a factor of
10 to 25 depending on the logic circuit. This greater than an
order-of-magnitude improvement increases the performance of
high speed computing while also enhancing the range of
applications for which ECL-based logic is effective.
V.
CONCLUSION
In contrast to other proposed spintronic logic families,
emitter-coupled spin-transistor logic provides the critical
property of logic elements that can drive cascaded stages
without amplification or modulation. This ability to cascade
logic stages is necessary for logic circuits capable of replacing
Si CMOS in the post-Dennard scaling era [24]. Emittercoupled spin-transistor logic provides significant improvements
in speed, power, and area, promising to be a very highperformance logic family for the next generation of computing.
ACKNOWLEDGMENTS
The authors would like to thank Nikhil Rangaraju for
technical discussions and the anonmyous reviewers for their
insightful comments.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
E. Y. Tsymbal and I. Zutic, Eds., Handbook of spin transport and
magnetism. Boca Raton, FL: CRC Press, 2012.
6$:ROI-/X056WDQ(&KHQDQG'07UHJHU³7KHSURPLVH
of nanomagnetics and spintronics for future logic and universal
PHPRU\´ Proc. IEEE, vol. 98, pp. 2155-2168, Dec. 2010.
J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, "InMnAs
Magnetoresistive Spin-Diode Logic," Proc. ACM Great Lakes
Symposium on VLSI, May 2012.
6'DWWDDQG%'DV³(OHFWURQLFDQDORJRIWKHHOHFWUR-RSWLFPRGXODWRU´
Appl. Phys. Lett., vol. 56, pp. 665-667, Feb. 1990.
J. Shen, "Logic Devices and Circuits Based on Giant
Magnetoresistance," IEEE Trans. Magnetics, vol. 33, pp. 4492-4497,
Nov. 1997.
$ 1H\ & 3DPSXFK 5 .RFK DQG . + 3ORRJ ³3URJUDPPable
FRPSXWLQJ ZLWK D VLQJOH PDJQHWRUHVLVWLYH HOHPHQW´ Nature, vol. 425,
pp. 485-487, Oct. 2003.
S. S. P. Parkin et al., "Exchange-biased magnetic tunnel junctions and
application to nonvolatile magnetic random access memory," J. Appl.
Phys., vol. 85, pp. 5828-5833, Apr. 1999.
6$:ROI-/X056WDQ(&KHQDQG'07UHJHU³7KHSURPLVH
of nanomagnetics and spintronics for future logic and universal
PHPRU\´Proc. IEEE, vol. 98, pp. 2155-2168, Dec. 2010.
R. P. Cowburn and M. E. Welland, "Room temperature magnetic
quantum cellular automata," Science, vol. 287, pp. 1466-1468, Feb.
2000.
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
[10] A. Imre, G. Csaba, L. Ji, A. Orlov, G. H. Bernstein, and W. Porod,
³0DMRULW\ ORJLF JDWH IRU PDJQHWLF TXDQWXP-GRW FHOOXODU DXWRPDWD´
Science, vol. 311, pp. 205-208, Jan. 2006.
[11] '$$OOZRRGHWDO³0DJQHWLFGRPDLQ-ZDOOORJLF´Science, vol. 309,
pp. 1688-1692, Sep. 2005.
[12] H. Dery, P. Dalal, L. Cywinski, L. J. Sham, "Spin-based logic in
semiconductors for reconfigurable large-scale circuits," Nature, vol. 447,
pp. 573-576, May 2007.
[13] $.KLWXQ0%DRDQG./:DQJ³6SLQZDYHPDJQHWLFQDQRIDEULFD
new approach to spin-EDVHG ORJLF FLUFXLWU\´ IEEE Trans. Magnetics,
vol. 44, pp. 2141-2152, Sep. 2008.
[14] B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, "Proposal for an
all-spin logic device with built-in memory," Nature Nanotechnology,
vol. 5, pp. 266-270, Feb. 2010.
[15] C. Augustine, G. Panagopoulos, B. Behin-Aein, S. Srinivasan, A.
6DUNDU . 5R\ ³/RZ-power functionality enhanced computation
architecture using spin-baseG GHYLFHV´ Proc. IEEE/ACM International
Symposium on Nanoscale Architectures, pp. 129-136, Jun. 2011.
[16] N. Rangaraju, J. A. Peters, and B. W. Wessels, "Magnetoamplification in
a bipolar magnetic junction transistor," Phys. Rev. Lett., vol. 105, pp.
117202-1-4, Sep. 2010.
[17] 15DQJDUDMX3&/LDQG%::HVVHOV³*LDQWPDJQHWRUHVLVWDQFHRI
PDJQHWLF VHPLFRQGXFWRU KHWHURMXQFWLRQV´ Phys. Rev. B, vol. 79, pp.
205209-1-5, May 2009.
[18] J. Millman, Microelectronics: Digital and Analog Circuits and Systems.
New York: McGraw-Hill, 1979.
[19] - $ 3HWHUV 1 5DQJDUDMX & )HHVHU DQG % : :HVVHOV ³6SLQdependent magnetotransport in a p-InMnSb/n-InSb magnetic
VHPLFRQGXFWRUKHWHURMXQFWLRQ´Appl. Phys. Lett., vol. 98, pp. 193506-13, May 2011.
[20] J. Fabian, I. Zutic, S. D. Sarma, "Magnetic bipolar transistor," Appl.
Phys. Lett., vol. 84, pp. 85-87, Jan. 2004.
[21] D. Neamen, Electronic Circuit Analysis and Design, 2nd ed. New York:
McGraw-Hill, 2001.
[22] K. L. Averett, X. Wu, M. W. Koch, G. W. Wicks, "InAs-based
heterojunction bipolar transistors," Electronics Letters, vol. 38, pp. 344346, Mar. 2002.
[23] J. J. Ebers, J. L. Moll, "Large-signal behavior of junction transistors,"
Proc. IRE, vol. 42, pp. 1761-1772, Dec. 1954.
[24] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.63:RQJ³'HYLFHVFDOLQJOLPLWVRI6L026)(7VDQGWKHLUDSSOLFDWLRQ
GHSHQGHQFLHV´Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
145