J. W. Bruce
24
the ADC’s input. ADCs are implemented with many, and widely varying, architectures. Several sources,
listed at the conclusion of this article,
can provide a glimpse into the
diverse world of ADCs.
Viewed as a black box, the DAC
has an n bit digital word input. Its
analog output is proportional to the
DAC’s input. The DAC’s output is
typically a voltage or current. A wide
variety of circuits have been
designed to perform digital to analog
conversion. The astounding assortment of data converter architectures
will quickly overwhelm the uninitiated. An understanding of how conversions are done will allow the engineer to make the proper choice for a
given application.
DACs can be classified into two
categories, Nyquist-rate DACs or
oversampling DACs, according to
their operation. In general, Nyquistrate DACs operate on data samples
generated their outputs at the sampling frequency. Nyquist-rate DACs
typically have circuits that very obviously convert a digital number into
an analog quantity. Oversampling
DACs operate on data samples generated at frequencies that are much
higher than the sampling frequency.
Oversampling DACS usually have
relatively simple circuitry, but use
complex signal processing techniques to complete the data conversion. An excellent reference is pro-
0278-6648/01/$10.00 © 2001 IEEE
vided at the conclusion of this article.
This article covers two popular types
of Nyquist-rate DACs: the flash
DAC and the serial DAC.
Flash DACs perform their conversion in a single clock cycle and
are typically designed to operate at
high speeds. Serial DACs convert
the digital signal to an analog signal
one bit at a time. Serial DACs trade
the hardware complexity of a flash
DAC for longer conversion times.
In this article, three variations of
flash DACs are introduced along
with two serial DACs. Also, the
advantages and disadvantages for
each architecture will be discussed.
Flash DACs
A flash digital to analog converter, sometimes called a parallel DAC,
is characterized by its ability to generate an output within a single clock
cycle. The speed of a flash DAC is
achieved by the parallel generation
of a set of fixed references. The set of
references are complete, i.e., they are
capable of constructing all the possible DAC output values. Thus, any
output can be created nearly instantly providing flash DACs with the
ability to operate at high speeds. The
differences between resistor string
DACs, charge scaling DACs, and
current steering DACs are primarily
how each one creates the set of references and combines them to create
the output.
IEEE POTENTIALS
© 1997 Artville, LLC., PhotoDisc, Jeff Nishinaka
he ever-dropping
cost of Very Large
Scale
Integrated
(VLSI)
circuits
allows many analog
functions to be done digitally.
However, the real world still is, and
will always continue to be, a fundamentally analog place. Thus, the
analog signal of interest is translated into a format that a digital computer can utilize. This translation is
the function of an Analog to
Digital Converter (ADC). After
processing, the resulting digital
stream of information is returned
to an analog form by a Digital to
Analog Converter (DAC). An analog-signal once again, the information can be consumed by human
senses or manipulated by analog
circuits. Figure 1 shows the information conversion cycle between
the analog and digital domains.
ADCs and DACs are ubiquitous in computing systems. Many
electronic products, including
compact disc players, camcorders,
digital cellular phones, modems,
computer sound cards, computer
graphics adapters, and high definition televisions, contain one or
more data converters.
For many purposes, a sufficient
interpretation is that the converter
accepts an analog input, typically a
voltage or current. It then provides an
n bit digital output which represents
J. W. Bruce
24
the ADC’s input. ADCs are implemented with many, and widely varying, architectures. Several sources,
listed at the conclusion of this article,
can provide a glimpse into the
diverse world of ADCs.
Viewed as a black box, the DAC
has an n bit digital word input. Its
analog output is proportional to the
DAC’s input. The DAC’s output is
typically a voltage or current. A wide
variety of circuits have been
designed to perform digital to analog
conversion. The astounding assortment of data converter architectures
will quickly overwhelm the uninitiated. An understanding of how conversions are done will allow the engineer to make the proper choice for a
given application.
DACs can be classified into two
categories, Nyquist-rate DACs or
oversampling DACs, according to
their operation. In general, Nyquistrate DACs operate on data samples
generated their outputs at the sampling frequency. Nyquist-rate DACs
typically have circuits that very obviously convert a digital number into
an analog quantity. Oversampling
DACs operate on data samples generated at frequencies that are much
higher than the sampling frequency.
Oversampling DACS usually have
relatively simple circuitry, but use
complex signal processing techniques to complete the data conversion. An excellent reference is pro-
0278-6648/01/$10.00 © 2001 IEEE
vided at the conclusion of this article.
This article covers two popular types
of Nyquist-rate DACs: the flash
DAC and the serial DAC.
Flash DACs perform their conversion in a single clock cycle and
are typically designed to operate at
high speeds. Serial DACs convert
the digital signal to an analog signal
one bit at a time. Serial DACs trade
the hardware complexity of a flash
DAC for longer conversion times.
In this article, three variations of
flash DACs are introduced along
with two serial DACs. Also, the
advantages and disadvantages for
each architecture will be discussed.
Resistor string DACs
Flash DACs
A flash digital to analog converter, sometimes called a parallel DAC,
is characterized by its ability to generate an output within a single clock
cycle. The speed of a flash DAC is
achieved by the parallel generation
of a set of fixed references. The set of
references are complete, i.e., they are
capable of constructing all the possible DAC output values. Thus, any
output can be created nearly instantly providing flash DACs with the
ability to operate at high speeds. The
differences between resistor string
DACs, charge scaling DACs, and
current steering DACs are primarily
how each one creates the set of references and combines them to create
the output.
IEEE POTENTIALS
© 1997 Artville, LLC., PhotoDisc, Jeff Nishinaka
he ever-dropping
cost of Very Large
Scale
Integrated
(VLSI)
circuits
allows many analog
functions to be done digitally.
However, the real world still is, and
will always continue to be, a fundamentally analog place. Thus, the
analog signal of interest is translated into a format that a digital computer can utilize. This translation is
the function of an Analog to
Digital Converter (ADC). After
processing, the resulting digital
stream of information is returned
to an analog form by a Digital to
Analog Converter (DAC). An analog-signal once again, the information can be consumed by human
senses or manipulated by analog
circuits. Figure 1 shows the information conversion cycle between
the analog and digital domains.
ADCs and DACs are ubiquitous in computing systems. Many
electronic products, including
compact disc players, camcorders,
digital cellular phones, modems,
computer sound cards, computer
graphics adapters, and high definition televisions, contain one or
more data converters.
For many purposes, a sufficient
interpretation is that the converter
accepts an analog input, typically a
voltage or current. It then provides an
n bit digital output which represents
Voltage division flash DACs
typically use 2Bor more matched
circuit elements to divide the reference voltage into 2Bvoltages that
can be used as the DAC’s analog
voltage output. Resistor string
DACs and charge scaling DACs
use resistors and capacitors, respectively, to perform voltage division.
They are the most common voltage
division DACs. Current steering
flash DACs typically uses B, 2B, or
more matched circuit elements, to
create reference currents. These are
summed to create the DAC’s analog current output.
Resistor string digital-to-analog
converters use a resistor voltage
divider network, connected between
two reference voltages, to generate a
complete set of voltages. Each voltage divider tap corresponds to a digital input. A B bit resistor string flash
DAC uses at least 2B resistors. Some
designs use additional resistors to create more accurate reference voltages,
or voltages that correspond to rounded rather than truncated digital values.
Switches, controlled by the DAC’s
digital input, select the appropriate
reference voltage to use as the output.
Figure 2 shows a three-bit resistor
string flash DAC architecture. The
resistor string divides the DAC reference voltage, VREF, into 2B equally
spaced voltages, Vk for k = 0, 1, ...,
2B – 1. The DAC architecture in
Figure 2(a) uses 2B switches to connect the appropriate voltage to the
DAC output, y(t). The switch control
signals, Sk for k = 0, 1, ...,2B –1, are
generated by a B:2Bdecoder (not
shown). For longer word lengths, a
large parasitic capacitance appears at
the DAC output, limiting the DAC
operating speed. An alternative resis-
AUGUST/SEPTEMBER 2001
tor string DAC architecture in Fig.
linearities are introduced directly into
2(b) arranges the switches into a
the DAC’s output.
binary tree structure. This architecA B:2B decoder is required to
ture does not need a dedicated
provide the 2B signals controlling the
switches for the DAC implementadecoder, and uses the DAC’s digital
tion in Fig. 2(a). Moreover, the
input bits, xk[n], and their compleDAC’s output is always connected to
ments, *xk[n], for k = 0, 1, ..., 2B – 1,
to control the switches. Furthermore,
2B – 1 open switches and one closed
parasitic capacitances are reduced
switch. For large B, the parasitic
since the output is connected to most
capacitance at the DAC’s output
B closed switches and B open switchnode grows large, and cones, thus increasing the conversion
version times lengthen. An alterspeed. Major disadvanThe "Analog" World
tages of the resistor string
flash DAC architecture in
Fig. 2 are the extreme voltage string resistors matching requirements and the
Analog to ...110001010...
...100101110... Digital to
Digital
DAC’s inability to drive
Digital
Analog
Signal
Converter
Converter
loads without a buffer.
Processor
(ADC)
(DAC)
Resistor string voltage
division accuracy is Fig. 1 Information conversion cycle between the
restricted by VLSI techanalog and digital domains
nology limitations. They
VREF
VREF
include: linear gradient
errors due to variations in
V7
V7
doping density or fabriS7
x0[n]
R
R
cated resistor widths,
x1[n]
V6
V6
S6[n]
nonlinear errors in dif*x0[n]
R
R
x2[n]
fused resistors from non
V5
V5
S5[n]
x0[n]
uniform depletion layer
R
R
*x1[n]
thickness, random errors
V4
V4
S4[n]
*x0[n]
y(t)
R
due to geometry uncery(t)
R
V3
V3
tainties, random contact
S3[n]
x0[n]
R
R
resistances, component
x1[n]
V2
V2
n
]
S
[
noise and component
*x0[n]
2
R
R
*x2[n]
aging. Furthermore, the
V1
V1
x
[
n
]
n
]
S
[
0
1
output of a voltage diviR
R
*x1[n]
sion DAC must be
V0
V0
S0[n]
*x0[n]
R
R
buffered by a high impedance amplifier. If appreciable current is drawn from
(a)
(b)
the voltage divider network, additional errors will Fig. 2 Three bit resistor string flash DAC architecture
be introduced due to the
(a) requiring a decoder to generate switch connonlinearity of the DAC’s
trol signals; (b) Three bit resistor string flash DAC
analog switches. High
architecture using tree structured switches proimpedance amplifier nonviding inherent decoding
25
physical size of the
resistors
can
be
increased to minimize
the resistor matching
t3 [n ]
t6 [n ]
t0 [n ]
t5 [ n ]
t1 [n ]
t2 [ n]
t4 [n ]
t7 [n ]
reset
errors, but that lowers
C
C
C
C
C
C
C
C
C
the circuit density.
y(t)
With current fabrica(a)
tion technology, resistor
VREF
string DACs are limited
to word lengths of less
than 10 bits. Other resistor string DAC design
x 2 [n ]
x1 [n ]
x0 [n ]
Reset
issues deal with circuit
4C
2C
C
C
area and power dissipay(t)
tion. Large chip areas are
required for longer word
(b)
length DACs due to the
Fig. 3 Three bit charge scaling flash DAC architecture
large number of voltage
(a) with unary weighted capacitors, and (b)
divider resistors. Area
binary weighted capacitors
usage is then further
increased because the
y(t)
VLSI processes are inefficient at creating highly
resistive components.
t1 [n ]
t5 [n ]
t6 [n ]
t7 [n ]
t2[n]
t3 [n ]
t4 [n ]
t 0 [n ]
Furthermore, since curI
I
I
I
I
I
I
I
rent is always flowing
through the voltage
(a)
divider, power is cony(t)
stantly being dissipated.
Although the resistor
value, R, can be
x 1 [n ]
x2 [n ]
x 0 [n ]
increased to reduce
4I
2I
I
power losses, larger
resistors occupy more
(b)
area. Finally, resistor
string DACs have no
Fig. 4 Three bit current steering flash DAC architecture
(a) with unary weighted current sources, and (b) load driving ability. If
the DAC output has an
binary weighted current sources
appreciable current draw,
native implementation of the resistor
this current is siphoned off of the voltstring flash DAC is shown in Fig. 2(b).
age divider. This siphoning causes the
This implementation uses a binary tree
reference voltages to be inaccurate.
switch array. The DAC output is conA big advantage of resistor string
nected to B closed switches and B open
DACs is their monotonicity and their
switches. Fewer switches connected to
ability to operate at high speeds.
the DAC output reduce the parasitic
Monotonicity is the guarantee that an
capacitances and reduce the conversion
increase in the DAC’s digital input
time. The binary tree array switches are
causes the DAC’s analog output to
controlled by the DAC’s binary input
increase. Because of the parallel
since the decoding is inherent in the
nature of their design, the resistor
binary tree arrangement of the switches.
string DAC implementations in Fig. 2
The resistor string DAC architecare very fast. Resistor string DACs are
tures in Fig. 2 are only as accurate as
used in many high bandwidth applicathe matching of voltage divider resistions such as digital video, RADAR
tors. As the DAC’s input word length
and communications.
increases, the quantization step size
decreases. In other words, the reference
Charge scaling flash DAC
voltages generated by the resistor string
Charge scaling flash digital to anaare much closer, and the resistor matchlog converters perform signal convering requirements are increased.
sion by dividing the DAC’s reference
Unfortunately, modern VLSI fabricavoltage, V REF , using B, 2 B, or more
tion processes are not exact and resismatched capacitors. For example, Fig. 3
shows a three bit charge scaling DAC
tors cannot be perfectly matched. The
VREF
26
architecture. Initially, each capacitor is
discharged using the reset switch.
Next, each capacitor is connected to
either V REF or ground, causing the
DAC output voltage, y(t), to be a function of the voltage division between
the capacitors. The DAC architecture
in Fig. 4(a) uses 2B switches to connect
the appropriate number of unary
weighted capacitors to VREF and the
remaining capacitors to ground. The
switch control signals, tk for k = 0, 1,
..., 2 B - 1, are generated by a thermometer encoder (not shown). The
charge scaling flash DAC architecture
in Fig. 3(b) uses B switches to connect
the appropriate combination of binary
weighted capacitors to VREF thereby
creating the DAC output voltage, y(t).
This architecture does not need a thermometer encoder. It uses the DAC’s
digital input bits, xk[n], and their complements, *xk[n], for k = 0, 1,…, 2B - 1,
to control the switches. A major disadvantage of the charge scaling flash
DACs in Fig. 3 is the inability to drive
loads without a buffer, the need for
precisely matched capacitors, and the
large transient currents drawn from
VREF during switching.
Charge scaling DACs are made
nonlinear by capacitor mismatch,
capacitor voltage dependence, and top
plate parasitic capacitances. Capacitor
geometry mismatches can be both linear gradient and random. Geometric
mismatches are functions of capacitor
width, length and oxide thickness.
Oxide thickness is a function of the
fabrication process. Oxide thickness
gradients can become significant for
large capacitors. Therefore, increasing
capacitor dimensions does not reduce
the mismatch error indefinitely.
Capacitor mismatch reaches its smallest amount at a certain process-specific
dimension. To improve the matching
between capacitors, common centroid
layout techniques can be used.
Capacitor voltage dependence originates from the variation of the dielectric
constant across capacitors and the
depletion region thickness of each
capacitor plate. Also, the top plate of
the capacitors in the capacitor array has
an appreciable parasitic capacitance to
the substrate. This parasitic capacitance
introduces a gain error over the fullscale range of the DAC. While the gain
error is easily ignored or corrected in
stand-alone DACs, it creates differential
nonlinearities in multistep ADCs or
oversampling modulators.
IEEE POTENTIALS
Current steering flash DAC
A B bit current steering flash digital
to analog converter typically uses B, 2B
or more matched circuit elements to
create B, 2B, or more reference currents.
For example, Fig. 4 shows a three bit
current steering DAC architecture. The
resistor string divides the DAC reference voltage, V REF , into 2 B equally
spaced voltages, Vk for k = 0, 1,…, 2B -1.
The DAC architecture in Fig. 4(a) uses
2B switches to connect the appropriate
number of binary weighted reference
currents to create the DAC output current, y(t). The switch control signals, tk
for k = 0, 1,…, 2B - 1, are generated by
a thermometer encoder (not shown). An
alternative current steering flash DAC
architecture in Figure 4(b) uses B
switches to connect the appropriate
combination of binary weighted reference currents to create the DAC output
current, y(t). This architecture does not
need a thermometer encoder and uses
the DAC’s digital input bits, xk[n] for
k = 0, 1,…, 2 B - 1 , to control the
switches. A major advantage of the current steering DAC architecture in Fig. 4
is its inherent high current drive and
high speed. A disadvantage of this
architecture is the glitches created when
the switches do not operate at the exact
same instant. Since the current sources
are in parallel, if one source is switched
off and another source is switched on, a
glitch occurs if the timing is such that
both sources are off, or both sources are
on, at the same instant. This error is
most significant at the DAC’s midscale
when the largest number of sources are
switching. Another design issue in current steering flash DACs is the stringent
current source matching requirements.
Current mirrors are typically used to
implement the current sources in current
steering DACs. However, current mirrors can exhibit significant matching
errors, including linear gradient errors,
random errors due to geometry uncertainties, component aging and component noise. Additional sources of error
in current steering DACs are the finite
output impedance of the current sources
and the DAC’s load resistor nonlinearity. As the DAC output varies over its
full-scale range, different impedances
are connected to the DAC output changing the load resistance and introducing
nonlinearity. Furthermore, many current
steering DACs convert the current output to a voltage by connecting the
DAC’s output node to an integrated cir-
AUGUST/SEPTEMBER 2001
cuit resistor. Polysilicon resistors have a
hyperbolic sine current-voltage characteristic, and integrated circuit diffusion
resistors are nonlinear because their
depletion region’s thickness is a function of voltage.
Serial DACs
their tasks of conversion, thus cyclic
DACs typically have very compact
designs. A cyclic DAC converts the digital input to an analog quantity one bit at
a time. Thus, the hardware complexity
is reduced at the expense of increased
conversion time. In a B bit cyclic DAC,
each bit conversion is added to the
input’s previous bit conversion until all
B bits of the DAC’s input have been
processed. The accumulated result is the
cyclic DAC’s analog output. Therefore,
B cycles are required to convert the
cyclic DAC’s B bit digital input.
Figure 6 shows a voltage summing
cyclic DAC architecture. In this architecture, the reset switch closes at the
start of each conversion forcing the out-
A serial digital to analog converter
is characterized by its bit-wise conversion of a DAC input. In general, serial
DACs are constructed with much simpler circuits compared to flash DACs.
However, the savings in hardware complexity is “bought” by an increase in
conversion time. This reduces the overall speed of the converter. For serial
DACs to be used at a Nyquist rate, the
internal “shifting” clock must
φ1
xk
φ2
run at a fre+
quency higher
than the Nyquist VREF +
C2
*xk
C1
Reset
Reset
y(t)
–
frequency.
–
Furthermore, the
serial
DACs
internal clock
frequency gener- Fig. 5 A two capacitor serial DAC architecture
ally increases with an increase in
put voltage of the sample and hold
input word length. This requirement is
amplifier (SHA) to be zero. To start the
often the limiting factor in serial DAC
conversion, the reset switch is opened.
The least significant bit of the DAC
clock rates.
A wide variety of serial DACs exist.
input determines if the voltage source,
A common characteristic of serial
or ground, is connected to the summer
DACs is that the data conversion is
input. The voltage, VREF , is connected
to the summer if the DAC’s least signifdone one bit at a time. To illustrate, Fig.
icant bit is one, and ground is connected
5 shows a very simple serial DAC: the
to the summer if the DAC’s least signiftwo-capacitor serial DAC. In Fig. 5, C1
= C2 and the signals ø1 and ø2 denote
icant bit is zero. The sample and hold
the phases of a two-phase nonoverlapamplifier holds the voltage constant and
ping clock. In this architecture, the reset
an amplifier with gain of 0.5 feeds the
switch closes at the start of each convervoltage back through the summer. The
sion, discharging both capacitors and
feedback path’s voltage is added to
forcing the DAC’s output voltage, y(t),
VREF if the DAC’s second least significant bit is one and ground if the DAC’s
to be zero. To start the conversion, the
second least significant bit is zero. The
reset switch is opened and ø1 = 1, the
process continues until all B bits have
least significant bit (LSB) of the DAC
been examined and y(t) is proportional
input determines if the C1 is charged to
to the cyclic DAC’s input.
VREF or zero. Next, ø1 opens its switch
The most obvious drawback to
and ø2 closes its switch. This operation
cyclic DACs is the increased conversion
allows C 1 and C 2 to share charges.
time compared to flash DACs.
Afterwards, ø2 opens its switch, ø1 closFurthermore, the conversion time
es its switch, and C1 is charged to VREF
increases linearly with the length of the
or zero, depending on the value of the
DAC’s input. However, the cyclic DAC
second least significant bit. The process
is extremely compact, and the circuit
continues until all B bits have been
does not change appreciably for longer
examined, and the charge in both C1,
input words. To illustrate, consider a
and C2, and the voltage, y(t), is proporthree bit cyclic DAC with VREF = 10 V
tional to the serial DAC’s input.
and input x2x1x0 = 011. The digital input
Cyclic DAC
011 corresponds to the decimal number
Cyclic digital to analog converters
3. Therefore, the expected DAC output
use very few components to perform
should be y(t) = 3/8 VREF = 3.75 V.
27
xk
VREF
+
-
Σ
Sample and Hold
Amplifier (SHA)
*xk
reset
clock
Fig. 6 A cyclic DAC architecture
Although the cyclic DAC has few
circuit components, these components
must be extremely accurate. The summer, sample and hold amplifier, and the
one-half gain amplifier must all be
accurate to one part in 2B. This requirement is prohibitive for large B, and typically is the limiting design specification
in cyclic DACs.
Pipeline DAC
Cyclic digital-to analog converters
typically have very compact circuits and
longer conversion times than flash
DACs. The pipeline DAC unrolls the
cyclic DAC to create a larger DAC that
can convert at much higher speeds. Like
the related cyclic DAC, a pipeline DAC
converts the digital input to an analog
quantity one bit at a time. However, the
pipeline DAC has dedicated circuitry
for each bit’s conversion. This circuitry
increases its hardware complexity and
operating speeds compared to the cyclic
DACs. In a B bit pipeline DAC, each bit
is processed, added to the previous bit
conversions and passed to the next stage
until all B bits of the DAC’s input have
been processed. The accumulated result
is the pipeline DAC’s analog output.
Therefore, B cycles pass before the initial DAC output is ready, but subsequent outputs are completed at every
clock period thereafter.
Figure 7 shows a voltage summing
pipeline DAC architecture. In this architecture, the least significant bit of the
DAC input determines if the voltage
source, or ground, is connected to the
sample and hold amplifier in the first
stage. The voltage, VREF , is connected
to the sample and hold amplifier if the
DAC’s least significant bit is one and
ground is connected to the sample and
hold amplifier if the DAC’s least significant bit is zero. The sample and hold
amplifier holds the voltage constant and
an amplifier with gain of 0.5 sends the
resulting voltage to the next stage. This
voltage is increased by V REF if the
28
DAC’s second least
significant bit is one,
and unchanged if the
DAC’s second least
significant bit is zero.
The process continues
down the pipeline
until all B bits have
been examined. The
output voltage, y(t), is
1
×−
2
y(t)
1
×−
2
SHA
Σ
Clock
Read more aboutit
• R.J. Baker, H.W. Li, and D.E.
Boyce, CMOS: Circuit design, layout
and simulation, New York: IEEE Press,
1998.
1
×−
2
Σ
VREF
x1
*x1
VREF
SHA
1
×−
2
y(t)
Clock
Clock
x0
*x0
SHA
relative merits, e.g., a flash DAC for
high speed applications, or a cyclic
DAC for low speed applications where
circuit complexity is crucial.
*xB-1
xB-1
VREF
Fig. 7 A pipeline DAC architecture
ready at the last stage B clock period
after the input is initially applied to the
DAC. However, the next to last stage is
forming the next DAC output, the
third-to-last stage is forming the following DAC output, and so on. Therefore,
the B bit pipeline DAC can generate a
valid DAC output each clock period
after an initial B period delay.
The most obvious drawback to
pipeline DACs is the increased hardware complexity compared to cyclic
DACs. Furthermore, the circuit complexity increases linearly with the
length of the DAC’s input. However,
the pipeline DAC can operate at very
high speeds after the initial delay to fill
the pipeline. Like the cyclic DAC, the
pipeline DAC’s components must be
extremely accurate.
All summers, sample and hold amplifiers, and the one-half gain amplifiers
must be accurate to one part in 2B. For
large B, this accuracy requirement, and
the requirement that components be carefully matched between the stages, limits
the pipeline DAC’s input word size.
Summary
The circuits presented in this article
are only examples of flash and serial
DACs implementations. Many variations of these architectures exist, and
many more remain to be discovered.
Furthermore, other DAC architectures,
including subranging DACs, segmented
DACs, multiplying DACs, interleaved
DACs, and oversampling DACs, exist.
The selection of the appropriate DAC
for a given job should be based on its
• J.W. Bruce, “Meeting the analog
world challenge: Nyquist-rate analog to
digital converter architectures,” IEEE
Potentials, vol. 17, no. 5, pp. 36-39,
1999.
• D. Hoeschele, Analog to digital
and digital to analog conversion techniques, New York: Wiley, 1994.
• S. Norsworthy, R. Schreier, and
G.C. Temes, Delta-sigma converters:
Theory, design, and simulation, New
York: IEEE Press, 1994.
• B. Razavi, Principles of data conversion system design, New York: IEEE
Press, 1995.
About the author
J.W. Bruce received a B.S. degree
from the University of Alabama in
Huntsville in 1991, an M.S. degree
from the Georgia Institute of
Technology in 1993, and a Ph.D.
degree from the University of Nevada
in Las Vegas in 2000, all in electrical
engineering. Dr. Bruce has served as a
member of the technical staff at the
Mevatec Corporation and the Integraph
Corporation. He is currently an
Assistant Professor in the Department
of Electrical and Computer Engineering
at Mississippi State University. His
research interests include digital signal
processing architectures and VLSI
implementations for digital signal processing and data conversion. Dr. Bruce
is investigating low harmonic distortion
data converter designs and their analysis. Dr. Bruce is an Associate Editor of
IEEE Potentials.
IEEE POTENTIALS