EE247
Lecture 14
• D/A converters continued:
– Resistor string DACs (continued)
– Serial charge redistribution DACs
– Charge scaling DACs
– R-2R type DACs
– Current based DACs
– Static performance of D/As
• Component matching
• Systematic & random errors
– Practical aspects of current-switched DACs
– Segmented current-switched DACs
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 1
R-String DAC
• Advantages:
– Takes full advantage of availability
of almost perfect switches in MOS
technologies
– Simple, fast for <8-10bits
– Inherently monotonic
– Compatible with purely digital
technologies
Vref
• Disadvantages:
– 2B resistors & ~2x2B switches for B
bits Æ High element count & large
area for B >10bits
– High settling time for high resolution
DACs:
τmax ~ 0.25 x 2B RC
C
Ref:
M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 2
R-String DAC
Including Interpolation
Resistor string DAC + Resistor string
interpolator increases resolution w/o drastic
increase in complexity
e.g. 10bit DACÆ (5bit +5bitÆ 2x25=26 # of
Rs) instead of direct 10bitÆ210
Vref
Considerations:
Vout
‰Main R-string loaded by the interpolation
string resistors
‰Large R values for interpolating stringÆ
less loading but lower speed
‰Can use buffers
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 3
R-String DAC
Including Interpolation
Use buffers to prevent
loading of the main
ladder
Vref
Issues:
Æ Buffer DC offset
Æ Effect of buffer
bandwidth
limitations on
overall speed
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 4
Charge Based: Serial Charge Redistribution DAC
Simplified Operation
Nominally C1=C2
• Operation based on redistribution of charge associated with C1 &
C2 to perform accurate division by factor of 2
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 5
Charge Based: Serial Charge Redistribution DAC
Simplified Operation: Conversion Sequence
T2
T1
QCT11 = VREF × C1 &
→ QCT11 + QCT12 = VREF × C1
QCT11 = 0
QCT11 + QCT12
= QCT 2 + QCT 2 = (C1 + C2 )Vo
1
VREF × C1 = ( C1 + C2 )Vo
Vo = VREF ×
C1
C1 + C2
S i nce C1 = C2
EECS 247- Lecture 14
2
Data Converters: DAC Design
→
Vo =
VREF
2
© 2008 H.K. Page 6
Serial Charge Redistribution DAC
Simplified Operation (Cont’d)
T2
T1
• Conversion sequence:
– Next cycle
• If S3 closed VC1=0 then when S1 closes VC1 = VC2 = VREF/4
• If S2 closed VC1=VREF then when S1 closes VC1 =VC2 =VREF/2+VREF/4
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 7
Serial Charge Redistribution DAC
• Conversion sequence:
– Discharge C1 & C2Æ S3& S4
closed
– For each bit in succession
beginning with LSB, b1:
• S1 open- if bi=1 C1
precharge to VREF if bi=0
discharged to GND
• S2 & S3 & S4 open- S1
closed- Charge sharing
C1 & C2
Æ ½ of precharge on
C1 +½ of charge
previously stored on
C2Æ C2
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 8
Serial Charge Redistribution DAC
Example: Input Code 101
LSB
b3 b2
MSB
b1
• Example input code 101Æ output (4/8 +0/8 +1/8 )VREF =5/8 VREF
• Very small area
• For an N-bit DAC, N redistribution cycles for one full analog output
generation Æ quite slow
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 9
Parallel Charge Scaling DAC
• DAC operation based on capacitive voltage division
Vout
Cy
Cx
C
Vout =
Cx
Vref
Cx + Cy + C
Vref
Æ Make Cx & Cy function of incoming DAC digital word
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 10
Parallel Charge Scaling DAC
reset
Vout
2(B-1) C
8C
4C
2C
C
C
bB-1 (msb)
b3
b2
b1
b0 (lsb)
Vref
B −1
• E.g. “Binary weighted”
Vout =
• B+1 capacitors & switches
(Cs built of unit elements
Æ 2B units of C)
EECS 247- Lecture 14
∑ bi 2 i C
i =0
2B C
Data Converters: DAC Design
Vref
© 2008 H.K. Page 11
Charge Scaling DAC
Example: 4Bit DAC- Input Code 1011
reset
2- Charge phase
1- Reset phase
Vout
Vout
8C
4C
2C
b3
b2
b1
C
C
8C
4C
b3
b2
b0 (lsb)
Vref
Vout =
EECS 247- Lecture 14
2C
C
C
b1
b0 (lsb)
Vref
20 C + 21 C + 23C
11
Vref = Vref
24 C
16
Data Converters: DAC Design
© 2008 H.K. Page 12
Charge Scaling DAC
reset
CP
2(B-1) C
8C
bB-1 (msb)
4C
b3
2C
b2
C
b1
C
b0 (lsb)
Vout
B −1
Vout =
∑b 2 C
i
i
i =0
2 B C + CP
Vref
Vref
• Sensitive to parasitic capacitor @ output
– If Cp constant Æ gain error
– If Cp voltage dependant Æ DAC nonlinearity
• Large area of caps for high DAC resolution (10bit DAC ratio
1:512)
• Monotonicity depends on element matching (more later)
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 13
Parasitic Insensitive
Charge Scaling DAC
reset
CI
CP
2(B-1) C
8C
4C
2C
C
bB-1 (msb)
b3
b2
b1
b0 (lsb)
Vout
+
Vref
B −1 i
∑ bi 2 C
Vout = − i = 0
Vref ,
CI
B −1 i
∑ bi 2
B
CI = 2 C → Vo ut = − i = 0
Vref
2B
• Opamp helps eliminate the parasitic capacitor effect by producing virtual
ground at the sensitive node since CP has zero volts at start & end
– Issue: opamp offset & speed
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 14
Charge Scaling DAC
Incorporating Offset Compensation
CI
S2
reset
reset
CP
S3
reset
2(B-1) C
8C
4C
2C
C
bB-1 (msb)
b3
b2
b1
b0 (lsb)
S1
-
Vos
Vout
+
Vref
• During reset phase:
– Opamp disconnected from capacitor array via switch S3
– Opamp connected in unity-gain configuration (S1)
– CI Bottom plate connected to ground (S2)
– Vout ~ - Vos Æ VCI = -Vos
• This effectively compensates for offset during normal phase
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 15
Charge Scaling DAC
Utilizing Split Array
reset
C
8/7C
C
2C
4C
b0
b1
b2
+
C
2C
4C
b3
b4
b5
-
Cse rie s =
∑ all LSB arra y C
∑ a ll MS B a rr ay C
Vout
Vref
C
• Split arrayÆ reduce the total area of the capacitors required for high
resolution DACs
– E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64 unit Cs
– Issue: Sensitive to parasitic capacitor
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 16
Charge Scaling DAC
• Advantages:
– Low power dissipation Æ capacitor array does not dissipate DC power
– Output is sample and held Æ no need for additional S/H
– INL function of capacitor ratio
– Possible to trim or calibrate for improved INL
– Offset cancellation almost for free
• Disadvantages:
– Process needs to include good capacitive material Æ not
compatible with standard digital process
– Requires large capacitor ratios
– Not inherently monotonic (more later)
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 17
Segmented DAC
Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
• Example: 12bit
DAC
– 6-bit MSB DACÆ
R- string
– 6-bit LSB DAC Æ
binary weighted
charge scaling
• Complexity much
lower compared to
reset
...
...
...
.
Vout
32 C
16C
8C
4C
2C
b5
b4
b3
b2
b1
C
C
b0
full R-string
– Full R stringÆ
4096 resistors
– Segmented Æ 64
R + 7 Cs (64 unit
caps)
EECS 247- Lecture 14
6bit
resistor
ladder
6-bit
binary weighted
charge redistribution DAC
Switch
Network
Data Converters: DAC Design
© 2008 H.K. Page 18
Current Based DACs
R-2R Ladder Type
• R-2R DAC basics:
R
– Simple R network
divides both voltage
& current by 2
V/2
V
I/2
I/2
I
2R
2R
Increase # of bits by replicating circuit
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 19
R-2R Ladder DAC
Iout
VB
2R
2R
VEE
R
R
2R
R
2R
2R
2R
R
Emitter-follower added to convert to high output impedance current
sources
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 20
R-2R Ladder DAC
How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
4xAunit
VB
2xAunit
VEE
EECS 247- Lecture 14
2R
2R
2R
2R
R
1xAunit 1xAunit
R
Data Converters: DAC Design
© 2008 H.K. Page 21
R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC:
1- Consolidate first two stages:
I2
I3
VB
VEE
IT
I1
Q3
Q2
Aunit
4Aunit
2Aunit
2Aunit
2R
2R
R
2R
R
R
Q3
Q2
Q1
QT
4Aunit
2Aunit
Aunit
2R
R
2R
R
2R
EECS 247- Lecture 14
VB
I1+IT
I2
I3
VEE
Data Converters: DAC Design
© 2008 H.K. Page 22
R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC2- Consolidate next two stages:
I2
I3
VB
VEE
I1+IT
VB
Q3
Q2
4Aunit
2Aunit
2R
R
2R
R
I2+I1+IT
I3
Q3
Q2
2Aunit
4Aunit
4Aunit
R
2R
R
R
VEE
I
I
I
I3 = I2 + I1 + IT → I3 = T ot al , I2 = T ot a l , I1 = To t al
2
4
8
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 23
R-2R Ladder DAC
How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
VB
4Aunit
4I
VEE
2R 2I
R
4I
Aunit
2Aunit
I
2R
2R I
Aunit
2R
R
2I
In most cases need to convert output current to voltage
Ref: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 24
R-2R Ladder DAC
RTotal
R
-
Vout
+
VB
16I
VEE
2R 8I
R
2R 4I
R
2R 2I
R
16I
8I
4I
I
2R
2R I
2R
R
2I
Trans-resistance amplifier added to:
- Convert current to voltage
- Generate virtual ground @ current summing node so that output
impedance of current sources do not cause error
- Issue: error due to opamp offset
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 25
R-2R Ladder DAC
Opamp Offset Issue
R ⎞
out = V in ⎛ 1 +
Vos
os ⎜
⎟
⎝ R T ot al ⎠
R
RTotal
-
If R T ota l = l a r g e,
Vos
out
in
→ Vos
≈ Vos
If RT ota l = n o t l a rg e
R ⎞
out
in ⎛ 1 +
→ Vos
= Vos
⎜ RT ot al ⎟
⎝
⎠
P r ob l em :
+
Vout
Offset
Model
S i nce RT ota l i s co d e d ep en d an t
ou t
w ou l d b e co de d ep en da n t
→ Vos
→ G i ves r i s e t o I N L & DN L
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 26
R-2R Ladder
Summary
• Advantages:
– Resistor ratios only x2
– Does not require precision capacitors
• Disadvantages:
– Total device emitter area Æ AEunitx 2B
Æ Not practical for high resolution DACs
– INL/DNL error due to amplifier offset
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 27
Current based DAC
Unit Element Current Source DAC
……………
Iref
•
•
•
•
•
Iref
……………
Iout
Iref
Iref
Iref
“Unit elements” or thermometer
2B-1 current sources & switches
Suited for both MOS and BJT technologies
Monotonicity does not depend on element matching and is guaranteed
Output resistance of current source Æ gain error
– Cascode type current sources higher output resistance Æ less gain
error
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 28
Current Source DAC
Unit Element
R
……………
Vout
+
Iref
……………
Iref
Iref
Iref
• Output resistance of current source Æ gain error problem
Æ Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed of the amplifier
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 29
Current Source DAC
Binary Weighted
……………
2B-1 Iref
……………
Iout
4 Iref
2Iref
Iref
• “Binary weighted”
• B current sources & switches (2B-1 unit current sources but less
# of switches)
• Monotonicity depends on element matching Ænot guaranteed
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 30
Static DAC Errors -INL / DNL
Static DAC errors mainly due to component mismatch
– Systematic errors
• Contact resistance
• Edge effects in capacitor arrays
• Process gradients
• Finite current source output resistance
– Random variations
• Lithography etc…
• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC
Aug. 1989, pp. 1118-28.
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 31
Current Source DAC
DNL/INL Due to Element Mismatch
+
Iref
Iref
Iref
Iref -ΔI
Iref
Vout
Iref
Iref +ΔI
• Simplified example:
– 3-bit DAC
– Assume only two of the current sources mismatched (# 4 & #5)
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 32
Current Source DAC
DNL/INL Due to Element Mismatch
DN L[ m] =
DN L[ 4 ] =
=
Analog
Output
seg men t[ m] − V [ L S B ]
V [ LSB]
7 Iref R
seg men t[ 4 ] − V [ L S B ]
V [ LSB]
6
5
( I − Δ I )R − IR
4
IR
DN L[ 4 ] = −Δ I / I [ LSB ]
3
( I + Δ I )R − IR
2
DN L[ 5] =
IR
1xIref R
DN L[ 5 ] = Δ I / I [ L S B ]
→ IN Lmax = −Δ I / I [ L S B ]
EECS 247- Lecture 14
Digital
Input
0
000 001 010 011 100 101 110 111
Data Converters: DAC Design
© 2008 H.K. Page 33
Component Mismatch
Probability Distribution Function
• Component parameters Æ Random variables
• Each component is the product of many fabrication steps
• Most fabrication steps includes random variations
ÆOverall component variations product of several random variables
ÆAssuming each of these variables have a uniform pdf distribution:
ÆJoint pdf of a random variable affected by two uniformly
distributed variables Æ convolution of the two uniform pdfs…….
pdf [f(x1)]
pdf [f(x2)]
*
pdf [f(x1,x2)]
Æ
pdf [f(x3,x4)]
pdf [f(x1,x2)]
*
EECS 247- Lecture 14
Gaussian pdf
pdf [f(xm,xn)]
..……..
*
Data Converters: DAC Design
Æ
© 2008 H.K. Page 34
p( x ) =
−(
1
e
2πσ
Probability density p(x)
Gaussian Distribution
2
x−μ )
2σ 2
0.4
0.3
0.2
0.1
0
-3
-2
-1
where:
μ is the expected value and
standard deviation :σ = E( X 2 ) − μ 2
0
1
(x-μ) /σ
2
3
σ 2 → variance
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 35
P (− X ≤ x ≤ + X ) =
=
1
+X −
∫e
2π − X
⎛ X ⎞
= e rf ⎜
⎟
⎝ 2⎠
EECS 247- Lecture 14
x
2
2 dx
Probability density
p(x)
In most cases we are
interested in finding the
percentage of
components (e.g. R)
falling within certain
bounds:
0.4
P(-X ≤ x ≤ +X)
Yield
1
0.8
0.6
0.4
0.2
0
0.3
0.2
0.1
0
95.4
68.3
38.3
0
0.5
Data Converters: DAC Design
1
1.5
X/σ
2
2.5
3
© 2008 H.K. Page 36
Yield
X/σ
P(-X ≤ x ≤ X) [%]
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
EECS 247- Lecture 14
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
Data Converters: DAC Design
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2008 H.K. Page 37
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and μ = 0.
• Find the fraction of opamps with |Vos| < 6mV:
– X/σ = 3
Æ 99.73 % yield
• Fraction of opamps with |Vos| < 400μV:
– X/σ = 0.2 Æ 15.85 % yield
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 38
Component Mismatch
Example: Resistors layouted out
side-by-side
After fabrication large # of
devices measured
& graphed Æ typically if
sample size large shape
is Gaussian
EECS 247- Lecture 14
No. of resistors
…….
…….
400
300
ΔR
200
R
100
0
988
992
996
1000
1004
1008 1012
R[ Ω ]
E.g. Let us assume in this example 1000 Rs measured
& 68.5% fall within +-4OHM or +-0.4% of average
Æ 1σ for resistorsÆ 0.4%
Data Converters: DAC Design
© 2008 H.K. Page 39
Example: Two resistors
layouted out side-by-side
R=
R1 + R2
2
dR = R1 − R2
2
σ dR
∝
R
1
Are a
EECS 247- Lecture 14
Probability density p(x)
Component Mismatch
0.4
0.35
0.3
0.25
ΔR
0.2
R
0.15
0.1
0.05
0
−3σ −2σ
−σ
0
σ
For typical technologies & geometries
1σ for resistors Æ 0.02 to 5%
2σ
3σ
dR
R
In the case of resistors σ is a function of area
Data Converters: DAC Design
© 2008 H.K. Page 40
DNL Unit Element DAC
E.g. Resistor string DAC:
Assumption: No systematic error- only random error
2B −1
Δ = Rmedi an Iref
w h ere Rmedian =
Δi = Ri Iref
D N Li =
=
∑o Ri
Δi = Ri I ref
Δmedian
medi an
R
median
Iref
2B
Δi − Δmedian
Ri − R
Vref
=
dR
R
median
≈
dR
Ri
σ DNL = σ dRi
Ri
To first order Æ DNL of unit element DAC is independent of resolution!
Note: Similar results for other unit-element based DACs
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 41
DNL Unit Element DAC
E.g. Resistor string DAC:
σ D NL = σ dR
i
Ri
EECS 247- Lecture 14
Example:
If σdR/R = 0.4%, what
DNL spec goes into
the DAC datasheet so
that 99.9% of all
converters meet the
spec?
Data Converters: DAC Design
© 2008 H.K. Page 42
Yield
P(-X ≤ x ≤ X) [%]
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247- Lecture 14
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
Data Converters: DAC Design
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2008 H.K. Page 43
DNL Unit Element DAC
E.g. Resistor string DAC:
σ D NL = σ dR
Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
i
Ri
Answer:
From table: for 99.9%
Æ X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 3.3x0.4%=1.3%
ÆDNL= +/- 0.013 LSB
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 44
DAC INL Analysis
A=n+E
Output [LSB]
N
B=N-n-E
B
E
n
Variance
n.σε2
N-n
(N-n).σε2
E = A-n r =n/N
N=A+B
= A-r(A+B)
= (1-r). A - r.B
Æ Variance of E:
σE2 =(1-r)2 .σΑ2 + r 2 .σB2
A
n
Ideal
n
N=2B-1
Input [LSB]
=N.r .(1-r).σε2 = n .(1- n/N).σε2
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 45
DAC INL
⎛
σ E2 = n ⎜ 1 −
⎝
σINL/σε
n⎞
2
⎟ ×σ ε
N⎠
(2B-1)0.5/2
T o f i n d ma x. var i a nce :
→ n = N / 2 → σ E2 =
N
4
dσ E 2
dn
=0
×σ ε 2
• Error is maximum at mid-scale (N/2):
1
2B − 1 σε
2
w i th N = 2B − 1
σ IN L =
0
0
0.5
n/N
1
• INL depends on both DAC resolution & element matching σε
• While σDNL = σε is to first order independent of DAC resolution and is
only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 46
Untrimmed DAC INL
Example:
Assume the following requirement
for a DAC:
σINL = 0.1 LSB
σ INL ≅
1 B
2 − 1 σε
2
⎡ σ INL ⎤
⎥
⎣ σε ⎦
B ≅ 2 + 2log 2 ⎢
Find maximum resolution for:
σε
σε
σε
σε
σε
σε
σε
σε
= 1%
= 0.5%
= 0.2%
= 0.1%
EECS 247- Lecture 14
= 1% → Bmax = 8.6bits
= 0.5% → Bmax = 10.6bits
= 0.2% → Bmax = 13.3bits
= 0.1% → Bmax = 15.3bits
Data Converters: DAC Design
© 2008 H.K. Page 47
Simulation Example
12 Bit converter DNL and INL
DNL [LSB]
1
-0.04 / +0.03 LSB
0
-1
500
1000
1500 2000 2500 3000 3500 4000
bin
INL LSB]
2
1
-0.2 / +0.8 LSB
0
-1
500
1000
1500 2000 2500 3000 3500 4000
bin
EECS 247- Lecture 14
σε
= 1%
B
= 12
Random #
generator used in
MatLab
2
Data Converters: DAC Design
Computed INL:
σINLmax = 0.3 LSB
(midscale)
Why is the
results not as
expected per our
derivation?
© 2008 H.K. Page 48
INL & DNL for Binary Weighted DAC
Iout
• INL same as for unit
element DAC
• DNL depends on transition
–Example:
2B-1 Iref
……………
0 to 1 ÆσDNL2 =
σ(dΙ/Ι) 2
1 to 2 Æ σDNL2 = 3σ(dΙ/Ι) 2
4 Iref
2Iref
Iref
• Consider MSB transition:
0111 … Æ 1000 …
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 49
DAC DNL
Example: 4bit DAC
..
Iout
8
Analog
Output [Iref]
I8off, I4on ,I2on ,I1on
7
I8
8Iref
I4
4Iref
I2
6
I1
2Iref
5
Iref
4
2
σ(dΙref/Ιref)2
1 to 2 Æ σDNL2 = 3σ(dΙref/Ιref)2
EECS 247- Lecture 14
1
I4on ,I2off ,I1off
.
..
..
3
• DNL depends on transition
– Example:
0 to 1 ÆσDNL2 =
..
.
I8on, I4off ,I2off ,I1off
I2on ,I1on
I2on ,I1off
I1on
0
Digital
Input
0000 0001 0010 0011 0100 0101 0110 0111 1000
Data Converters: DAC Design
© 2008 H.K. Page 50
Binary Weighted DAC DNL
• Worst-case transition
occurs at mid-scale:
DNL for a 4-Bit DAC
15
(
)
(
)
2
σ DNL
= 2B−1 − 1 σ ε2 + 2B−1 σε2
σDNL2/ σε2
144244
3 14243
10
0111...
1000...
≅ 2Bσ ε2
σ DNLma x = 2B / 2σε
5
σ INLmax ≅
1
2
2B − 1 σ ε ≅
1
2
σ DNLmax
• Example:
0
2
4
6
8
10
12
14
B = 12, σε = 1%
DAC Output [LSB]
EECS 247- Lecture 14
Data Converters: DAC Design
ÆσDNL = 0.64 LSB
ÆσINL = 0.32 LSB
© 2008 H.K. Page 51
MOS Current Source Variations
Due to Device Matching Effects
Id =
Id1 + Id 2
2
Id1
dId Id1 − Id 2
=
Id
Id
Id2
dId
dW L
2 × dVth
=
+
W
Id
VGS −Vth
L
• Current matching depends on:
- Device W/L ratio matching
Æ Larger device area less mismatch effect
- Current mismatch due to threshold voltage variations:
Æ Larger gate-overdrive less threshold voltage mismatch effect
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 52
Current-Switched DACs in CMOS
Iout
Iref
dId
Id
=
dW L
W
+
L
Switch Array
2d Vth
……
VGS − Vth
256
128
64 ………..…..1
Example: 8bit Binary Weighted
• Advantages:
Can be very fast
Reasonable area for resolution < 9-10bits
• Disadvantages:
Accuracy depends on device W/L & Vth matching
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 53
Unit Element versus Binary Weighted DAC
Unit Element DAC
Binary Weighted DAC
σ DN L = σε
σ DN L ≅ 2 2 σε = 2σ IN L
B
B
−1
σ IN L ≅ 2 2 σε
B
−1
σ IN L ≅ 2 2
σε
Number of switched elements:
S = 2B
S=B
Key point: Significant difference in performance and complexity!
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 54
Unit Element versus Binary Weighted DAC
Example: B=10
Unit Element DAC
Binary Weighted DAC
σ D NL = σ ε
σ DNL ≅ 2 σ ε = 32σ ε
σ I NL ≅ 2
B
2
B
−1
σ ε = 1 6σ ε
σ INL ≅ 2
B
2
2
−1
σ ε = 16σ ε
Number of switched elements:
S = B = 10
S = 2B = 1 0 2 4
Significant difference in performance and complexity!
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 55
“Another” Random Run …
DNL [LSB]
2
1
DNL and INL of 12 Bit converter
-1 / +0.1 LSB,
Now (by chance) worst
DNL is mid-scale.
0
-1
-2
500 1000 1500 2000 2500 3000 3500 4000
bin
Statistical result!
INL [LSB]
2
1
-0.8 / +0.8 LSB
0
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 56
10Bit DAC DNL/INL Comparison
Plots: 100 Simulation Runs Overlaid
Ref: C. Lin
and K. Bult,
"A 10-b,
500MSample/s
CMOS DAC
in 0.6
mm2," IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.
Note: σε=2%
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 57
10Bit DAC DNL/INL Comparison
Plots: RMS for 100 Simulation Runs
Ref: C. Lin
and K. Bult,
"A 10-b,
500MSample/s
CMOS DAC
in 0.6
mm2," IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.
Note: σε=2%
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 58
DAC INL/DNL Summary
• DAC choice of architecture has significant impact on
DNL
• INL is independent of DAC architecture and requires
element matching commensurate with overall DAC
precision
• Results assume uncorrelated random element
variations
• Systematic errors and correlations are usually also
important and may affect final DAC performance
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 59
Segmented DAC
• Objective:
Compromise between unit element and binary weighted DAC
MSB (B1 bits)
(B2 bits)
…
…
LSB
Unit Element Binary Weighted
• Approach:
B1 MSB bits Æ unit elements
B2 LSB bits Æ binary weighted
VAnalog
BTotal = B1+B2
• INL: unaffected same as either architecture
• DNL: Worst case occurs when LSB DAC turns off and one more MSB
DAC element turns on Æ Same as binary weighted DAC with (B2+1) # of
bits
• Number of switched elements: (2B1-1) + B2
EECS 247- Lecture 14
Data Converters: DAC Design
© 2008 H.K. Page 60
Comparison
Example:
B = 12, B1 = 5,
B1 = 6,
( B2 +1)
σ DNL ≅ 2
B2 = 7
B2 = 6
MSB
σ I NL ≅ 2
LSB
2
σ ε = 2σ I NL
−1
σε
S = 2B1 − 1 + B2
Assuming: σε = 1%
DAC Architecture
(B1+B2)
Unit element (12+0)
Segmented
(6+6)
Segmented
(5+7)
Binary weighted(0+12)
EECS 247- Lecture 14
B
2
σINL[LSB]
σDNL[LSB]
# of switched
elements
0.32
0.32
0.32
0.32
0.01
0.113
0.16
0.64
4095
63+6=69
31+7=38
12
Data Converters: DAC Design
© 2008 H.K. Page 61