EECS 141 – S02
Lecture 7
Inverter Sizing
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Last Lecture
l
The CMOS Inverter: Dynamic Behavior
» Capacitors in MOS transistors
l
Summary:
» Gate Capacitances (Thin Oxide)
– Channel - voltage-dependent
– Overlap - constant
» Drain- and Source Junction (Depletion)
– Bottom - CJ, MJ
– Side-wall - CJSW, MJSW
Digital Integrated Circuits
Inverter
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1
Today
Propagation Delay
l CMOS Inverter sizing for optimum delay
l
Digital Integrated Circuits
Inverter
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Propagation Delay
Digital Integrated Circuits
Inverter
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2
CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
Vout
~
Iav
CL
kn VDD
CL
Vin = V DD
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
Digital Integrated Circuits
Inverter
t
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3
CMOS Inverters
VDD
PMOS
1.2µm
=2λ
λ
Out
In
Metal1
Polysilicon
NMOS
GND
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Transient Response
?
3
2.5
2
tp = 0.69 CL (Reqn+Reqp)/2
V
out
(V)
1.5
tpHL
tpLH
1
0.5
0
-0.5
0
0.5
1
1.5
2
t (sec)
Digital Integrated Circuits
2.5
x 10
Inverter
-10
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4
Design for Performance
Keep capacitances small
l Increase transistor sizes
l
» watch out for self-loading!
l
Increase VDD (????)
Digital Integrated Circuits
Inverter
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Delay as a function of VDD
5.5
5
4.5
3.5
3
p
t (normalized)
4
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
Digital Integrated Circuits
DD
1.8
2
2.2
2.4
(V)
Inverter
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5
Device Sizing
3.8
x 10
-11
(for fixed load)
3.6
3.4
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
2
4
6
8
S
10
Digital Integrated Circuits
12
14
Inverter
© Prentice Hall 1999
NMOS/PMOS ratio
5
x 10
-11
tpHL
tpLH
4.5
β = Wp/Wn
tp
4
p
p
3
t (sec)
t (sec)
3.2
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
b
Digital Integrated Circuits
Inverter
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6
Impact of Rise Time on Delay
0.35
tpH L (nsec)
0.3
0.25
0.2
0.15
Digital Integrated Circuits
0
0.2
0.4
0.6
trise (nsec)
Inverter
0.8
1
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Inverter Sizing
Digital Integrated Circuits
Inverter
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7
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Inverter Delay
• Minimum length devices, L=0.25µm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 W
RP = Runit  P
 Wunit



−1
 W 
≈ Runit  N 
 Wunit 
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
Digital Integrated Circuits
2W
W
−1
= RN = RW
tpLH = (ln 2) RPCL
C gin = 3
Inverter
W
Cunit
Wunit
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8
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
Digital Integrated Circuits
Inverter
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Inverter with Load
CP = 2Cunit
Delay
2W
W
Cint
CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
9
Delay Formula
Delay ~ RW (C int + C L )
t p = kR W C int (1 + C L / C int ) = t p 0 (1 + f / γ
)
Cint = γCgin with γ ≈ 1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C

t pj ~ Runit Cunit 1 + gin, j +1 
 γC gin, j 


N
N 

C
t p = ∑ t p , j = t p 0 ∑ 1 + gin, j +1 , C gin, N +1 = C L
 γC

j =1
i =1 
gin , j 
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
10
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j = C gin , j −1C gin, j +1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Optimum Delay and Number
of Stages
When each stage is sized by f and has same eff. fanout f:
f
N
= F = C L / C gin ,1
Effective fanout of each stage:
f =NF
Minimum path delay
(
t p = Nt p 0 1 + N F / γ
Digital Integrated Circuits
Inverter
)
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11
Example
In
Out
1
C1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f =38=2
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
C L = F ⋅ Cin = f N Cin with N =
ln f
t p 0 ln F  f
γ

+
γ
 ln f ln f
∂t p t p 0 ln F ln f − 1 − γ f
=
⋅
=0
∂f
γ
ln 2 f
(
)
t p = Nt p 0 F 1/ N / γ + 1 =
For γ = 0, f = e, N = lnF
Digital Integrated Circuits
Inverter



f = exp(1 + γ f )
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12
Optimum Effective Fanout f
Optimum f for given process defined by γ
f = exp(1 + γ f )
fopt = 3.6
for γ=1
Digital Integrated Circuits
Inverter
© Prentice Hall 1999
Impact of Self-Loading on tp
No Self-Loading, γ=0
With Self-Loading γ=1
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
u
Digital Integrated Circuits
Inverter
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13
Normalized delay function of F
(
t p = Nt p 0 1 + N F / γ
Digital Integrated Circuits
)
Inverter
© Prentice Hall 1999
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
Digital Integrated Circuits
64
22.6
Inverter
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