IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 11, NO. 1, JANUARY/FEBRUARY 2005
173
Integrated Transceivers for Optical Wireless
Communications
Dominic C. O’Brien, Grahame E. Faulkner, Emmanuel B. Zyambo, Kalok Jim, David J. Edwards, Paul Stavrinou,
Gareth Parry, Jacques Bellon, Martin J. Sibley, Vinod A. Lalithambika, Valencia M. Joyner, Rina J. Samsudin,
David M. Holburn, and Robert J. Mears
Abstract—Line-of-sight free-space optical links can provide extremely high bandwidth communications, but this usually requires
that transmitter and receiver are precisely aligned. In order to
allow terminals to be mobile, links must be able to track users
within their field of view so that the link is maintained. There
are various means to do this, but all require complex subsystems
with a number of different optical, optoelectronic, and electrical
components. In this paper, a solid-state tracking architecture is
introduced and a seven-channel tracking system demonstration
described. The system is designed to operate at 155 Mb/s and
is, to the best of our knowledge, the first that uses an integrated
approach. Arrays of novel resonant cavity LED (RCLED) emitters
that operate at 980 nm are used as sources. These are flip-chip
bonded to arrays of CMOS driver circuits and integrated with
the necessary transmitter optics. The receiver uses a back-illuminated detector array flip-chip bonded to arrays of custom CMOS
receivers. All these components are custom and have performance
substantially better than nonoptimized commercially available
components.
In the paper, the design and fabrication of the optics, optoelectronics, and electronics required for this is described. Successful
operation of all the subsystems is detailed, together with results
from an initial link demonstration.
Index Terms—Free-space optical communications, optical
communications, optical wireless, optoelectronic devices, optoelectronic integration.
I. INTRODUCTION
W
IRELESS optical channels have the potential to offer
wireless connection with data rates far in excess of that
available using RF approaches, due to both the higher carrier
frequency and the limited availability of free spectrum in the
crowded RF frequency regions [1]. However, multipath dispersion and limited receiver sensitivity when compared with radio
LANs requires that line-of-sight (LOS) paths be established between transmitter and receiver in order to achieve high bit rates.
Maintaining a link between a base station and mobile terminal
Manuscript received May 4, 2004; revised November 10, 2004. The work of
R. J. Samsudin was supported by the Malaysian Prime Minister’s Fellowship
Exchange Program.
D. C. O’Brien, G. E. Faulkner, E. B. Zyambo, K. Jim, and D. J. Edwards are
with the Department of Engineering Science, Oxford OX1 3PJ, U.K. (e-mail:
dominic.obrien@eng.ox.ac.uk).
P. Stavrinou and G. Parry are with the Centre for Semiconductor Materials
and Devices, Blackett Laboratory, Imperial College, London SW7 2BZ, U.K.
J. Bellon and M. J. Sibley are with the Department of Electronic and Electrical
Engineering, University of Huddersfield, Queensgate, Huddersfield HD1 3DH,
U.K.
V. A. Lalithambika, V. M. Joyner, R. J. Samsudin, D. M. Holburn, and R.
J. Mears are with the Cambridge University Department of Engineering, Cambridge CB2 1PZ, U.K.
Digital Object Identifier 10.1109/JSTQE.2004.841471
Fig. 1. System architecture.
while the terminal moves within the optical wireless cell then
becomes a major problem. Various approaches to tracking the
movement of terminals and directing light toward them have
been taken. The use of angle diversity is demonstrated in [2],
and the concept of an imaging (essentially tracking) receiver
is reviewed in [3]. The use of multiple transmitter and receiver
beams is described in [4]. There are few experimental demonstrations of such systems. In [5], tracking in one dimension
is demonstrated, and the first experimental demonstration of
tracking in two dimensions (to the best of our knowledge) is described in [6]. These highlight the problems of producing such
an integrated system, in that there are a large number of disparate optical, optoelectronic, and electrical components.
This paper describes work to design integrated transceiver
components and is arranged as follows. In Section II, the system
architecture and approach to integration is described. In Section III, the design of the system is discussed; and subsequent
sections then describe the design and fabrication of the individual components. Section VII describes results obtained thus
far, and Section VIII draws conclusions and discusses directions
of future work.
II. SYSTEM OVERVIEW
Fig. 1 shows the system under development. A base station
is situated above the coverage area, and this uses a two-dimensional (2-D) array of semiconductor sources that emit normal
to their substrate. A lens system is used to map sources in the
emitter array to a particular angle, thus creating complete coverage of the space. The use of an array of sources both minimizes
power transmitted, as sources not pointing at a terminal can be
deactivated, and offers the potential for each source to transmit
different data.
1077-260X/$20.00 © 2005 IEEE
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Fig. 2. Approach to integration.
Each terminal within the space has a lens system that collects
andfocusesthebeamoflightontoaparticulardetectorwithinadetector array. The resulting electrical signal is amplified and a data
stream is extracted from it. The detector array allows the angle of
arrival of the beam to be determined and, hence, the direction of
the required uplink (from terminal to base station). The system is,
therefore, a combination of a tracking transmitter and tracking receiver. This has the potential to maximize the power available at
the receiver (when compared with combinations of tracking and
nontracking components). Each detector has low capacitance and
a narrow field of view, thus increasing channel bandwidth and reducing the effect of ambient illumination.
Fig. 2 shows the approach taken to integration. Arrays of
sources that emit through their substrate are flip-chip bonded to
arrays of driver electronics fabricated in a “commodity” CMOS
process. This provides the transmitter functionality, and a similar approach is taken with the receiver photodetector array.
Particular features of this approach make it amenable to largescale integration.
1) Scalability. The flip-chip bonding of drivers and receivers
directly under the detector arrays within the area required
ensures the basic driver and receiver units are scalable to
large numbers of elements. This integration can take place
at a wafer scale.
2) Functionality. The CMOS process used for the electronics
allows complex digital control circuitry to be integrated
with the analog receiver and transmitter electronics
3) Cost. The electronic circuits use a low-cost CMOS
process, and the optoelectronic devices can be produced
and tested on a wafer scale [7].
III. SYSTEM DEMONSTRATION
In order to demonstrate these ideas, a seven-channel demonstration has been fabricated and tested. The system is designed
to operate at 155 Mb/s, using Manchester coding. This was
chosen because it is relatively robust to any low-frequency electrical noise caused by inadvertent detection of ambient artificial
illumination, due to the small amount of energy in its spectrum
that is present at these low frequencies. Manchester coding also
allows straightforward clock recovery, and as the focus of the
work described here is the transceiver components, more complex codes were not considered.
The link is designed to operate over several meters using approximately 0 dBm of transmission power, with a target receiver
sensitivity of approximately 30 dBm, and will track over a
field of view of approximately 14 at this distance.
The system operates at 980 nm as substrate emitting devices
were available at this wavelength, and the materials systems
required to fabricate these are well understood. At wavelengths
beyond 1400 nm, eye safety regulations allow more than an
order of magnitude more power to be emitted than at 980 nm,
and the receivers are designed to operate at these longer
wavelengths. Suitable arrays of surface normal emitters are
unavailable, however. Initial examples of emitters operating at
this wavelength have been grown under the program, but are
not at a sufficiently advanced level for integration.
In the following sections each of the components is described
in detail.
IV. OPTOELECTRONIC DEVICES
A. Emitters
The system requires 2-D arrays of surface emitters that emit
through the semiconductor substrate, thus making devices suitable for flip-chip bonding. Both vertical cavity surface-emitting
lasers (VCSELs) [8] and resonant cavity LEDs (RCLEDs) [9],
[10] are suitable for this application. In this case, RCLEDs have
sufficient modulation bandwidth, an emission profile that can
be optimized for this application, and a simpler structure than
that a VCSEL. This is particularly relevant for operation at long
wavelength, where growth of the mirror structures represents a
considerable technical challenge.
1) Device Structure: Fig. 3 shows the structure of the LED.
The emitter devices are metal/semiconductor hybrid RCLEDs
designed on the basis of previous work [9], [11] . The structures
are epitaxially grown by molecular beam epitaxy (MBE) on
double polished n+ GaAs wafers and emit through the substrate,
which is nominally transparent at these wavelengths. The active
As (
layers in the cavity are three or four strained In Ga
) quantum wells (QWs) clad by GaAs barrier layers. The
bottom mirror is a multiple quarter-wave stack of GaAs/AlAs
layers, known as a distributed Bragg reflector (DBR). The cavity
is completed by the deposition of a metal mirror on the upper
surface of the multilayer structure shown. For this device structure, the typical on-axis linewidth is 20–30 nm around 980 nm.
A key property of RCLEDs for this type of application is the
ability to determine the emission angular beam profile by designing the emission wavelength of the QWs inside the cavity
to be approximately 10–20 nm shorter than the resonance wavelength of the cavity. The emission wavelength is predominantly
governed by the width of the QWs and the indium mole fraction,
while the cavity resonance wavelength is determined by the aggregate optical thickness of the layers between the metal top
mirror and the bottom DBR. The offset in the two wavelengths
is known as detuning, and the degree of detuning affects the
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Fig. 3. Structure of RCLED.
Fig. 5. (a) DC characteristics of RCLED. (b) Eye diagram for RCLED
modulated at 310 Mb/s. (c) Simulated and measured beam profile of RCLED.
Fig. 4. RCLED array suitable for flip-chip bonding.
beam profile of the emission. A detailed simulation of the optical system was undertaken in order to determine the optimum
detuning for this application, and this is described in Section VI.
Wafers were grown at the University of Sheffield, Sheffield,
U.K., using metal–organic vapor phase epitaxy (MOVPE),
and areas of the wafer with the optimum degree of detuning
( 20 nm) identified. Appropriate material was then processed
into seven-element hexagonal pitch arrays using standard
lithography techniques. The devices are on a 400- m pitch, and
are suitable for flip-chip bonding. Fig. 4 shows one example;
the central seven contacts are to the p-device terminal and the
peripheral contacts are used as a common cathode connection.
Additional thin ( 20-nm) layers of platinum were used to
protect the contacts on the device from the solder used in
flip-chip bonding.
2) Device Performance: The optical power versus current
and voltage versus current characteristics for the RCLEDs for a
typical device are shown in Fig. 5(a). Device efficiency was approximately 0.6% for 100-mA drive current, with output power
of approximately 1.75 mW and a slope resistance of around 3
for devices that gave the maximum output optical power. Further optimization should lead to more efficient devices, but these
devices have sufficient performance for this application.
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Fig. 6. Photodetector structure.
Fig. 7.
Fig. 5(b) shows an eye diagram for a device that is biased
using a constant current driver and modulated using a 310-Mb/s
pseudorandom binary sequence. This shows that the RCLEDs
have sufficient bandwidth for this application. Fig. 5(c) shows
the simulated and actual measured beam profile from a typical
device. The measured profile is a closest match to the simulated result for the highly detuned devices, showing the particular array uses a highly detuned portion of the wafer.
B. Detectors
1) Detector Structure: The system requires a close-packed
array of hexagonal detectors that are illuminated through their
substrate, and the performance of these detectors is one of the
key design constraints. In a system where the transmitter beam is
larger than the receiver collection aperture, the power collected
will usually be proportional to the detector area for any given
optical system. However, increasing detector area increases
the capacitance presented to the system preamplifiers, which
reduces the available bandwidth. A major focus of this work
has been in optimizing detector structures for this free-space
application. An optimum detector for optical wireless would
balance transit time and capacitance controlled bandwidth and
achieve maximum area for a given bandwidth. Epitaxially
grown structures such as that grown here allow independent
control of depletion width and field by the growth of Intrinsic
(I) regions of the correct thickness, so that this should be
possible. Preliminary modeling of an InGaAs p-i-n structure
shows that a 30- m I region could offer bandwidths of 1
GHz for a 1-mm device (assuming a 50- amplifier input
impedance). This is a formidable challenge, due to the problems
in controlling doping in such thick structures, and in the devices
grown for this work, the I region was limited to a 5- m layer.
Optimized detectors might also include filtering layers to reduce
the noise from optically broadband ambient illumination, and
preliminary structures that show filtering action have been
grown [12]. However, these proved to be too capacitive and
simpler p-i-n structures were grown for the demonstrator.
Fig. 6 shows the p-i-n photodiode structures grown for the
receiver subsystem. These are substrate illuminated InGaAs/InP
p-i-n diodes grown on InP substrates by MOVPE. These are
Seven-channel detector array suitable for flip-chip bonding.
designed for substrate illumination and operation in the range
from 980 to beyond 1500 nm. The structure incorporates a top
contact that also acts as a mirror, which ensures that unabsorbed
photons are reflected back into the detectors, thus increasing
their responsivity.
Wafers were processed into seven-element hexagonal pitch
arrays, with close-packed devices on a 500- m pitch. Device
size and, hence, pitch was chosen from optical design considerations and to ensure the maximum capacitance presented to the
receivers was within their design specification.
2) Device Performance: Devices typically have a measured
capacitance of 5.2 pF (at 4-V reverse bias) compared with a
calculated value of 5.1 pF for a fully depleted I region. The slight
discrepancy is due to the reduced bias voltage (4 V) compared
to that required to fully deplete the I region (estimated to be
approximately 8 V). This is a factor of five lower than typical
commercial devices, showing the importance of optimizing
devices for this application. The measured responsivity was 0.39
A/W at 980 nm, compared with a theoretical maximum of 0.79
A/W. Two factors contribute to the reduction in responsivity: the
InP substrate has significant absorption at this wavelength, and
the Fresnel losses ( 30 ) as light enters the semiconductor
substrate reduce the illumination incident on the p-i-n structure.
An estimate of the likely reduction these two effects produce
leads us to believe the detectors are operating efficiently.
Fig. 7 shows a picture of a seven-channel detector array with
a 500- m pitch that is suitable for flip-chip bonding. As was the
case for the emitters, a number of protective metal layers were
grown on top of the basic detector structure in order to stop gold
diffusing into the solder bumps.
V. SILICON DESIGN
A. Transmitters
Fig. 8(a) shows a block diagram of the RCLED driver circuit
that is used to drive each source. The core function of the driver
is voltage-to-current conversion to produce modulating forward
current from a voltage data signal. The modulation circuit in
the driver consists of a voltage-to-current transducer and a
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Fig. 8. (a) RCLED driver circuit block diagram.(b) Eye diagram derived from optical output of RCLED and driver modulated at 100 Mb/s.
current mirror with a suitable amplification factor to produce
the necessary output levels. In addition, the driver incorporates
integrated speedup capabilities aimed at improving the optical
source’s turn-on and turnoff times. These are implemented
using three circuits: namely, the bias, charge injection, and
charge extraction circuits, the latter two employing the use
of novel pulse generators. The bias circuit supplies a small
quiescent current to the RCLED at all times and, thus, keeps
the space-charge capacitance of the source constantly charged.
This effectively reduces the delay of carrier injection into the
active region [13] after stimulation of the optical source with a
pulse, thereby minimizing delay in light output. Charge injection works by introducing a large current spike at each positive
edge of the data signal, which reduces the optical rise time of
the emitter [14]. Similarly, charge extraction improves optical
fall time by sweeping out carriers from the active region of the
emitter [15], [16] through the introduction of a negative current
spike at each falling edge of the data signal. Charge injection
and extraction are implemented using pulse generators that
consist of delay elements and logic gates [as shown in Fig. 8(a)]
to generate short-duration digital pulses at specific instances
of the data signal. The charge injection pulse generator uses
a NAND gate to trigger on the positive edge of the data signal,
which is the instance at which the emitter must turn on. This
then creates a short-width pulse that is subsequently converted
to a large current spike coinciding with the turn-on instance of
the light source. The generator for charge extraction utilizes a
NOR gate to generate a short-width pulse on the falling edge
of the data signal coinciding with the turnoff instance of the
source. Each driver is designed to source 100 mA of forward
current at 1.5 V forward voltage, which would yield 2.5 mW of
optical output power with device efficiencies of around 1.7%.
Single channel driver test structures have been fabricated in
a CMOS 0.7- m technology and tested using infrared LEDs
[17]. DC tests show that the CMOS devices can source the
necessary current to drive and prebias the RCLEDs. Fig. 8(b)
shows a 100-Mb/s [nonreturn-to-zero (NRZ)] eye diagram from
a CMOS driver and RCLED showing excellent performance.
This may be limited by inductance in the wirebonds between
driver and source. There is an estimated 6 nH of inductance,
which combined with the 100-mA drive current that is sourced
in several nanoseconds might lead to a substantial drop in the
2 V applied to the LEDs. When the driver is integrated with
the RCLEDs using flip-chip bonding, we expect to see much
improved performance. Such fully integrated devices are now
complete and awaiting testing.
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Fig. 9. Transimpedance amplifier circuit diagram.
B. Receivers
1) Transimpedance Amplifier: A major effort has been the
design of the receiver preamplifier circuit, shown in Fig. 9. The
details of its design are outlined in [18]. A transimpedance amplifier structure is used and consists of a three-stage voltage amplifier with shunt resistive feedback. This approach provides the
best compromise in terms of noise, gain, and bandwidth, all of
which are influenced by the capacitance of the detector. Each
stage of the amplifier is identical and consists of an inverter stage
with diode-connected load. This topology has several design advantages. The inverter, compared to a single device, produces a
higher transconductance for a given bias current. Furthermore,
the diode-connected load is used to trade off the gain of the unloaded inverter for increased small-signal bandwidth. The transimpedance bandwidth is governed by the input capacitance,
open loop gain of the amplifier, and the feedback resistance. In
order to account for variances in the detector capacitance and
parasitics, a variable feedback resistor is implemented using a
positive channel MOS (PMOS) transistor biased in the linear region. The resistance can be varied by applying a voltage bias
to the gate of the transistor in order to achieve the required bandwidth and maintain stability over a range of 2–10 pF of capacitance at the input.
The preamplifier circuit was fabricated using a 0.7- m
CMOS process technology, offered through the Europractice
initiative. With a total input capacitance (including detector
and parasitics) of 10 pF, the transimpedance amplifier achieves
a measured bandwidth of 217 MHz and transimpedance gain
of 4.2 k . This compares extremely favorably with [19] which
reports a 156-Mb/s receiver with a 2.5-pF input capacitance.
Noise performance of the circuit was measured by comparing
the output noise spectra with and without input signal in order
to remove the effect of measurement noise, as proposed by
Carruthers [20]. The measured input-referred noise current
density is 5.92 pA Hz. At a bandwidth of 217 MHz, using
the measured detector responsivity of 0.39 A/W, this implies
a sensitivity of approximately 29 dBm at 980 nm. Fig. 10(a)
shows a 310-Mb/s eye diagram receiver output, showing good
performance at this data rate. Calculations indicate that a
variation in optical power of approximately 22 dB can be accommodated by the preamplifier, but due to the limited source
power available, this was only verified by measurement over a
7.5-dB range.
Fig. 10. Eye diagrams for transimpedance amplifier operating at 310 Mb/s and
later design operating at 1 Gb/s.
2) Gigabit Receiver: In order to investigate extending the
proposed receiver architecture to Gb/s data rates, a receiver IC
operating at 1 Gb/s was developed and realized in a 0.35- m
CMOS process. The chip includes two transimpedance amplifier stages; one is a common-source input stage, and the other
a current-mode common-gate input stage. The low input resistance of the common-gate stage has many potential advantages, as the large detector capacitance can be decoupled from
the bandwidth and gain of the preamplifier, ultimately leading
to lower noise. Theoretical analysis presented in [21] shows
that the performance improvement offered by the common-gate
stage is limited when implementing the receiver in a standard
CMOS technology operating at a single, low supply voltage.
Furthermore, isolating the large photodiode capacitances expected in optical wireless receivers can lead to large junction
capacitances that further degrade performance and hinder design optimization. Electrical measurements were carried out on
both preamplifier topologies using a detector emulation circuit
at the input of each channel with an associated capacitance of 6
pF. Best results were achieved on the common-source channel.
The common-source preamplifier achieves a gain of 44.6 dB,
3-dB bandwidth of 500 MHz, and an input-referred current
noise power spectral density (PSD) of 14.8 pA Hz; good eye
openings have been demonstrated at bit rates up to 1 Gb/s as
shown in Fig. 10(b).
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Fig. 11. (a) Diversity receiver block diagram. (b) Transconductance amplifier
schematic.
3) Diversity Receiver: In order to recover data from the incoming optical power, the signal from the desired detector or
group of detectors must be routed to the data recovery circuit.
A combiner circuit that allows arbitrary combination of signals from three preamplifiers has been designed, fabricated, and
tested. Fig. 11(a) shows a block diagram of the selector combiner circuit. Each detector drives a dedicated preamplifier circuit. Channel selection and combination is performed using a
current bus-bar approach. The preamplifier circuit, with output
voltage Vpre, drives a transconductance stage (Gm) producing
an output current Iout.
The transconductance stage is shown in Fig. 11(b) and is implemented using an n-type differential pair with an active current mirror load. The preamplifier output signal Vpre is applied
directly to the noninverting input terminal and passed through
an RC low-pass filter to supply the preamplifier dc output signal
to the inverting input terminal. This low-pass filter and differential pair combination has a bandpass filtering characteristic with
the lower cutoff frequency set by the low-pass filter cutoff. In
terms of noise performance, this transconductance approach can
considerably reduce low-frequency 1 receiver noise and enhance sensitivity. To avoid signal distortion, the low-pass filter
cutoff frequency is set well below frequencies expected at the
receiver input.
The output current signals are steered by switches to a current
bus-bar, which serves as a current summing junction. These
switches are controlled by the SEL signals derived from the external control circuit. The SEL signal is assigned based on the
signal level Vpre at the output of the preamplifier circuit. The
selector–combiner circuit can select the channel with the best
signal-to-noise ratio (so-called select best combining) or all
channels having appreciable signal levels and combine them
with equal gain. Details of this architecture can be found in [21].
Fig. 12. Received electrical signals for three-channel combiner operating at
200 Mb/s, showing two individual channel signals and the resulting combined
signal.
This was fabricated using a 0.7- m CMOS process technology.
Fig. 12 illustrates equal gain combining of two input signals.
4) Seven-Channel Receiver: Flip-chip packaging allows
integration of optoelectronic ICs directly to the supporting
CMOS electronics with low parasitics, enabling significant
improvements to the design and implementation of scalable
optical receiver arrays. The flip-chip compatible receiver IC
was realized using a 0.7- m CMOS process. The chip is arranged into three separate receiving segments to give greater
flexibility in performing optical measurements. There are two
three-channel combiner circuits consisting of the preamplifier
and selector–combiner circuits presented above; a single channel
with preamplifier and buffer circuit is also included. Integration
of this chip with the detector array is detailed in Section VII.
VI. OPTICAL SYSTEM DESIGN
A. Design Considerations
The optical system can be thought of as performing a spaceangle mapping at the transmitter and the inverse mapping at the receiver.Transmitteropticalelements arerelativelystraightforward
to design, and the system is largely constrained by the receiver.
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Fig. 13. (a) Schematic of optical system. (b) Simulated received power as
receiver tracks across a coverage cell for different degrees of RCLED cavity
detuning.
Constant radiance considerations allow an estimate of the
maximum optical “gain” that can be obtained at the receiver.
High gain (defined as input aperture area/output area) is desirable, but this severely constrains the angle of incidence at
which incident optical power is all collected and focussed onto
the detector array. In practice, designing systems that approach
these limits is challenging and, in our case, further constrained
by the use of commercially available singlet lenses in the first
demonstration system. For a high-bandwidth system detector,
size is necessarily constrained to limit capacitance, so that a
large number (perhaps several hundred) detectors will be required for a “full” receiver design with the ability to accept light
over a wide range of angles of incidence. This further reinforces
the integrated approach taken here, as it is believed this approach
is scalable to these numbers of detectors.
A combination of ray-tracing packages and custom design
tools are used to optimize the optical system. The RCLED array
geometries, beam profiles, and the passage of light through the
system is simulated. This allows the optimum profile and geometry to be obtained, as well as variation in detected power as the
receiver tracks across the coverage area. Fig. 13(a) shows the
final optical design of the system. Fig. 13(b) shows the power
received as the receiver is translated across a coverage cell for
RCLEDs with different degrees of detuning This shows that
greater detuning and, hence, a more divergent beam [the simulated beam profiles are shown in Fig. 5(c)] is advantageous, as
it increases the power received at the cell edge and reduces the
dynamic range required from the receiver.
Fig. 14. (a) Measured illumination profile from transmitter (profile is shown
for seven-channel array with some nonworking elements). (b) Measured
received signal as illumination angle is changed, showing signal is detected by
different elements in array according to angle of incidence of illumination.
B. Measurements
In order to test the performance of the optical systems, arrays
of sources and detectors were mounted onto the optomechanical systems and the system was tested without data modulation.
Fig. 14(a) shows an angle scan of transmitter illumination; the
transmitter assembly is mounted on a goniometer that is scanned
in azimuth and elevation. The coverage map shows received intensity using a decibel scale normalized to the maximum value
versus azimuth and elevation (in degrees). This shows a variation in illumination of 6 dB between maximum and minimum
points. The simulated variation in power from cell center to edge
for a highly detuned device is approximately 18 dB, as can be
seen in Fig. 13(b). This simulation does not takes into account
illumination from adjacent cells, which might increase the illumination at the cell edge by a factor of three (4.7 dB), thus
implying an overall variation of approximately 13 dB. The measured and simulated values are not exactly comparable, as the
measurement does not take into account loss in the receiver optical system. However, it does indicate that the wider than predicted beam profile of the RCLEDs leads to a more uniform
coverage than predicted.
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Fig. 16.
181
Optomechanical arrangement for link.
TABLE I
SIMULATED AND MEASURED LINK BUDGETS
Fig. 15. Flip-chip integration and packaging of seven-channel receiver.
The receiver system is tested by illuminating the aperture of
the receiver in a direction along the optical axis of the system,
and then rotating the receiver and recording the signal from the
central and two adjacent detectors in the hexagonal array [22].
As the angle is increased, light should strike the outer detectors, thus demonstrating the angle position mapping. Fig. 14(b)
shows the plots of detected photocurrent for each of the detectors as the angle of incidence is changed. When the illumination
is on axis, the signal is all received from the central detector, and
this changes to adjacent detectors when the angle of incidence
changes. These measurements indicate the optical system is performing to specification.
VII. INTEGRATION
Fig. 15 shows a schematic of the integration approach used
for the seven-channel receiver (a similar approach is using the
transmitter). Tin–lead solder bumps were placed on the CMOS
ICs using a proprietary process. This uses an electroless plating
process to deposit a protective layer of nickel on the underlying
CMOS bond pads. Individual solder balls are then placed and
laser welded to the IC. In the case of the transmitter, these are
approximately 120 m in diameter, with 200 m used for the
larger receiver. Parts are then aligned in a reflow-aligner and the
resulting hybrid placed in an IC package. Connections are made
around the periphery using wirebonds.
Fig. 16 shows how the optomechanical system used to integrate the optical system with the optoelectronic hybrids are
aligned with the optical system in both receiver and transmitter.
At present, the hybrids are complete and awaiting testing before
integration with the optical system.
VIII. RESULTS AND DEMONSTRATION LINK
The individual components required for the transceivers have
been tested, and the results from measurements allow the performance of the link to be inferred. Table I shows a comparison between the simulated link performance and that inferred
from measurements. As can be seen from the table, the expected
performance is better than that predicted by simulation. This
is largely due to the higher output power of the RCLEDs than
the conservative estimate made at the design stage. It should
be noted that this calculation assumes power from three transmitters is collected by the receiver at the cell edges, where the
signal is weakest; in the case of a single transmitter illuminating
the cell edge, the margins drop by 4.7 dB.
Measurements indicate that a dynamic range of approximately 6 dB is required to account for the variation in received
power as the receiver moves across the cellular illumination
pattern, and experimental measurements indicate that this can
be accommodated by the transimpedance amplifier. Calculation
indicates the receiver has a dynamic range of approximately
182
Fig. 17.
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 11, NO. 1, JANUARY/FEBRUARY 2005
Eye diagram for hybrid integrated link.
22 dB, which should be sufficient to allow correct operation
with large variations in link length as well as coverage at a
particular distance. Further variation might be accommodated
by controlling the transmitter power levels using received signal
strength information from the distant transceiver.
In order to test the individual components in combination, the
CMOS electronics was integrated with the optoelectronics using
wirebonding techniques, within a large IC package. Simple optics was used at transmitter and receiver, and transmitter and
receiver aligned over a short distance. Fig. 17 shows an eye diagram from a hybrid demonstration, showing data link operation
at 100 Mb/s.
The link uses entirely custom components, and these results
are the first from such a system. These are excellent results,
given the added inductance and shielding problems with these
integration techniques. We, therefore, expect the integrated
demonstrator to show much improved performance.
The link demonstration uses external circuitry to provide the
control signals to the driver and receiver circuits, and in this preliminary work these are set manually. A more advanced system
would incorporate channel power control, signal strength detection, and other link management functions within the transceiver
integrated circuit. These were beyond the scope of this initial
demonstration, but the use of a commodity CMOS process offers the possibility of such a high level of integration.
IX. CONCLUSION
Results from this work show that high-performance components which are optimized for free-space optical communications can be realized using well-developed processes and that
these when integrated should provide transceivers with good
overall performance. The receivers are the fastest reported for
such high-input capacitance and show performance much beyond that of nonoptimized commercially available components.
Similarly, the detectors show lower capacitance than those available commercially, and modeling suggests further substantial
gains are possible.
They also show that there are significant challenges for optical wireless, perhaps the major one being scalability. As a first
estimate, assuming that each transceiver has a 90 field of view
(FOV) in all directions and each cell has a 4.5 FOV, approximately 200 channels would be required. This is largely due to
detector capacitance and the need to limit this by fabricating
small detectors. At present, the receiver circuits that we have
designed are not scalable, in that the transimpedance amplifiers
have a slightly larger area than the detectors, especially when including space for the flip-chip bonding pads. The development
of detectors with lower capacitance per unit area and the use of
a finer feature size CMOS process should allow the fabrication
of channel electronics beneath the optoelectronic emitter or detector footprint and an increase in the FOV covered with each
channel. While these represent significant technical challenges,
the basic approach that we have taken should allow scaling to the
large number of channels that an indoor transceiver will require.
This work has demonstrated gigabit-per-second operation of
a high-input capacitance receiver, which is far in excess of that
available using current wireless LAN standards. As the additional “cost” of an optical channel is small, data rates can be
increased at the cost of detector size, and preliminary simulations show that with the further optimization of receivers and
detector structures this approach should be scalable to gigabitper-second channel capacities with large numbers of detectors.
ACKNOWLEDGMENT
The authors would like to thank G. Hill, C. Roberts,
J. Roberts, and C. Button for growing and processing the
optoelectronic devices.
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Dominic C. O’Brien received the M.A. and Ph.D. degrees from the
Department of Engineering, University of Cambridge, Cambridge, U.K. in
1991 and 1993, respectively.
He is a currently a Lecturer in engineering science at the University of
Oxford, Oxford, U.K., where he leads the Optical Wireless Communications
Group. From 1993 to 1995, he was a NATO Fellow at the Optoelectronic
Computing Systems Center, University of Colorado. He is the author or
coauthor of approximately 70 publications or patents in the area of optics
and optoelectronics. His research interests are focused on the field of optical
wireless systems, including integrated transceiver components for high-speed
networks, retroreflecting transceivers, optical channel characterisation, and
aspects of optoelectronic component integration.
Grahame E. Faulkner received the B.Sc. degree (with honors) in physics
and microelectronics from Oxford Brookes University, Oxford, U.K.
He is currently a Research Assistant in the Department of Engineering Science, Oxford University, Oxford. He has coauthored several papers in the field
of optical wireless communications, optical interconnects, and optoelectronic
integration.
Emmanuel B. Zyambo, photograph and biography not available at the time of
publication.
Kalok Jim, photograph and biography not available at the time of publication.
183
David J. Edwards, photograph and biography not available at the time of publication.
Paul Stavrinou, photograph and biography not available at the time of publication.
Gareth Parry is a Professor of applied physics at Imperial College, London,
U.K. Prior to taking up this appointment, he was the Rank Foundation Chair in
Electro-Optic Engineering at Oxford University, Oxford, U.K., and a Professor
of electronic engineering at University College London. His research interests
include semiconductor optoelectronic devices and their application in communication and interconnect.
He is a Fellow of the IEE, Fellow of Institute of Physics and Fellow of the
Royal Academy of Engineering.
Jacques Bellon, photograph and biography not available at the time of
publication.
Martin J. Sibley received the B.Sc.(Hons.) degree in electrical engineering
and the Ph.D. degree from Huddersfield Polytechnic, Huddersfield, U.K., in
1981 and 1984, respectively.
From 1981-1984, he remained at Huddersfield where he was sponsored by
British Telecom Research Laboratories to research the design of common-collector input preamplifiers for use in optical receivers. This work led to the first
preamplifier design in ic. He is now a Reader at the University of Huddersfield,
where his research interests include pulse position modulation, preamplifier design for optical receivers, optical wireless LANs ,and free-space optical links.
Dr. Sibely was awarded the Marconi Premium from the Institute of Electronic
and Radio Engineers for the best engineering paper published in their Proceedings in1985.
Vinod A. Lalithambika received the M.Phil. and Ph.D. degrees from the University of Cambridge, Cambridge, U.K. He was a Malaysian Commonwealth
Scholar at the University of Cambridge from 2001 to 2002.
His research interests include opto-electonic integrated circuits, RF circuit
design, cipolar and CMOS circuit design.
Valencia M. Joyner received the S.B. and M.Eng. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology,
Cambridge, MA, in 1998 and 1999, respectively. She is currently working toward the Ph.D. degree in the Department of Engineering, University of Cambridge, Cambridge, U.K., where her research focus is on the design of high
frequency receiver ICs in CMOS for optical wireless networks.
In 1998, she was an intern at Toshiba Corporation, Yokohama, Japan, where
she worked on sense amplifier architectures for high-speed SRAM chips.
Ms. Joyner is a Marshall Scholar and a National Science Foundation Graduate
Research Fellow
Rina J. Samsudin received the B.Sc. degree in electrical engineering from
the Massachusetts Institute of Technology, Cambridge, MA, in 1999, and the
M.Phil. and Ph.D. degrees from Cambridge University, Cambridge, U.K., in
2001 and 2004 respectively.
David M. Holburn received the B.A. degree in electrical sciences and the
Ph.D. degree in electrical engineering from the University of Cambridge,
Cambridge, U.K., in 1975 and 1979, respectively.
From 1979 to 1986, he worked first as a Research Associate in Microelectronics, then as Lecturer in Computer Science at Westfield College, University
of London, London, U.K., where he has been a Senior Lecturer in the University
Engineering Department since January 1986.
He is a Member of the Institution of Electrical Engineers and a Chartered
Engineer.
Robert J. Mears, photograph and biography not available at the time of
publication.