SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986
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•
•
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SN54ALS114A . . . J PACKAGE
SN74ALS114A . . . D OR N PACKAGE
(TOP VIEW)
CLR
1K
1J
1PRE
1Q
1Q
GND
6
7
1
2
3
4
5
14
13
12
11
10
9
8
V
CC
CLK
2K
2J
2PRE
2Q
2Q
SN54ALS114A . . . FK PACKAGE
(TOP VIEW)
These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The SN54ALS114A is characterized for operation over the full military temperature range of − 55 ° C to 125
°
C. The SN74ALS114A is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
PRE
L
CLR
H
INPUTS
CLK
X
J
X
K
X
OUTPUTS
Q
H
Q
L
H L X X X L H
L
H
H
H
H
L
H
H
H
H
X
↓
↓
↓
↓
X
L
H
L
H
X
L
L
H
H
H†
Q0
H
L
H†
Q0
L
H
TOGGLE
H H H X X Q0 Q0
† The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at Preset and
Clear are near VIL maximum. Furthermore, this configuration is nonstable; that is, it will not persist when either Preset or
Clear returns to its inactive (high) level.
1J
NC
1PRE
NC
1Q
CLR
CLK
1PRE
1J
1K
2PRE
2J
2K
1
13
4
3
2
10
11
12
6
7
4
3 2 1 20 19
18
5 17
16
15
8 14
9 10 11 12 13
NC−No internal connection
R
C1
S
1J
1K
2K
NC
2J
NC
2PRE
5
6
9
8
1Q
1Q
2Q
2Q
‡ This symbol is in accordance with ANSI/IEEE Std 911-1984 and
IEC Publication 617-12.
Pin numbers are for D, J, and N packages.
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
POST OFFICE BOX 655303
POST OFFICE BOX 1443
•
•
DALLAS, TEXAS 75265
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Copyright

1986, Texas Instruments Incorporated
5BASIC
1

SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986
Q
Q
PRE
K
CLR
J
CLK
To Other Flip-Flop
Supply voltage, V
CC
Input voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 V
7 V
Operating free-air temperature range: SN54ALS114A
Storage temperature range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 ° C to 125 ° C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0 ° C to 70 ° C
−65 ° C to 150 ° C
tsu th
TA
VCC
VIH
Supply voltage
High-level input voltage
VIL
IOH
IOL
Low-level input voltage
High-level output current
Low-level output current fclock Clock frequency tw Pulse duration
Setup time before CLK
↓
Hold time, data after CLK ↓
Operating free-air temperature
PRE or CLR low
CLK high
CLK low
Data
PRE or CLR inactive
20
25
25
0
− 55
SN54ALS114A
MIN NOM MAX
4.5
5 5.5
2
0.7
− 0.4
4
25 0
20
20
125
16.5
22
20
0
0
SN74ALS114A
MIN NOM MAX
4.5
5 5.5
2
UNIT
V
V
0.8
V
− 0.4
mA
8 mA
30 mHz 0
10
16.5
ns
70 ns ns
°
C
2
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•
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SDAS201 − D2661, DECEMBER 1982 − REVISED MAY 1986
VIK
VOH
VOL
PARAMETER TEST CONDITIONS
VCC = 4.5 V, II = − 18 mA
VCC = 4.5 V to 5.5 V, IOH = − 0.4 mA
VCC = 4.5 V, IOL = 4 mA
VCC = 4.5 V, IOL = 8 mA
SN54ALS114A
MIN TYP† MAX
− 1.5
VCC −2
0.25
0.4
SN74ALS114A
MIN TYP† MAX
VCC −2
0.35
− 1.5
UNIT
V
V
V
II
IIH
J, K, or CLK
PRE or CLR
J, K, or CLK
PRE or CLR
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
0.1
0.2
20
40
0.5
0.1
0.2
20
40 mA
µ
A
IIL
J, K, or CLK
PRE or CLR
VCC = 5.5 V, VI = 0.4 V
− 0.2
− 0.4
− 0.2
− 0.4
mA
IO‡ VCC = 5.5 V, VO = 2.25 V − 30 − 112 − 30 − 112 mA
ICC VCC = 5.5 V, See Note 1 2.5
4.5
2.5
4.5
mA
† All typical values are at VCC = 5 V, TA = 25 °
C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.
PARAMETER
FROM
(INPUT) fmax tPLH
PRE or CLR tPHL tPLH
CLK tPHL
NOTE 2: Load circuit and Voltage waveforms are shown in Section 1.
TO
(OUTPUT)
Q or Q
Q or Q
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω ,
TA = MIN to MAX
SN54ALS114A SN74ALS114A
MIN MAX MIN MAX
25
3
4
3
5
29
30
28
31
30
3
4
3
5
15
18
15
19
UNIT
MHz ns ns
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3

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