Wired: Wire
Wire--Aware Circuit Design
Intel custom project, funded by the Semiconductor Research Corporation
Corporation (SRC)
Emil Axelsson
Mary Sheeran and Koen Claessen
Chalmers University of Technology
For CHARME 2005
Background
There’s a whole world beneath the netlist
Physical design stage introduces wires
Only implicitly present in netlist
Real physical objects with associated side-effects
1
Down-scaling chip technologies
Active devices gain performance
Wires don’t (on average)
Non-ideal wire effects exposed
E.g. ratio of wire/gate delay increases
Wires already dominating
75% of path delays, and 50% of power consumption
Wire-aware design flow
Traditional models abstract away from wires
The designer looses important control over performance
Sub-optimal solutions
Higher time-to-market
Urgent need to take wires into account from start
2
Formal verification?
Broaden the view of formal verification to also include
nonnon-functional properties
“FV
“FV community
community …
… must
must realize
realize the
the functional
functional
design
enough
design concerns
concerns are
are not
not enough”
enough”
enough
(Wolfgang
(WolfgangRoesner
Roesner(IBM)
(IBM)at
atCHARME’03)
CHARME’03)
Non-functional property checking
Our approach
Explicit wires!
Requires detailed explicit layout
… low-level design?
–Yes, but in a high-level, language-based system
Embedding in functional programming language Haskell
raises abstraction level
3
Our approach
Connection patterns raise level further
bitMult = row bitMult1
Functional, non-functional and geometrical aspects all
modeled
Our system is called Wired
Related work
μFP/Ruby/CADIC
Behavior and layout
Lava
Adds meta-programming
Interconnect-aware synthesis of arithmetic modules
Physically knowledgeable synthesis (PKS)
Automatic integration of logical and physical design stages
Cadence, Synopsys, Magma
4
Wired in short I
A description is either
R
Primitive defined by a surface
and a surface relation
Compound defined by two subdescriptions and a combinator
R1
R2
A surface is a structure of contact segments
Relation propagates constraints across the surface
Both structural and behavioral constraints
Wired in short II
The surface structure may be
partially unspecified
Description surface and
context surface must be equal
Context surface
Instantiation engine “solves” the unknown surfaces using
this constraint and the surface relations
Example – stretchy wires:
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Wired in short III
Generic description
Awaits surface info from context, and then instantiates
?
Instantiation encoded as a Haskell function
Allows clever choices
Used to describe recursive connection patterns
Most common row:
row
row D
D
row D
Parallel prefix
Central component in CPUs
Carry computation in look-ahead adders
Priority encoders
sklansky
sklansky 00 == thinEmptyX1
thinEmptyX1
sklansky
sklansky dep
dep == join
join *=~
*=~ (subSklansky
(subSklansky ~||~
~||~ subSklansky)
subSklansky)
where
where
subSklansky
subSklansky == sklansky
sklansky (dep-1)
(dep-1)
join
join == (row
(row w1
w1 ~||*
~||* w3)
w3) -||-||- (row
(row d2
d2 ~||*
~||* d)
d)
params2
where
(d,d2,w1,_,w3,_)
=
params
where (d,d2,w1,_,w3,_) = params2
params
6
Paramterization
sklansky
sklansky 00 == thinEmptyX1
thinEmptyX1
sklansky
sklansky dep
dep == join
join *=~
*=~ (subSklansky
(subSklansky ~||~
~||~ subSklansky)
subSklansky)
where
where
subSklansky
subSklansky == sklansky
sklansky (dep-1)
(dep-1)
join
join == (row
(row w1
w1 ~||*
~||* w3)
w3) -||-||- (row
(row d2
d2 ~||*
~||* d)
d)
params2
where
(d,d2,w1,_,w3,_)
=
where (d,d2,w1,_,w3,_) = params2
New parallel prefix structure
New structure with low fanout (here 67 inputs)
Non-trivial structure; ≈50 lines of code
7
(Non-)functional analysis
The user makes statements about connections, e.g.:
Signals s1 and s2 are connected over distance d :
s1
s2
d
The actual relation depends on signal interpretation (NSI)
Logical value (standard interpretation)
Direction (in/out)
Unit delay
Drive resistance / load capacitance
RC-delay
…
RC-delay; bi-directional analysis
RC-delay
RR == rr •• ll
r, c
R
modeled as
l
C
CC == cc •• ll
delay
delay ≈≈ RC
RC // 22
Composition with fanout (Elmore approximation)
R1,C1
R0, C0
0
1
R3, C3
3
R4, C4
4
R2,C2
2
delay
delay ≈≈
RR00CC00 // 22 ++ RR33CC33 // 22
++ RR00•• ((CC11 ++ CC22 ++ CC33++ CC44))
delay
8
Bi-directional analysis
No magic
The primitives know how to propagate values locally
Instantiation engine propagates values globally
Functional setting and symbolic evaluation
Forwards analysis
Relational setting
Bi-direcional analysis
Why not external analysis?
Quick evaluation of different alternatives
Analysis can be used to guide instantiation
⇒ adaptive descriptions
s1
s2
s3
?
delay s1 < delay s3
otherwise
s1
s2
s3
s1
s2
s3
&
&
&
&
M. Sheeran. Generating fast multipliers using clever circuits.
FMCAD 2004.
9
What has been done?
Instantiation engine
Primitives, combinators, connection patterns
Analysis (all of the above)
Browser/debugger
Output: currently postscript layout
Who should use Wired?
Low-level designers
Hide boring details in patterns
Quick evaluation of different layout alternatives
Module designers
Wired descriptions can be made
Highly parameterized
Context-sensitive
10
Future work
Examples: Adaptive circuits (low-power), …
Output
Real layout (VLSI project)
Netlist (timed VHDL)
Analysis: Crosstalk, …
Semantics
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