Ground planes for low cost boards
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Ground planes for low cost boards
The ground plane approach is well established for high-value, high-speed digital
circuits for which multilayer PCBs are the norm. What is sometimes less appreciated is
that it is directly relevant to low-cost analogue circuits as well. Adding a ground plane
to a cheap single-sided analogue board is often the single most cost effective change for
improving EMC.
Despite the encroachment of digital technology, analogue circuits are still widely
used for simple, cost-sensitive applications, particularly in the consumer market.
Examples are security sensors, timers and residual current detectors. For these
products, cost is the driving factor and both component count and assembly time must
be kept to a minimum. Volumes may be high and assembly is often done in low labour
cost areas, so that through hole insertion is still economic by comparison with surface
mounting. PCB technology may be single sided on PRBF, if double-sided PTH on
fibreglass represents too high a cost. These products typically are unconcerned with RF
emissions, and historically EMC has never been considered in their design. Under the
EMC Directive though, RF and transient immunity is important, even as it is for
reliability of operation. This immunity can frequently best be achieved by
implementing a ground plane on the board.
1
Adding a grounded copper layer
A plane can be implemented retrospectively by simply adding a top copper layer to a
single-sided board design, without changing the original layout (Figure 1). The top
copper etch pattern is limited to clearance holes around each component lead – the
original pad pattern in reverse. The top layer is connected by a through wire or eyelet
to the 0V track on the underside. Note that it must be connected at least at one point –
a floating copper layer is worse than useless, since it merely increases capacitive
coupling between the enclosure or outside, and the circuit.
Common point
for 0V track and
copper plane
Copper plane
on component
side of board
Figure 1 Simple copper layer added to a single sided PCB
Tim Williams, Elmac Services, PO Box 111, Chichester, UK PO19 4ZS
http://www.elmac.co.uk
© 2000
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This construction does not make the plane behave in the optimum fashion, where
current flowing within it minimises magnetic coupling to the circuits – the plane
ensuring minimum possible loop area for each circuit path. It cannot do this as long as
the 0V returns for each and every circuit are not connected to it. It does, though, act as
a partial electric field screen, reducing the effect of capacitive coupling to the tracks.
This is most effective for higher-impedance circuits where capacitive coupling is the
prime threat. It will also reduce differential voltages across the length and width of the
PCB, induced either magnetically or electrically. You can think of it as creating a
“quasi-equipotential” area for RF interference over the region of the circuit.
Its effect is maximised if the 0V connection is made in the vicinity of the most
sensitive part of the circuit, and if this part of the circuit is located away from the edges
of the plane. The purpose of this is to ensure that the remaining interference-induced
voltage differences between the plane and the circuit tracks are lowest in the most
critical area.
2
Making the copper layer into a ground plane
If some cost increase is permissible and a double sided PTH board can be used, then it
is preferable to transfer all 0V current onto the plane layer, which then becomes a true
ground plane. All circuit 0V connections are returned to the ground plane via PTH pads
and the original 0V track is redundant. In a revised or new layout, the 0V track is
omitted entirely, possibly allowing a tighter component and tracking density. Figure 2
shows this transition.
0V points taken
direct to ground
plane, no track
needed
Ground plane
on component
side of board
Figure 2 Taking all 0V connections to the ground plane
This will have the effect not only of reducing capacitive coupling to the circuit, as
discussed above, but also magnetic coupling, since all circuit paths now inherently have
the least loop area. As long as sensitive circuits are located well inboard of the edges of
the plane they will enjoy the greatest protection. Fringing fields at the edge of a ground
plane increase its effective inductance, and magnetic coupling to the circuit tracks
worsens.
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It is not essential that the ground plane area covers the whole of the board, or even
all of the tracks, as long as it does cover the tracks and circuit areas which are critical
for immunity.
3
Breaks in the ground plane
What is essential is that the plane remains unbroken in the direction of current flow.
Any deviations from an unbroken plane effectively increase the loop area and hence the
inductance. If breaks are necessary it is preferable to include a small bridging track next
to a critical signal track to link two adjacent areas of plane (Figure 3). A slot in the
signal
current
return
current
This is not a ground plane!
If a break is unavoidable, it is best
linked with a short bridging track
Figure 3 A broken ground plane
ground plane will nullify the beneficial effect of the plane if it interrupts the current,
however narrow it is. This is why a multilayer construction with an unbroken internal
ground plane is the easiest to design, especially for fast logic which requires a closely
controlled track characteristic impedance. Where double-sided board with a partial
ground plane is used, bridging tracks as shown in Figure 3 should accompany all critical
tracks, especially those which carry sensitive signals a significant way across the board.
The most typical source of ground plane breaks is a slot due to a row of through hole
connections, such as required by a SIL or DIL IC package (Figure 4). The effect of such
a slot is worst for the tracks in its centre, since the return current is diverted all the way
to the edge of the slot. This translates to greater ground inductance and an unnecessary
increase in induced interference voltage in this area of the board’s ground network. If
the slot straddles a particularly sensitive circuit then worsened immunity will result,
even though you have gone to the trouble of putting a ground plane onto the board. It
is a simple matter to ensure that each pair of holes is bridged by a thin copper trace –
most etching technology is capable of this degree of resolution – it adds nothing to the
production cost and can give several dB improvement in immunity in the best case.
4
Crosstalk
A ground plane is a useful tool to combat crosstalk, which is strictly speaking an
internal EMC phenomenon. Crosstalk coupling between two tracks is mediated via
inductive, capacitive and common ground impedance routes, usually a combination of
all three (Figure 5). The effect of the ground plane is to significantly reduce the
common ground impedance ZG, by between 40−70dB, in the case of an infinite ground
plane compared to a narrow track.
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slots in ground plane around DIL pads
HF return current must negotiate slots –
greater loop area is equivalent
to excess ground inductance
tie traces between pads break up slots
HF return current can choose optimum
return path – minimum loop area means
lowest ground inductance
inductive effect of slot
Figure 4 Dealing with slots at DIL pinouts
The ground plane may also reduce mutual inductance coupling (M12) by ensuring
that the coupled current loops are not co-planar. Capacitive coupling between the tracks
will not be directly affected by the ground plane, but the lowered impedance of the line
(equivalent to saying that C1G and C2G have been increased) will reduce capacitive
crosstalk amplitude.
capacitance to ground
ZS1
VS1
mutual
VS2
inductance
ZS2
M 12
ZL1
C1G
C12
ZG
C2G
ground impedance
Figure 5 Crosstalk equivalent circuit
ZL2
coupling
capacitance
Crosstalk problems, or internal interference coupling, are by no means limited to
digital circuits, although these tend to make the problem most visible. A common threat
to the immunity of analogue circuits is crosstalk from other circuits carrying high
interference currents or voltages. Mains-borne interference is the most widespread, but
RF or transient interference induced onto signal cables can also be significant. You
should always be on the lookout to minimise crosstalk from these sources by ensuring
the maximum separation (hence minimum M12 and C12) between the circuits; or by
interposing electric field screening between them, if C12 is dominant; or by
implementing a ground plane, to minimise ZG and maximise C1G and C2G.