Freescale Semiconductor
Application Note
AN2759
Rev. 0.2, 9/2004
Implementing an Ethernet
Interface with the MC9S12NE64
By: Bill Lucas and Steven Torres
Systems Engineering
Austin, Texas
Introduction
This application note provides recommendations for implementing an Ethernet interface with the
MC9S12NE64 microcontroller unit (MCU). The discussion covers many topics including:
•
Overview of the MC9S12NE64 including available packages
•
Components required to add Ethernet functionality to the MC9S12NE64
•
MC9S12NE64 schematics showing the minimum system design
•
Circuit connections between the MC9S12NE64 and a high-speed LAN magnetics isolation module
and RJ45 connector
•
General printed circuit board (PCB) layout recommendations for 10 and 100 Mbps Ethernet design
•
High-speed LAN magnetics isolation module requirements
•
Crystal placement and circuitry recommendations
•
MC9S12NE64 Ethernet design examples in both 112-pin and 80-pin packages
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC9S12NE64 Single-Chip Ethernet Solution
Figure 1 shows a preview of the design examples:
Figure 1. Design Examples
MC9S12NE64 Single-Chip Ethernet Solution
This section introduces the MC9S12NE64 and provides an overview of the MC9S12NE64 integrated
Ethernet controller and MC9S12NE64 system design.
MC9S12NE64 Overview
The MC9S12NE64 is a 16-bit MCU based on Freescale Semiconductor’s HCS12 CPU platform. It
includes 8K bytes of RAM and 64K bytes of FLASH memory. In the 80-pin package, the MC9S12NE64
has other standard on-chip peripherals including two asynchronous serial communications interface
modules (SCIs), one synchronous serial peripheral interface (SPI), an inter-integrated circuit bus (IIC), a
4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ADC), and up to 18
pins available as keypad wake-up inputs (KWUs) or general-purpose I/O pins. In addition, an expanded
bus that can be operated at 16 MHz1 is available on the 112-pin package.
The MC9S12NE64 introduces a new peripheral for the HCS12 CPU platform, an integrated Ethernet
controller. The MC9S12NE64 integrates an Ethernet controller that includes a media access controller
(MAC) and a physical transceiver (PHY) in one die with the CPU, memory, and other HCS12 standard
on-chip peripherals. The MC9S12NE64 integrated Ethernet controller is compatible with IEEE 802.3 and
802.3u specifications for 10-Mbps or 100-Mbps operation, respectively.
1. At a 16-MHz internal bus speed, the MC9S12NE64 integrated Ethernet controller is limited to 10-Mbps operation. A 25-MHz
internal bus speed is required for 100-Mbps operation.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
2
Freescale Semiconductor
MC9S12NE64 Single-Chip Ethernet Solution
The MC9S12NE64 can be targeted at low-throughput connectivity applications that require operation
from a nominal 3.3-V power supply. With an on-chip bandgap-based voltage regulator (VREG), the
internal digital supply voltage of 2.5 V (VDD) will be generated internally. Figure 2 shows a block diagram
of the MC9S12NE64. More information on the MC9S12NE64 is available from the
Freescale Semiconductor website: http://freescale.com.
HCS12 CPU WITH DEBUG MODULE
2 X SCI
64K FLASH
IIC
V REG 3.3 V
TO 2.5 V CONVERTER
18 KEY WAKEUP
IRQ PORTS
INTERNAL BUS
SPI
8K RAM
ATD
10-BIT, 8 CH
EPHY
TIMER
16-BIT, 4 CH
EMAC
Figure 2. Block Diagram of the MC9S12NE64
MC9S12NE64 Packages
The MC9S12NE64 is available in two packages. Table 1 provides device numbers for each package
Figure 3 shows the 112-pin LQFP package pin-out. Figure 4 shows the 80-pin TQFP-EP package pin out.
Table 1. MC68HCS908NE64 Package Options
Device Number
Mask Set
Temp
Package
MC9S12NE64CFU
0L19S
–40° C, 85° C
80TQFP-EP
MC9S12NE64CPV
0L19S
–40° C, 85° C
112LQFP
•
112-pin LQFP package — 70 I/O port pins and 10 input-only pins
•
80-pin TQFP-EP package — 38 I/O port pins and 10 input-only pins
The 80-pin TQFP-EP package does not have access to the multiplex address and data bus. It is designed
for single-chip applications that use the internal FLASH and RAM memory. The 80-pin TQFP-EP package
has an exposed flag for heat dissipation and requires special PCB layout to accommodate the flag. See
the Exposed Flag section.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
3
MC9S12NE64-Family
112LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PL0/ACTLED
PL1/LNKLED
VDDR
PL2/SPDLED
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PHY_VSSRX
PHY_VDDRX
PHY_RXN
PHY_RXP
PHY_VSSTX
PHY_TXN
PHY_TXP
PHY_VDDTX
PHY_VDDA
PHY_VSSA
PHY_RBIAS
VDD2
VSS2
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PL3/DUPLED
PL4/COLLED
BKGD/MODC
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
KWG7/PG7
SCI0_RXD/PS0
SCI0_TXD/PS1
SCI1_RXD/PS2
SCI1_TXD/PS3
SPI_MISO/PS4
SPI_MOSI/PS5
SPI_SCK/PS6
SPI_SS/PS7
NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PL6
PL5
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
MII_TXER/KWH6/PH6
MII_TXEN/KWH5/PH5
MII_TXCLK/KWH4/PH4
MII_TXD3/KWH3/PH3
MII_TXD2/KWH2/PH2
MII_TXD1/KWH1/PH1
MII_TXD0/KWH0/PH0
MII_MDC/KWJ0/PJ0
MII_MDIO/KWJ1/PJ1
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
VDDX1
VSSX1
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
MII_CRS/KWJ2/PJ2
MII_COL/KWJ3/PJ3
MII_RXD0/KWG0/PG0
MII_RXD1/KWG1/PG1
MII_RXD2/KWG2/PG2
MII_RXD3/KWG3/PG3
MII_RXCLK/KWG4/PG4
MII_RXDV/KWG5/PG5
MII_RXER/KWG6/PG6
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PJ6/KWJ6/IIC_SDA
PJ7/KWJ7/IIC_SCL
PT4/TIM_IOC4
PT5/TIM_IOC5
PT6/TIM_IOC6
PT7/TIM_IOC7
PK7/ECS/ROMCTL
PK6/XCS
PK5/XADDR19
PK4/XADDR18
VDD1
VSS1
PK3/XADDR17
PK2/XADDR16
PK1/XADDR15
PK0/XADDR14
VSSA
VRL
VRH
VDDA
PAD7/AN7
PAD6/AN6
PAD5/AN5
PAD4/AN4
PAD3/AN3
PAD2/AN2
PAD1/AN1
PAD0/AN0
MC9S12NE64 Single-Chip Ethernet Solution
Signals shown in Bold are not available on the 80-pin package.
Figure 3. Pinout of MC9S12NE64 in 112-Pin LQFP Package
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
4
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MC9S12NE64-Family
80 TQFP-EP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PL0/ACTLED
PL1/LNKLED
VDDR
PL2/SPDLED
PHY_VSSRX
PHY_VDDRX
PHY_RXN
PHY_RXP
PHY_VSSTX
PHY_TXN
PHY_TXP
PHY_VDDTX
PHY_VDDA
PHY_VSSA
PHY_RBIAS
VDD2
VSS2
PL3/DUPLED
PL4/COLLED
BKGD/MODC
SCI0_RXD/PS0
SCI0_TXD/PS1
SCI1_RXD/PS2
SCI1_TXD/PS3
SPI_MISO/PS4
SPI_MOSI/PS5
SPI_SCK/PS6
SPI_SS/PS7
ECLK/PE4
VSSX2
VDDX2
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
IRQ/PE1
XIRQ/PE0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MII_TXER/KWH6/PH6
MII_TXEN/KWH5/PH5
MII_TXCLK/KWH4/PH4
MII_TXD3/KWH3/PH3
MII_TXD2/KWH2/PH2
MII_TXD1/KWH1/PH1
MII_TXD0/KWH0/PH0
MII_MDC/KWJ0/PJ0
MII_MDIO/KWJ1/PJ1
VDDX1
VSSX1
MII_CRS/KWJ2/PJ2
MII_COL/KWJ3/PJ3
MII_RXD0/KWG0/PG0
MII_RXD1/KWG1/PG1
MII_RXD2/KWG2/PG2
MII_RXD3/KWG3/PG3
MII_RXCLK/KWG4/PG4
MII_RXDV/KWG5/PG5
MII_RXER/KWG6/PG6
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PJ6/KWJ6/IIC_SDA
PJ7/KWJ7/IIC_SCL
PT4/TIM_IOC4/
PT5/TIM_IOC5
PT6/TIM_IOC6
PT7/TIM_IOC7
VDD1
VSS1
VSSA
VRL
VRH
VDDA
PAD7/AN7
PAD6/AN6
PAD5/AN5
PAD4/AN4
PAD3/AN3
PAD2/AN2
PAD1/AN1
PAD0/AN0
MC9S12NE64 Single-Chip Ethernet Solution
Figure 4. Pinout of MC9S12NE64 in 80-Pin TQFP-EP Package
Designing with the MC9S12NE64 and Adding an Ethernet Interface
The MC9S12NE64 is a single-chip Ethernet solution. Having built-in CPU, FLASH, RAM, MAC, and PHY
reduces the cost of implementing an embedded device with Ethernet connectivity, because no active
external components are required. The components required to enable the MC9S12NE64 Ethernet
interface include the following:
•
•
•
•
•
•
•
•
•
MC9S12NE64 MCU
25-MHz crystal
3.3-V power supply
External resistor for PHY_RBIAS pin (see data sheet for value of R Bias)
High-speed LAN magnetics isolation module
RJ45 connector
Miscellaneous capacitors and resistors
Optional: PHY status LEDs (available in some integrated RJ45 connectors)
Optional: Background debug (BDM) connector
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
5
MC9S12NE64 Single-Chip Ethernet Solution
Figure 5 is a schematic of a MC9S12NE64 minimum system circuit implementation using the
MC9S12NE64 in an 80-pin package and the components described in this section. This circuit
implementation shows an optional background debug connector (J1), and status LEDs (LED1 through
LED5). The circuit also shows the required bias resistor (R5), high-speed LAN magnetics isolation
module, and RJ45 Ethernet connector.
3.3V
C1
62
63
64
65
61
PAD0/ AN0
PAD1/ AN1
PAD2/ AN2
PAD3/ AN3
PAD4/ AN4
67
68
66
PAD5/ AN5
PAD6/ AN6
69
PAD7/ AN7
70
VRH
VDDA
72
71
VRL
73
VSS1
VSSA
75
76
77
74
VDD1
PT7/ TIM_ IOC7
PT6/ TIM_ IOC6
PT5/ TIM_ IOC5
79
78
PT4/ TIM_ IOC4
PJ6/ KWJ6/ IIC_SDA
PHY_VDDTX
MII_COL/KWJ3/PJ3
PHY_VDDA
MII_RXD0/KWG0/PG0
PHY_VSSA
MII_RXD1/KWG1/PG1
PHY_RBIAS
MII_RXD2/KWG2/PG2
VDD2
MII_RXD3/KWG3/PG3
VSS2
MII_RXCLK/KWG4/PG4
PL3/DUPLED
MII_RXDV/KWG5/PG5
PL4/COLLED
60
PL0/ACTLED
59
C2
PL1/LNKLED
58
0.01
3.3V
57
TRANSFORMER / RJ-45 CONNECTOR
PL2/SPDLED
56
C3
0.22
55
R1
R2
49.9
49.9
T1
6
54
5
53
4
MCU SIDE
J6
J7
J8
J3
75 OHMS
CT
6
7
8
3
R+
RJ-45
52
51
3
50
49
2
0.22
C4
1
C5
48
0.22
47
46
45
R3
R4
49.9
49.9
8
T-
J2
J4
J5
J1
75 OHMS
CT
T+
2
4
5
1
1000 pF
2kV
.
R5
12.4k 1%
EARTH/CHASSIS
0.22
C6
44
43
PL3/DUPLED
42
OPTIONAL STATUS LED's
PL4/COLLED
41
3.3V
LED1
J1
XIRQ/ PE0
CABLE SIDE
R-
1
3
5
1
3
5
2
4
6
2
4
6
BACKGROUND DEBUG
R6
PL1/LNKLED
*RESET
LNK_LED
220
3.3V
LED2
40
IRQ/ PE1
39
TEST
38
XTAL
EXTAL
36
37
VSSPLL
35
34
33
XFC
VDDPLL
RESET
32
VDDX2
BKGD/MODC
31
MII_RXER/KWG6/PG6
21
20
PHY_TXP
MII_CRS/KWJ2/PJ2
R7
PL2/SPDLED
3.3V
*RESET
19
PHY_TXN
MC9S12NE64
VSSX1
VSSX2
18
VDDX1
30
17
PHY_VSSTX
ECLK/PE4
16
PHY_RXP
MII_MDIO/KWJ1/PJ1
SPI_SS/ PS7
15
MII_MDC/KWJ0/PJ0
28
14
PHY_RXN
29
13
MII_TXD0/KWH0/PH0
SPI_ SCK/ PS6
12
PHY_VDDRX
27
11
MII_TXD1/KWH1/PH1
SPI_ MOSI/ PS5
10
PHY_VSSRX
26
3.3V
MII_TXD2/KWH2/PH2
SPI_ MISO/ PS4
9
PL2/SPDLED
SCI1_ TXD/ PS3
8
VDDR
MII_TXD3/KWH3/PH3
25
7
PL1/LNKLED
24
6
3.3V
PL0/ACTLED
MII_TXCLK/KWH4/PH4
SCI1_ RXD/ PS2
5
MII_TXEN/KWH5/PH5
23
4
SCI0_ TXD/ PS1
3
MII_TXER/KWH6/PH6
SCI0_ RXD/ PS0
2
22
1
PJ7/ KWJ7/ IIC_ SCL
U1
80
0.22
SPD_LED
220
LED3
R8
DUP_LED
220
PL3/DUPLED
C7
25 MHz
Y1
0.22
LED4
R9
PL0/ACTLED
R10
R11
C10
470Pf
C8
10M
ACT_LED
C9
LED5
2.2k
15pF
C11
15pF
220
R12
PL4/COLLED
COL_LED
220
4700Pf
Figure 5. MC9S12NE64 Minimum System Circuit Implementation in the 80-Pin Package
In Figure 5, the MC9S12NE64 in the 80-pin package will operate in normal single-chip mode. Figure 5
shows that the design operates with the internal voltage regulator enabled. Using the internal voltage
regulator is the recommended configuration for the MC9S12NE64. Figure 5 also illustrates the basic
MC9S12NE64 power and clock input requirements, which are described in following sections.
To configure the MC9S12NE64 (in a 112-pin package) in normal single-chip mode, the MODC, MODB,
and MODA pins may need to be pulled up or down. The operating mode of the MC9S12NE64, as well as
other HCS12 MCUs, out of reset is determined by the states of MODC, MODB, and MODA during reset.
MODC, MODB, and MODA can alternatively be configured by software. Table 2 describes the available
modes on the 112-pin package.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
6
Freescale Semiconductor
MC9S12NE64 Single-Chip Ethernet Solution
Table 2. Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PP6 =
ROMCTL
ROMON
Bit
0
0
0
X
1
0
0
1
0
1
1
0
0
1
0
X
0
0
1
1
0
1
1
0
1
0
0
X
1
1
0
1
0
0
1
1
1
1
0
X
1
1
1
1
0
0
1
1
Mode Description
Special single chip, BDM allowed and active. BDM
is allowed in all other modes, but a serial
command is required to make BDM active.
Emulation expanded narrow, BDM allowed
Special test (expanded wide), BDM allowed
Emulation expanded wide, BDM allowed
Normal single chip, BDM allowed
Normal expanded narrow, BDM allowed
Peripheral; BDM allowed but bus operations would
cause bus conflicts (must not be used)
Normal expanded wide, BDM allowed
For details about modes, refer to the MC9S12NE64 device user guide.
Connecting a Power Supply to the MC9S12NE64
Using the internal voltage regulator can simplify power supply requirements for the design because (with
the internal voltage regulator enabled) only a 3.3-V power supply that can handle the current load of the
MC9S12NE64 is required. The power supply must be connected to VDDX1, VDDX2, and VDDR.
The internal voltage regulator is a five-stage regulator that provides 2.5 V to the MC9S12NE64, including:
•
CPU
•
PLL
•
PHY analog
•
PHY transmitter
•
PHY receiver
Alternatively, depending on the embedded design requirements, the MC9S12NE64 can be set up with the
internal voltage regulator disabled, which would require a 2.5-V external power supply for the logic plus
a 3.3-V supply for the PHY I/O. This application note describes MC9S12NE64 configuration with the
internal 2.5-V voltage regulator enabled. For configurations with the internal voltage regulator is disabled,
see the MC9S12NE64 data sheet for special circuitry requirements. Disabling the voltage regulator is not
recommended.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
7
MC9S12NE64 Single-Chip Ethernet Solution
Connecting a Crystal to the MC9S12NE64
For basic operation of the MC9S12NE64 Ethernet controller, a 25-MHz crystal input with a tolerance of
25 ppm is required per IEEE 802.3 specification. The 25-MHz crystal input is required to provide the clock
input to the integrated PHY for basic operation at 10 Mbps and/or 100 Mbps. The crystal must connect to
the MC9S12NE64 in a Pierce configuration by the XTAL and EXTAL pins as shown on Table 5 with
related cap and resistors.
In addition to providing a 25-MHz crystal input, to operate at 100 Mbps, the internal bus clock must be
configured to 25 MHz. With the 25-MHz crystal, the CRG must be configured so the PLL is enabled and
multiplies the crystal oscillator clock to achieve the internal bus clock 25 MHz operational setting.
For 10 Mbps, an internal bus clock setting of 2.5 MHz minimum is acceptable, but a 25-MHz crystal input
is still required.
For details about the CRG and configuring the PLL, see Freescale Semiconductor document AN2692/D:
MC9S12NE64 Integrated Ethernet Controller.
MC9S12NE64 PHY External Pins
Table 3 describes the pins related to the MC9S12NE64 PHY, their operation, and their circuitry design.
The PHY pins in Table 3 serve several possible functions including power, signaling, component, and
indicators for the EPHY.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
8
Freescale Semiconductor
MC9S12NE64 Single-Chip Ethernet Solution
Table 3. MC9S12NE64 PHY External Pins
Pin Function
Power
Pin Label(s)
PHY_VDDA,
PHY_VSSA
Power supply
pins for EPHY
analog power
PHY_VDDRX,
PHY_VSSRX
Power supply
pins for EPHY
receiver power
PHY_VDDTX,
PHY_VSSTX
Power supply
pins for EPHY
transmitter
PHY_TXP
EPHY twisted
pair output +
PHY_TXN
EPHY twisted
pair output –
PHY_RXP
EPHY twisted
pair input +
PHY_RXN
EPHY twisted
pair input –
Signaling
Circuit
(EPHY bias
pin)
Pin Overview
Description
This 2.5-V supply is derived from the internal voltage regulator. No
static load is allowed on these pins. The internal voltage regulator
is turned off if VDDR is tied to ground.
Ethernet twisted pair output pin. These pins are Hi-Z out of reset.
PHY_RBIAS
EPHY bias
control resistor
Connect an external bias resistor(1), (R5), between the PHY_RBIAS
pin and analog ground. This resistor should be placed as near a
possible to the MCU pin. Stray capacitance must be less than 10
pF (greater than 50 pF may cause instability). No high-speed
signals should go in the region of the bias resistor.
COLLED
Collision LED
Flashes in half-duplex mode when a collision occurs on the
network.
DUPLED
Duplex LED
Indicates the duplex of the link, which can be full-duplex or halfduplex.
SPDLED
Speed LED
Indicates the speed of a link, which can be 10 Mbps or 100 Mbps.
LNKLED
Link LED
Indicates whether a link is established with another network device.
ACTLED
Activity LED
Flashes when data is received by the device.
Indicator
NOTES:
1. See the MC9S12NE64 data sheet for the value of the bias resistor
LED Indicator Pins
The power, signaling, and EPHY bias pins are required for basic operation of the EPHY; indicator pins
(PL0:5) are optional. The EPHY can be configuring by software to drive indicator pins (PL0:5)
automatically by setting the LEDEN bit of the EPHY EPHYCTL0 register. When LEDEN = 1, PL0:5 pins
are dedicated to the EPHY. Alternatively, the system can be designed such that user software drives
LEDs on any port pin to show EPHY status. For instance, the user may desire to show only link status. In
this case, the user can manually drive an LED with software to show link status (with LEDEN bit = 0),
which would allow the other four pins to be used for other purposes.
MC9S12NE64 low-level Ethernet drivers are available to handle software-driven LEDs.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
9
MC9S12NE64 Single-Chip Ethernet Solution
Adding an RJ45 Connector to the MC9S12NE64
Because the MC9S12NE64 has an integrated MAC and PHY, connecting an RJ45 Ethernet connector
and transformer is easy. A high-speed LAN magnetics isolation module must be used between the
MC9S12NE64 and the RJ45 Ethernet connector. This high-speed LAN magnetics isolation module can
be discrete or integrated within a RJ45 Ethernet connector. Figure 6 shows the required circuitry
configuration.
Figure 6. Ethernet Interface Circuitry
Table 4 describes the signal wiring for the MCU side.
Table 4. High-Speed LAN Magnetics Isolation Module Circuit Connections
High-Speed LAN Magnetics
Isolation Module
TX CT
MC9S12NE64 pins
3.3 V
T+
PHY_TXP
T-
PHY_TXN
RX CT
3.3 V
R+
PHY_RXP
R-
PHY_RXN
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
10
Freescale Semiconductor
PCB Design Recommendation
PCB Design Recommendation
The section provides recommendations for PCB design and high-speed LAN magnetics isolation module
selection.
General PCB Design Recommendations
The PCB layout must be designed to ensure proper operation of the voltage regulator and the MCU. The
following recommendations are provided to ensure a robust PCB design:
•
Every supply pair must be decoupled by a low-ESR (equivalent series resistance) ceramic
capacitor connected as near as possible to the corresponding pins.
•
Central point of the ground star should be the VSSX1 and VSSX2 pins.
•
Use low-ohmic, low-inductance connections with VSS1, VSS2, VSSX1, and VSSX2 pins.
•
VSSPLL must be directly connected to VSSX.
•
Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and their occupied board area as
small as possible.
Ethernet PCB Design Recommendations
When designing a PCB that uses the MC9S12NE64 Ethernet module, several design considerations
must be made to ensure that Ethernet operation conforms to the IEEE 802.3 physical interface
specification. Use the following recommendations for PCB design between the high-speed LAN
magnetics isolation module and:
•
•
MC9S12NE64 EPHY external pins (most critical)
RJ45 connector
Ethernet PCB design recommendations:
•
•
•
•
•
•
•
•
•
•
•
The distance between the magnetic module and the RJ-45 jack is the most critical and must always
be as short as possible (must be less than one inch).
Never use 90° traces. Use 45° angles or radius curves in traces.
Trace widths of 0.010” are recommended. Wider is better. Trace widths should not vary.
Route differential Tx and Rx pairs near together (max 0.010” separation with 0.010” traces).
Trace lengths must always be as short as possible (must be less than one inch).
Make trace lengths as equal as possible.
Keep TX and RX differential pairs routes separated (at least 0.020” separation). Better to separate
with a ground plane.
Avoid routing Tx and Rx traces over or under a plane. Areas under the Tx and Rx traces should be
open, See Figures 9, 10, 11, 17 and 18.
Use precision components in the line termination circuitry with 1% tolerance.
Ensure that the power supply is rated for a load of 300 mA minimum.
Avoid vias and layer changes.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
11
PCB Design Recommendation
In addition, all termination resistors should be near to the driving source. The MCU is the driving source
for PHY_TXP and PHY_TXN pins. The high-speed LAN magnetics isolation module is the driving source
for PHY_RXP and PHY_RXN pins.
High-Speed LAN Magnetics Isolation Module Requirements
The MC9S12NE64 requires a 1:1 ratio transformer for the high-speed LAN magnetics isolation module
for both the receive and the transmit signals. The basic high-speed LAN magnetics isolation module
specification requirements are provided in Table 5. High-speed LAN magnetics isolation modules that
meet these requirements are available from a variety of manufacturers.
Table 5. High-Speed LAN Magnetics Isolation Module
Specification Requirements
Parameter
Value
Units
Test Condition
Tx/Rx turns ratio
1:1 CT / 1:1
—
—
Inductance
350
mH (min)
—
Insertion loss
1.1
dB (max)
1 to 100 MHz
–18
dB (min)
1 to 30 MHz
–14
dB (min)
30 to 60 MHz
–12
dB (min)
60 to 80 MHz
Differential to common
mode rejection
–40
dB (min)
1 to 60 MHz
–30
dB (min)
60 to 100 MHz
Transformer
1500
V
—
Return loss
The MC9S12NE64 can be used with high-speed LAN magnetics isolation modules that are either discrete
or integrated into a RJ45 connector. Some of these integrated connectors have built-in LEDs as well. For
the MC9S12NE64, an RJ45 connector with an integrated high-speed LAN magnetics isolation module is
recommended because it reduces component count and simplifies PCB layout.
Because the MC9S12NE64 does not implement Auto-MDIX, an Auto-MDIX capable high-speed LAN
magnetics isolation module is not required. A high-speed LAN magnetics isolation module with improved
return loss characteristics is recommended to avoid Ethernet return loss issues.
Table 6 provides discrete and integrated high-speed LAN magnetics isolation modules that have been
found in testing to satisfy the requirements necessary to establish an IEEE-compliant Ethernet interface
with the MC9S12NE64. Other models can be used as long as the high-speed LAN magnetics isolation
module specifications satisfy the requirements.
Although specific hardware is discussed in this section, Freescale Semiconductor does not recommend
or endorse any particular product or vendor. This data is provided only to describe the specification
requirements.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
12
Freescale Semiconductor
Design Examples
Table 6. Discrete High-Speed LAN Magnetics Isolation Module
Type
Discrete
Manufacturer
Pulse
Midcom
Pulse
Integrated
Model
H1102
000-6241-37R
J10-0026
Midcom
JFM25xxx-0510, JFM24xxx-1010
Bel Fuse
0810-1X1T-06
Halo
HFJ11-2450E
Design Examples
This section shows two MC9S12NE64 design examples of Ethernet interface implementations with the
MC9S12NE64 in a minimum system. These minimum system examples are provided only to demonstrate
recommended MC9S12NE64 PCB design. These MC9S12NE64 design examples are test boards, and
they are not available for purchase.
The first design shows a minimum system using the MC9S12NE64 in a 112-pin package. The second
design is an example of a system using the 80-pin MC9S12NE64 with a very compact PCB footprint.
Schematics and all artwork layer views for both designs will be shown in this section. Both designs are
implemented on 4-layer PCBs to provide better heat dissipation. Both boards are minimum system
designs that use the internal voltage regulator.
MC9S12NE64 112-Pin Package Design Example
A photo of the MC9S12NE64 112-pin package design example is provided in Figure 7. The PCB, which
is approximately 6.3 cm x 6.3 cm, was designed using the recommendations discussed in the PCB Design
Recommendation section. This design and PCB layout are discussed in detail in following sections.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
13
Design Examples
Figure 7. 112-Pin Package Design Example
A schematic of this design example is provided in Figure 8.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
14
Freescale Semiconductor
85
ADDR7/DATA7/PB7
PHY_RBIAS
MII_CRS/KWJ6/PJ2
VDD2
MII_COL/KWJ7/PJ3
VSS2
MII_RXD0/KWG0/PG0
PA3/ADDR11/DATA11
MII_RXD1/KWG1/PG1
PA2/ADDR10/DATA10
MII_RXD2/KWG2/PG2
PA1/ADDR9/DATA9
SCAN_ MODE/ XIRQ/ PE0
PL3/DUPLED/LEDD
PL4/COLLED/LEDC
BKGD/MODC/SCANCLK2
R11
50
3.3V
81
PL2/SPDLED/LEDS
J2
6
77
76
1
.22
C11
R8
50
75
3
73
R12
50
72
71
.22
*RESET
66
.22
330
C6
EARTH/CHASSIS
65
64
63
OPTIONAL STATUS LED's
62
3.3V
61
60
47
PL3/DUPLED
58
PL4/COLLED
3.3V
C8
0.1
15 pF
15 pF
57
220
ACT_LED
LED1
BACKGROUND DEBUG
1
3
5
1
3
5
2
4
6
R5
COL_LED
*RESET
3.3V
R6
1
1 2
2 3
3
J3
+
C14
C15
C16 100 uF
0.22
0.01
JP1
2-PIN JUMPER
Figure 8. Minimum 112-Pin Package System Schematic
220
R7
PL4/COLLED
2
4
6
C3
0.22
DUP_LED
PL0/ACTLED
330
LED4
POWER
TP1
1
4700 pF
R3
LED3
R16
2
C1
470 pF
LED2
PL3/DUPLED
59
1
RESET
C2 10M
12 LED2AGREEN
11 LED2C
330
2
R2
C5
14 LED1AYELLOW
13 LED1C
12
11
PL2/SPDLED/LEDS
1
SW1
R1
R9
2.2k
3 TX-
R15
R10
3.3V
C7
2 TX_CT
PL1/LNKLED/LEDL
67
1
R4
27k
6 RX1 TX+
R13
C9
68
10k
3.3V
GND
EARTH
5 RX_CT
C10
69
.22
4 RX+
14
13
70
POWER_IN
25 MHz
2
74
J1
Y1
5
78
3.3V
3.3V
4
R14
50
79
MIDCOM JFM2411-0101W
80
56
SIDDQ/ IRQ/ PE1
55
LSTRB/TAGLO/PE3
ANLG_TST/R/W/PE2
54
53
PL5
52
PL6
51
TEST/ VPP
50
XTAL
49
VSSPLL
EXTAL
48
47
46
XFC
VDDPLL
45
RESET
44
MII_RXER/KWG6/PG6
VDDX2
MII_RXDV/KWG5/PG5
PA0/ADDR8/DATA8
43
MII_RXCLK/KWG4/PG4
VSSX2
MII_RXD3/KWG3/PG3
PL1/LNKLED/LEDL
82
9 CASE
10
PHY_VSSA
83
8ERTH
ADDR6/DATA6/PB6
PL0/ACTLED
9
10
PHY_VDDA
84
8
PAD0/ AN0/ BGTRIM0
87
86
PAD1/ AN1/ BGTRIM1
88
PAD3/ AN3/ BGTRIM3
PAD2/ AN2/ BGTRIM2
90
91
92
93
89
PAD4/ AN4/ TMOD0
PAD5/ AN5/ TMOD1
PAD6/ AN6/ TMOD2
PAD7/ AN7/ SCANCLK3
94
VRH
VDDA
96
97
98
95
VRL
VSSA
PK0/ XADDR14/ TX_ AMP_ TRIM0
100
101
102
103
99
PK1/ XADDR15/ TX_ AMP_ TRIM1
PK2/ XADDR16/ TX_ SLP_ TRIM0
PK3/ XADDR17/ TX_ SLP_ TRIM1
VSS1
VDD1
PK4/ XADDR18/ B10_ DIS
105
104
PK5/ XADDR19/ B100_ DIS
PK6/ XCS/ SYMBOL_ MODE
107
108
106
PK7/ ECS/ TRISTATE
PT7/ TIM_ IOC7/ PHY3
PT6/ TIM_ IOC6/ PHY2
109
110
PT4/ TIM_ IOC4/ PHY0
PJ6/ KWJ6/ IIC_ SDA/ ANDIS
PHY_VDDTX
ADDR5/DATA5/PB5
42
28
ADDR4/DATA4/PB4
SCANCLK1/ ECLK/ PE4
27
PHY_TXP
41
26
PHY_TXN
VSSX1
MODA/ IPIPE0/ PE5
25
VDDX1
40
24
PHY_VSSTX
MODB/ IPIPE1/ PE6
23
ADDR3/DATA3/PB3
NOACC/ PE7
22
PHY_RXP
39
21
ADDR2/DATA2/PB2
38
20
PHY_RXN
MDINT/ SPI_ SS/ PS7
19
ADDR1/DATA1/PB1
SCAN_ RESET/ SPI_ SCK/ PS6
18
PHY_VDDRX
37
17
ADDR0/DATA0/PB0
36
16
PHY_VSSRX
SCAN_ SET/ SPI_ MOSI/ PS5
15
PA4/ADDR12/DATA12
35
3.3V
14
PL2/SPDLED/LEDS
MII_MDIO/KWJ1/PJ1
TXD4/ SPI_ MISO/ PS4
13
VDDR
MII_MDC/KWJ0/PJ0
RXD4/ SCI1_ TXD/ PS3
12
PL1/LNKLED/LEDL
PA5/ADDR13/DATA13
34
11
0.01
PL0/ACTLED/LEDT
MII_TXD0/KWH0/PH0
33
10
C4
PA6/ADDR14/DATA14
SCAN_ ENABLE/ SCI1_ RXD/ PS2
9
3.3V
PA7/ADDR15/DATA15
32
8
3.3V
MII_TXD1/KWH1/PH1
DISABLE100/ SCI0_ TXD/ PS1
7
C13
.1
MII_TXD2/KWH2/PH2
31
6
MII_TXD3/KWH3/PH3
PT5/ TIM_ IOC5/ PHY1
111
112
5
MII_TXCLK/KWH4/PH4
PHY4/ SCI0_ RXD/ PS0
4
MII_TXEN/KWH5/PH5
KWG7/ PG7
3
30
2
MII_TXER/KWH6/PH6
29
1
PJ7/ KWJ7/ IIC_ SCL/ DISABLE10
U1
C12
.22
GND TESTPOINT
220
Design Examples
SPLIT
Figure 9. Minimum 112-pin Package Artwork All Layers
Ground planes and how grounds are tied together affect noise immunity. To maximize noise immunity, it
is important to get a good ground plane under the MCU. It is also a good practice to have the ground plane
under the crystal components. Note, on the layout, Figure 10, there is a white area to the left of the MCU.
That area is directly under the Ethernet transmit and receive traces from the MCU to the high-speed LAN
magnetics isolation module. That area under those traces must be devoid of any ground plane to reduce
capacitance.
As shown in Figure 9 and Figure 10, there is a split in the ground plane. It starts just to the right of the top
center of the PC board and continues down to just above the center of connector J3. The center pin of J3
is the system ground connection. This split in the ground plane forces the system’s ground currents to
flow to a common point, the ground connection for the PC board. This technique helps increase noise
immunity in the system.
As shown in Figure 11, attention was given to the length of the Ethernet transmit and receive pairs that
go between the MCU and the Ethernet integrated magnetics/RJ45 connector. They were made as short
as possible for this mechanical layout. The PC board tracks in the Ethernet portion of this design are
0.010” and the maximum conductor length is just under 0.5”. The PC board traces bend on 45° angles,
with no 90° angles. Figure 11 demonstrates these design practices.
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
16
Freescale Semiconductor
Design Examples
SPLIT
Ground Layer
WHITE
AREA
Power Layer
WHITE
AREA
Figure 10. Minimum 112-Pin Package Artwork
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
17
Design Examples
Top Layer
Bottom Layer
Figure 11. Minimum 112-pin Package Artwork
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
18
Freescale Semiconductor
Design Examples
As with all designs, place the crystal and its associated components as near to their MCU pins as possible
and use minimum trace lengths. This is also true with the XFC connections (PLL components).
There are a number of power supply decoupling capacitors necessary to decouple the MCU and its
various internal power supplies. These pins are VDD1, VDD2, VDDA, VDDPLL, PHY_VDDRX, and
PHY_VDDTX. These capacitors should be good quality, low ESR type ceramic components.
MC9S12NE64 80-Pin Package Design Example
The second design example uses the 80-pin MC9S12NE64 and uses the PCB design recommendations
discussed for the 112-pin design example. A photo is provided in Figure 12.
This example demonstrates that the MC9S12NE64 can implement Ethernet capability in a very small
package footprint. This 80-pin design example resides on a very small 1” x 1.5” PCB and shows a
complete Ethernet PCB system implementation. The design example uses the PCB recommendations
described in this application note. A schematic of this design example is provided in Figure 13.
Figure 12. 80-Pin Package Design Example
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
19
P2
3.3V
61
PAD0/ AN0
VDD2
MII_RXD3/KWG3/PG3
VSS2
MII_RXCLK/KWG4/PG4
PL3/DUPLED
MII_RXDV/KWG5/PG5
PL4/COLLED
MII_RXER/KWG6/PG6
BKGD/MODC
58
3.3V
57
R7
49.9
PL2/SPDLED
56
J1
R5
6
49.9
54
5
53
4
6 RX5 RX_CT
MIDCOM JFM2411-0101W
0.22
C12
55
4 RX+
52
3
51
R6
50
2
49.9
1
0.22
C9
49
3 TX2 TX_CT
1 TX+
3.3V
R8
48
14
13
49.9
0.22
C11
47
12
11
R9
46
12.4k 1%
45
R2
0.22
C8
44
14 LED1A YELLOW
13 LED1C
12 LED2A GREEN
11 LED2C
PL1/LNKLED
9
CASE
10
MII_RXD2/KWG2/PG2
PL1/LNKLED
8ERTH
PHY_RBIAS
59
330
43
3.3V
R12
9
10
MII_RXD1/KWG1/PG1
0.01
60
8
PAD1/ AN1
63
62
PAD2/ AN2
65
64
PAD3/ AN3
PAD4/ AN4
PAD5/ AN5
66
67
PAD7/ AN7
PAD6/ AN6
68
69
VDDA
70
VRH
72
71
VRL
VSS1
VSSA
74
73
VDD1
R3
PL2/SPDLED
42
10k
330
R13
10k
41
XIRQ/ PE0
IRQ/ PE1
1
3
5
2
4
6
2
4
6
SCI_Rx
*RESET
3.3V
BACKGROUND DEBUG
40
TEST
38
39
XTAL
37
VSSPLL
XFC
EXTAL
36
35
VDDPLL
34
RESET
33
SCI_Tx
*RESET
VSSX2
3.3V
32
31
VDDX2
J2
1
3
5
LED1
R4
USER_LED
330
3.3V
3.3V
25 MHz
C1
4700pF
R10
R1
C13
2.2k
15pF
10M
1
Citizen page 627,top left
300-8105-1-ND
C3
470Pf
+3.3V
GND
C10
15pF
2-PAD JUMPER
1
0.22
C2
2
Y1
P1
C6
0.1
C5
0.01
+ C4
R11
330
10 uF
2
76
75
PT7/ TIM_ IOC7
PT6/ TIM_ IOC6
77
PT5/ TIM_ IOC5
78
PT4/ TIM_ IOC4
80
79
PHY_VSSA
30
20
PHY_VDDA
MII_RXD0/KWG0/PG0
SPI_SS/ PS7
19
MII_COL/KWJ7/PJ3
ECLK/PE4
18
PHY_VDDTX
MII_CRS/KWJ6/PJ2
29
17
PHY_TXP
VSSX1
SPI_ SCK/ PS6
16
PHY_TXN
VDDX1
27
15
PHY_VSSTX
MII_MDIO/KWJ1/PJ1
28
14
PHY_RXP
MII_MDC/KWJ0/PJ0
SPI_ MOSI/ PS5
13
PHY_RXN
SPI_ MISO/ PS4
12
MII_TXD0/KWH0/PH0
26
11
PHY_VDDRX
SCI1_ TXD/ PS3
10
PHY_VSSRX
MII_TXD1/KWH1/PH1
25
3.3V
C7
MII_TXD2/KWH2/PH2
24
9
3.3V
VDDR
SCI1_ RXD/ PS2
8
2
4
PL2/SPDLED
MII_TXD3/KWH3/PH3
SCI0_ TXD/ PS1
7
2
4
PL1/LNKLED
23
6
1
3
2-PAD JUMPER
PL0/ACTLED
SCI_Tx
5
C14
MII_TXCLK/KWH4/PH4
SCI0_ RXD/ PS0
4
MII_TXEN/KWH5/PH5
22
3
MII_TXER/KWH6/PH6
SCI_Rx
2
21
1
PJ7/ KWJ7/ IIC_ SCL
FLAG
U1
PJ6/ KWJ6/ IIC_SDA
81
0.22
1
3
LED2
POWER
Figure 13. 80-Pin Package System Schematic
lnk green
spd green
duplex = third LED green
Design Examples
Figure 14 provides all artwork for the MC9S12NE64 80-pin package design example.
Power Layer
Top Layer
All Layers
Ground Layer
Bottom Layer
Figure 14. 80-Pin Package Artwork
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
21
Conclusion
Exposed Flag
Because the 80-pin TQFP-EP package has an exposed flag, which provides additional heat dissipation
for the MC9S12NE64, the artwork shows special PCB design to accommodate the exposed flag. There
are two ways to accommodate the flag:
•
Have a hatched pattern in the solder mask
•
Use small copper areas under the flag
The concept is to have about 50% of the flag soldered to the PC board.
Conclusion
The MC9S12NE64 is a highly integrated, flexible and easy-to-use Ethernet-capable microcontroller with
an integrated MAC and PHY. No external active components are needed to implement an Ethernet
interface. The schematics in this document illustrate the simplicity of implementing such a system.
Interfacing the device to an Ethernet trunk is accomplished with the addition of only four resistors, a
decoupling capacitor and an integrated transformer/RJ45 connector. PCB layout around the high-speed
LAN magnetics isolation module is critical, as with any high frequency design. Using techniques
discussed in this document makes that task easier.
NOTE
With the exception of mask set errata documents, if any other Freescale Semiconductor document
contains information that conflicts with the information in the device user guide, the user guide should be
considered to have the most current and correct data.
Notes
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
22
Freescale Semiconductor
Notes
This page is intentionally blank
Implementing an Ethernet Interface with the MC9S12NE64, Rev. 0.2
Freescale Semiconductor
23
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AN2759
Rev. 0.2, 9/2004