TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
D PACKAGE
(TOP VIEW)
D
Dual 8-Bit Voltage Output DAC
D
Programmable Internal Reference
D
Programmable Settling Time:
0.8
µ s in Fast Mode ,
2.8
µ s in Slow Mode
D
Compatible With TMS320 and SPI

Serial
Ports
D
Differential Nonlinearity <0.1 LSB Typ
D
Monotonic Over Temperature
DIN
SCLK
CS
OUTA
3
4
1
2
6
5
8
7
V
DD
OUTB
REF
AGND
D
Digital Servo Control Loops
D
Digital Offset and Gain Adjustment
D
Industrial Process Control
D
Machine and Motion Control Devices
D
Mass Storage Devices
The TLV5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows glueless interface to TMS320 and SPI

, QSPI

, and Microwire

serial ports. It is programmed with a 16-bit serial string containing 2 control and 8 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5626 simplifies overall system design.
Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges.
TA
AVAILABLE OPTIONS
PACKAGE
SOIC
(D)
0
°
C to 70
°
C
– 40
°
C to 85
°
C
TLV5626CD
TLV5626ID
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Copyright

1999, Texas Instruments Incorporated
1

TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
REF AGND VDD
PGA With
Output Enable
Voltage
Bandgap
Power-On
Reset
2
Power and Speed
Control
2
2-Bit
Control
Latch
DIN
8-Bit
DAC A
Latch
SCLK
8 8
CS
Serial
Interface and
Control
8
Buffer
8 8
8-Bit
DAC B
Latch x2 x2
OUTA
OUTB
TERMINAL
NAME
AGND
CS
NO.
5
3
DIN
OUTA
OUTB
REF
SCLK
VDD
6
2
8
1
4
7
I
I
O
P
I
Ground
Chip select. Digital input active low, used to enable/disable inputs
Digital serial data input
DAC A analog voltage output
DAC B analog voltage output
I/O Analog reference voltage input/output
I Digital serial clock input
P Positive power supply
2
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
†
Supply voltage (V
DD
to AGND)
Reference input voltage range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 V
– 0.3 V to V
DD
+ 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
– 0.3 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
°
+ 0.3 V
C to 70
°
C
TLV5626I – 40
°
C to 85
°
C
Storage temperature range, T stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
°
C to 150
°
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VDD = 5 V
VDD = 3 V
MIN
4.5
2.7
0.55
NOM
5
3
MAX UNIT
5.5
V
3.3
2
V
V Power on threshold voltage, POR
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REF terminal
Reference voltage, Vref to REF terminal
Load resistance, RL
Load capacitance, CL
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 5 V (see Note 1)
VDD = 3 V (see Note 1)
2
AGND
AGND
2
2.048
1.024
0.8
VDD –1.5
VDD – 1.5
100 k
V
V
V
V
Ω pF
Clock frequency, fCLK 20 MHz
TLV5626C 0 70
°
C
TLV5626I –40 85
NOTE 1: Due to the x2 output buffer, a reference input voltage
≥
(VDD – 0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
power supply
PARAMETER TEST CONDITIONS
Fast
Int. ref.
Slow
Fast
No load,
Int. ref.
Slow
Fast
DAC latch = 0x800
Ext. ref.
Slow
Fast
Ext. ref.
Power-down supply current
Zero scale, See Note 2
PSRR Power supply rejection ratio
Full scale, See Note 3
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]
Slow
2
3.7
1.7
3.8
1.7
3.4
1.4
1
–65
–65
3.6
6.3
3.0
6.3
3.0
5.7
mA mA mA mA mA mA static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INL
DNL
EZS
Resolution
Integral nonlinearity, end point adjusted
Differential nonlinearity
Zero-scale error (offset error at zero scale)
See Note 4
See Note 5
See Note 6
8
±
0.4
±
1 bits
LSB
±
0.1
±
0.5
LSB
±
24 mV
10 ppm/
°
C EZS TC Zero-scale-error temperature coefficient See Note 7
EG Gain error See Note 8
±
0.6
% full scale V
EG TC Gain error temperature coefficient See Note 9 10 ppm/
°
C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref
×
×
106/(Tmax – Tmin).
excluding the effects of the zero-error.
106/(Tmax – Tmin).
output specifications
PARAMETER
VO Output voltage
Output load regulation accuracy
RL = 10 k
Ω
TEST CONDITIONS
VO = 4.096 V, 2.048 V, RL = 2 k Ω
vs 10 k

MIN TYP MAX UNIT
4.2
7 mA
MIN TYP
0
2.6
mA
µ
A
MAX UNIT
VDD–0.4
V
±
0.25
% full scale V
4
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
reference pin configured as output (REF)
PARAMETER
Vref(OUTL) Low reference voltage
Vref(OUTH) High reference voltage
Iref(source) Output source current
Iref(sink) Output sink current
Load capacitance
PSRR Power supply rejection ratio
TEST CONDITIONS
VDD > 4.75 V reference pin configured as input (REF)
VI
RI
CI
PARAMETER
Input voltage
Input resistance
Input capacitance
TEST CONDITIONS
REF = 0 2 V + 1 024 V dc
Fast
Slow
Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
IIH
IIL
Ci
PARAMETER
High-level digital input current
Low-level digital input current
Input capacitance
TEST CONDITIONS
VI = VDD
VI = 0 V
MIN TYP MAX UNIT
1.003
1.024
1.045
2.027
2.048
2.069
1
–1
V
V mA
–65
100 mA pF dB
MIN TYP
0
10
5
1.3
525
– 80
MAX UNIT
VDD–1.5
V
M
Ω pF
MHz kHz dB
MIN TYP MAX UNIT
–1
1
µ
A
µ
A
8 pF analog output dynamic performance
PARAMETER
RL = 10 k
L
RL = 10 k
TEST CONDITIONS
Ω
Ω
,
Ω
,
See Note 11
,
See Note 12
,
See Note 13
Fast
Slow
Fast
Slow
Fast
Slow
MIN TYP
0.8
2.8
0.4
0.8
12
1.8
MAX
2.4
5.5
1.2
1.6
UNIT
µ
µ
V/ s s
µ s
Glitch energy
DIN = 0 to 1, fCLK = 100 kHz,
CS = VDD
5 nV–S
SNR Signal-to-noise ratio
S/(N+D) Signal-to-noise + distortion
53
48
57
47
THD Total harmonic distortion RL = 10 k
Ω
, CL = 100 pF –50 –48
SFDR Spurious free dynamic range 50 62
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
tsu(CS–CK) Setup time, CS low before first negative SCLK edge tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge twH twL
SCLK pulse width high
SCLK pulse width low tsu(D) th(D)
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
MIN NOM MAX UNIT
10 ns
10 ns
25
25
10
5 ns ns ns ns
SCLK X
twL twH
3 4 5 15 1 tsu(D) th(D)
2 16
DIN X D15 tsu(CS-CK)
CS
D14 D13 D12 D1
X
D0 X tsu(C16-CS)
Figure 1. Timing Diagram
6
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
SUPPLY CURRENT vs
FREE-AIR TEMPERATURE
4.5
4
3.5
3
2.5
Fast Mode
I DD
2
Slow Mode
1.5
1
VDD = 5 V
Vref = Int. 2 V
Input Code = 1023 (Both DACs)
0.5
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Free-Air Temperature –
°
C
90
Figure 2
I DD
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 10
POWER DOWN SUPPLY CURRENT vs
TIME
20 60 70 80 30 40 50 t – Time –
µ s
Figure 4
SUPPLY CURRENT vs
FREE-AIR TEMPERATURE
4.5
4
3.5
3
2.5
Fast Mode
I DD
2
Slow Mode
1.5
1
VDD = 3 V
Vref = Int. 1 V
Input Code = 1023 (Both DACs)
0.5
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Free-Air Temperature –
°
C
Figure 3
90
2.064
2.062
2.06
2.058
2.056
2.054
OUTPUT VOLTAGE vs
LOAD CURRENT
Fast Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 4095
Slow Mode
2.052
2.05
0 0.5
1 1.5
2 2.5
3
Source Current – mA
Figure 5
3.5
4
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
4.128
4.126
4.124
OUTPUT VOLTAGE vs
LOAD CURRENT
Fast Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 4095
OUTPUT VOLTAGE vs
LOAD CURRENT
3
2.5
VDD = 3 V
Vref = Int. 1 V
Input Code = 0
Fast Mode
2
Slow Mode
4.122
1.5
4.12
1
4.118
4.116
4.114
0 0.5
1 1.5
2 2.5
Source Current – mA
3
Figure 6
3.5
4
OUTPUT VOLTAGE vs
LOAD CURRENT
5
2.5
2
1.5
4.5
4
3.5
3
VDD = 5 V
Vref = Int. 2 V
Input Code = 0
1
0.5
0
0 0.5
Fast Mode
1 1.5
2 2.5
Sink Current – mA
Figure 8
Slow Mode
3 3.5
4
0.5
0
0 0.5
Slow Mode
3.5
1 1.5
2 2.5
Sink Current – mA
Figure 7
3 4
–40
–50
–60
–70
–80
–90
–100
100
0
TOTAL HARMONIC DISTORTION AND NOISE vs
FREQUENCY
–10
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
–20
–30
Slow Mode
Fast Mode
100000 1000 10000 f – Frequency – Hz
Figure 9
8
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
TOTAL HARMONIC DISTORTION vs
FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
Slow Mode
Fast Mode
100000 1000 10000 f – Frequency – Hz
Figure 10
DIFFERENTIAL NONLINEARITY vs
DIGITAL OUTPUT CODE
0.20
0.15
0.10
0.05
–0.00
–0.05
–0.10
–0.15
–0.2
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
Digital Output Code
Figure 11
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TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
INTEGRAL NONLINEARITY vs
DIGITAL OUTPUT CODE
1.0
0.8
0.6
0.4
0.2
–0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
Digital Output Code
Figure 12
The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
2 REF
CODE
0x1000
[V]
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to
0 must be set to zero. A power-on reset initially puts the internal latches to a defined state (all bits zero).
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI

, and Microwire

.
TMS320
DSP FSX
DX
CLKX
CS
TLV5626
DIN
SCLK
SPI
I/O
MOSI
SCK
CS
TLV5626
DIN
SCLK
Microwire
I/O
SO
SK
CS
DIN
TLV5626
SCLK
Figure 13. Three-Wire Interface
10
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2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
Notes on SPI

and Microwire

: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI

and Microwire

), two write operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the control register are updated automatically on the 16 th
positive clock edge.
The maximum serial clock frequency is given by: f sclkmax
+ t whmin
1
) t wlmin
+ 20 MHz
The maximum update rate is: f updatemax
+
16
1 ǒ t whmin
) t wlmin
Ǔ
+ 1.25 MHz
The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626 has to be considered, too.
D15
R1
The 16-bit data word for the TLV5626 consists of two parts:
D
Program bits (D15..D12)
D
New data (D11..D0)
D14 D13
SPD PWR
D12
R0
D11 D10 D9 D8 D7 D6 D5
12 Data bits
D4
SPD: Speed control bit 1
→
fast mode
PWR: Power control bit 1
→
power down
0
0
→
→ slow mode
normal operation
The following table lists the possible combination of the register select bits: register select bits
R1
1
1
0
0
R0
0
1
0
1
REGISTER
Write data to DAC B and BUFFER
Write data to BUFFER
Write data to DAC A and update DAC B with BUFFER content
Write data to control register
D3 D2 D1 D0
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER
D11 D10 D9 D8 D7
New DAC Value
D6 D5 D4 D3
0
D2
0
D1
0
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
D0
0
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data bits: CONTROL
D11
X
X: don’t care
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
REF1
D0
REF0
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
reference bits
REF1
0
0
1
1
REF0
0
1
0
1
REFERENCE
External
1.024 V
2.048 V
External
D
Set DAC A output, select fast mode, select internal reference at 2.048 V:
1.
Set reference voltage to 2.048 V (CONTROL register):
D15
1
D14
1
CAUTION:
If external reference voltage is applied to the REF pin, external reference MUST be selected.
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
D15
1
D15
1
2.
Write new DAC A value and update DAC A output:
D14
1
D13
0
D12
0
D11 D10 D9 D8 D7
New DAC A output value
D6 D5 D4 D3
0
D2
0
D1
0
D0
0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again.
D
Set DAC B output, select fast mode, select external reference:
3.
Select external reference (CONTROL register):
D14
1
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
4.
Write new DAC B value to BUFFER and update DAC B output:
D15 D14
0 1
X = Don’t care
D13
0
D12
0
D11 D10 D9 D8 D7 D6 D5
New BUFFER content and DAC B output value
D4 D3
0
D2
0
D1
0
D0
0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again.
12
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D
Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V:
D15
1
1.
Set reference voltage to 1.024 V (CONTROL register):
D14
0
D13
0
D12
1
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
2.
Write data for DAC B to BUFFER:
D15 D14
0 0
X = Don’t care
D13
0
D12
1
D11 D10 D9 D8 D7
New DAC B value
D6 D5
3.
Write new DAC A value and update DAC A and B simultaneously:
D4 D3
0
D2
0
D1
0
D15 D14
1 0
X = Don’t care
D13
0
D12
0
D11 D10 D9 D8 D7
New DAC A value
D6 D5 D4 D3
0
D2
0
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
D
Set power-down mode:
D1
0
D15 D14
X X
X = Don’t care
D13
1
D12
X
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
0
D0
0
D0
X
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
Output
Voltage
Negative
Offset
0 V
DAC Code
Figure 14. Effect of Negative Offset (single supply)
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
13

TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (E
ZS
)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (E
G
)
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
14
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
PLASTIC SMALL-OUTLINE PACKAGE D (R-PDSO-G**)
14 PINS SHOWN
14
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
8
0.010 (0,25) M
0.157 (4,00)
0.150 (3,81)
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
Gage Plane
1
A
7
0
°
– 8
°
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
Seating Plane
0.004 (0,10)
DIM
PINS **
A MAX
A MIN
8 14 16
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
4040047 / D 10/96
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
15

www.ti.com
18-Jul-2006
Orderable Device
TLV5626CD
TLV5626CDG4
TLV5626CDR
TLV5626CDRG4
TLV5626ID
TLV5626IDG4
TLV5626IDR
TLV5626IDRG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
Package
Drawing
D
D
D
D
D
D
D
D
Eco Plan
(2)
Pins Package
Qty
8 75 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-1-260C-UNLIM
8 CU NIPDAU Level-1-260C-UNLIM
8
75 Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
8 CU NIPDAU Level-1-260C-UNLIM
8
8
8
8
2500 Green (RoHS & no Sb/Br)
75 Green (RoHS & no Sb/Br)
75 Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1

www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
TLV5626CDR
TLV5626IDR
Package
Type
Package
Drawing
SOIC
SOIC
D
D
Pins
8
8
SPQ
2500
2500
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
12.4
330.0
12.4
A0 (mm)
6.4
6.4
B0 (mm)
5.2
5.2
K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1

www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
TLV5626CDR
TLV5626IDR
Package Type Package Drawing Pins
SOIC
SOIC
D
D
8
8
SPQ
2500
2500
Length (mm) Width (mm) Height (mm)
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2

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