ISSN(Print) 1975-0102
ISSN(Online) 2093-7423
J Electr Eng Technol Vol. 8, No. ?: 742-?, 2013
http://dx.doi.org/10.5370/JEET.2013.8.?.742
Modified Unipolar Carrier-Based PWM Strategy for Three-Level
Neutral-Point-Clamped Voltage Source Inverters
Watcharin Srirattanawichaikul*, Suttichai Premrudeepreechacharn*
and Yuttana Kumsuwan†
Abstract – This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CBPWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI).
Analytical expressions for the relationship between modulation reference signals and output voltages
are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum
and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection
concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of
one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages
of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation
or space vector modulation (SVM) and it’s also simple to implement. The possibility of the proposed
CB-PWM technique has been verified though computer simulation and experimental results.
Keywords: Three-level neutral-point-clamped voltage source inverter, Carrier-based pulsewidth
modulation strategy, Multilevel converter.
standard two-level VSI with the same switching frequency.
However, the drawbacks of this topology are the higher
number of power switches, which adds complexity to the
modulation method. In addition the voltage balance of the
dc-link neutral point is required [5, 32].
In recent year, several modulation strategies for a threelevel NPC VSI have been developed [11-30]. They could
be mainly classified into carrier-based pulsewidth
modulation (CB-PWM) [11-18], space vector modulation
(SVM) [19-26], and selective harmonic elimination (SHE)
[27-30]. Among these PWM strategies, the CB-PWM has
probably been the most popular due to its simplicity of
implementation, which based on the comparison between
the modulation reference signals and two triangular carriers.
Also, several CB-PWM strategies for the three-level
NPC VSI have been extensively researches. The traditional
modulation technique for CB-PWM is sinusoidal
pulsewidth modulation (SPWM). The use of injected zerosequence signals for three-phase sinusoidal reference
voltages initiated the research on non-sinusoidal CB-PWM
[14-16]. Compared with SPWM, the non-sinusoidal CBPWM strategies can extend the linear modulation ranges
make it possible to increase the fundamental of the output
voltages. Reference [12] presented the CB-PWM strategies,
which are essentially two modulation modes (unipolar
mode and dipolar mode). The application of both
modulation modes to three-level NPC VSI has been
equated output voltages. The unipolar mode is the most
widely used at three-level NPC VSI due to the low ripple
output voltages and currents. The voltage balancing control
capability was improved. In [15], an optimal CB-PWM
strategy of three-level NPC VSI was proposed, which
1. Introduction
Multilevel converter topologies has recently been
increasingly applied in medium- and high-voltage, and
medium- and high-power industrial applications, such as
active power filters, static reactive power compensation,
adjustable-speed drive, and renewable energy generation,
due to advantages of high power rating, high quality output
waveforms associated with reduced voltage/current
harmonic distortions, low electromagnetic compatibility
(EMC) concerns, lower common-mode voltage, lower
switching losses, and higher efficiencies when compared to
the conventional two-level voltage source converters [1-3].
Nowadays, there are three generally commercial
classified topologies of multilevel converters in the
literature as diode-clamped converters [4, 5], cascaded Hbridge converters [6-8], and flying-capacitor converters [9],
[10]. Among the various multilevel converter topologies,
the most popular topology in high power industrial
applications is the three-level neutral point clamped (NPC)
voltage source inverter (VSI), which was proposed in 1981
by Nabae et al. [4], as shown in Fig. 1. One advantage of
the three-level NPC VSI topology is that the power
switches and the dc-link capacitors have to endure only
one-half of the dc-link voltage. As a result, the converter
can deal with double voltage and power value than in a
†
Corresponding Author: Department of Electrical Engineering, Faculty
of Engineering, Chiang Mai University, Chiang Mai, Thailand. (yt@
eng.cmu.ac.th)
* Department of Electrical Engineering, Faculty of Engineering,
Chiang Mai University, Chiang Mai, Thailand. (watcharin.cmu@
gmail.com and suttic@eng.cmu.ac.th)
Received: July 1, 2013; Accepted: September 16, 2013
742
Watcharin Srirattanawichaikul, Suttichai Premrudeepreechacharn and Yuttana Kumsuwan
P
analyzed continuous and discontinuous pulsewidth
modulation strategies. However, this conventional
modified method requires two triangular carriers to
generate the gating pulses. A PWM strategy based on
carrier-based concept, capable of controlling the locally
averaged neutral-point current to be equal to zero, was
presented and analyzed [17], which presented a modified
modulation strategy for a three-level NPC VSI. The
minimum and maximum of the sinusoidal three-phase
reference voltages were added to the output reference
voltages obtained from the modified modulation signals.
The proposed modulation strategy completely removes the
low-frequency voltage oscillations that appear in the
neutral-point voltage. In addition, this technique can be
implemented with a very simple algorithm and processed
very fast. Nevertheless, this technique is somewhat
complicated for two triangular carriers are required to
generate the gating pulses.
An even simple modified CB-PWM strategy is proposed.
In this paper, the only one triangular carrier is employed
for the modulation of three-level NPC VSI. The practical
implementation method of the modified unipolar CB-PWM
with a triangular carrier wave was proposed strategy in
conjunction with a zero-sequence voltage injection concept.
The switch states of each leg are determined by comparing
the modified modulation signals and a triangular carrier
wave. The proposed CB-PWM strategy has the following
advantages:
DA1
SA1
Cd1
np
Vd1
DA2
DZA1 SA2
iA
iB
Vd
iZ
Z
iC
DZA2
Cd2
Vd2
A
B
C
DA3
SA3
np
DA4
SA4
N
Fig. 1. Simplified schematic of the power circuit of the
three-level neutral-point-clamped voltage source
inverter.
Table 1. Switching states and pole voltages of a three-level
neutral-point-clamped voltage source inverter
1) it does not need to know the parameters of the
reference voltages;
2) simplifying the algorithm with no need of complex
two/multi triangular carrier or SVM;
3) the fundamental of output voltages are maintain equal
dc-link voltage due to extend the linear modulation
ranges;
4) ideal for closed loop and during dynamic operation.
Switching
Symbols
Sk1
P
O
N
ON
OFF
OFF
Switching States
Sk 2
Sk 3
ON
ON
OFF
OFF
ON
ON
Sk 4
OFF
OFF
ON
Pole Voltage
vkZ
Vd / 2
0
−Vd / 2
switches, twelve anti-parallel-connected freewheeling
diodes, six clamp diodes, and a split dc-link with series
connected capacitors. For example, the inverter leg A is
composed of four active switches S A1 to S A 4 with four
anti-parallel-connected freewheeling diodes DA1 to DA 4 .
The diodes connected to the neutral point Z , DZA1 to
DZA 2 , are the clamping diodes. On the dc-link side of the
inverter, the dc-link voltage capacitor is split into two,
providing a neutral point.
The proposed method has been verified by simulation
and experimental results for three-level NPC VSI.
This paper is organized as follows. Section II presents
principle of three-level NPC VSI. Section III details the
proposed of the CB-PWM strategy. Simulation results are
provided in Section IV to verify the good performance of
the proposed strategy. Section V describes the experimental
results, demonstrating the validity of the proposed method.
Finally, conclusions are presented in Section VI.
2.2 Switching states
The operating status of the switches in the three-level
NPC VSI can be represented by switching states shown in
Table 1, where k denotes one of the three-phase A, B,
or C , and vkZ denotes the each output pole voltage. This
voltage has possible values, namely Vd / 2, 0, and −Vd / 2 .
The switching state ‘P’ denotes that the each phase two
switches, Sk 1 and Sk 2 , are on and the output pole voltage
vkZ , which is the voltage terminal with respect to the
neutral point Z , is Vd / 2 . The switching state ‘N’ implies
that the lower two switches ( Sk 3 and Sk 4 ) conduct and lead
to vkZ = −Vd / 2 . The switching state ‘O’ signifies that the
inside two switches Sk 2 to Sk 3 are on. The output voltage is
clamped to zero through the clamping diodes, DZA1 to DZA 2 .
It can be observed from Table I that two switches of each
2. Three-Level Neutral-Point-Clamped Voltage
Source Inverter and Basic Theory
2.1 Three-level NPC-VSI configuration
Fig. 1 shows the simplified schematic of the power circuit
of the three-level NPC VSI. It consists of twelve active
743
Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters
ωs t = 2π f1t
phase are closed whilst the other two are opened. In other
words, switches Sk 1 and Sk 3 operate in a complementary
manner. With one switched on, the other must be off.
Similarly, Sk 2 and Sk 4 are a complementary pair as well.
In each leg, three valid switching states are available to
generate three voltage levels on the output pole voltage.
(4)
The objective of this section is to present the proposed
CB-PWM strategy, which evaluates performance of the
three-level NPC VSI of Fig. 1.
The traditional CB-PWM strategy takes the instantaneous
average of the maximum and minimum of the three-phase
reference voltages and adds this value from each of the
sinusoidal three-phase reference voltages to obtain the
modulation waveforms. The addition of this zero-sequence
voltage continuously centers all of the three reference
waveforms in the carrier band, which is like to the CBPWM conventional two-level VSI. The CB-PWM
technique can only be used for three-phase three-wire
system, and it enables the modulation index to be increased
by 15.5% before over-modulation.
3.1 Conventional CB-PWM strategy
3.2 Principle of the proposed CB-PWM strategy
Numerous studies about the CB-PWM strategy for the
three-level NPC VSI have been published [12], which
assists to understand the proposed method in this paper.
From their results, it is widely known that the addition of a
zero-sequence voltage v0* selected as (1) to the threephase sinusoidal reference voltages v*A , vB* , vC* in (2) locates
the non-zero voltage vectors in the center of a sampling
period [14]-[16]. It provides an optimum switching
sequence by which it has some advantages, such as lower
harmonic distortion and higher available modulation index
ma , compared with the SPWM technique. The zerosequence voltage v0* can be generated as,
In the traditional CB-PWM strategy, the three-phase
sinusoidal reference voltages including the zero-sequence
voltage v0* for generated the reference voltages of phase
leg voltages. The proposed CB-PWM strategy is a
generalized method that uses the effective three-phase
sinusoidal reference voltage and the maximum and
minimum of the three reference voltages.
The new two variables of modified reference voltage in
the proposed CB-PWM strategy are obtained through
*
*
and vkN
( k ∈ A, B, C ) for
double reference voltages vkP
*
each phase. The modified reference voltages v A, M ,
*
*
vB , M , vC , M are derived as follows:
3. Modulation Strategy
v0* = −
(
)
(
max v*A , vB* , vC* + min v*A , vB* , vC*
)
v*A, M = v*AP + v*AN
*
*
vB* , M = vBP
+ vBN
*
*
vC* , M = vCP
+ vCN
(1)
2
In the traditional modulation method, the three-phase
reference voltages including the zero-sequence voltage v0*
for generated the non-sinusoidal three-phase reference
*
*
*
voltages v A,0 , vB ,0 , vC ,0 can be described by,
v*A,0 = v*A + v0*
vB* ,0 = vB* + v0*
vC* ,0 = vC* + v0*
*
*
, vCP
where v*AP , vBP
are the positive reference voltages and
*
*
*
v AN , vBN , vCN are the negative reference voltages of the
modified reference voltage vk* , respectively.
The positive reference voltages take the minimum of the
three-reference voltages and subtract this value from each
of the three-phase sinusoidal reference voltages, which can
be expressed as,
(2)
where the sinusoidal three-phase reference voltages,
v*A , vB* , vC* , are given by,
v
v = ma sin (ωs t − ( 2π / 3) )
v = ma sin (ωs t + ( 2π / 3) )
*
AP
=
*
vBP
=
v = ma sin (ωs t )
*
A
*
B
(5)
(3)
*
vCP
=
*
C
v*A − min v*A , vB* , vC*
(
)
2
vB* − min v*A , vB* , vC*
(
)
2
vC* − min v*A , vB* , vC*
)
(
(6)
2
Similar to (6), the negative reference voltages takes the
maximum of the three-reference voltages and subtract this
value from each of the three-phase sinusoidal reference
voltages is given as,
where the normalized modulation index ma controls the
voltage magnitude and has range of 0 to 1.0.
In (3), ωs t is the inverter electrical position which may
be related to a desired fundamental frequency f1 of output
voltages by,
744
Watcharin Srirattanawichaikul, Suttichai Premrudeepreechacharn and Yuttana Kumsuwan
v
*
AN
*
vBN
*
vCN
(
)
(
)
(
)
 v*A − max v*A , vB* , vC*

= sgn 
+δ 
2




 vB* − max v*A , vB* , vC*

= sgn 
+δ 
2




 vC* − max v*A , vB* , vC*

= sgn 
+δ 
2




3maVd
sin (ωs t + (π / 6 ) )
2
3maVd
vBC = vBZ − vCZ =
sin (ωs t − ( π / 2 ) )
2
3maVd
vCA = vCZ − v AZ =
sin ( ωs t + ( 5π / 6 ) )
2
v AB = v AZ − vBZ =
(7)
In the linear modulation range in (10), the output line-toline voltages are equal to or less than dc-link voltage Vd .
Therefore, if a three-phase balanced voltage is to be
synthesized using CB-PWM scheme describe above. The
modulation index is defined as,
where sign function (sgn) is defined by +1 or -1, and
δ ∈ {0,1} .
Combining (6) and (7), the modified reference voltages,
v*A, M , vB* , M , vC* , M within the maximum and minimum of the
three reference voltages, is calculated as,
(
 v*A − min v*A , vB* , vC*
v*A,M = 
2


 vB* − min v*A , vB* , vC*
*
vB,M = 
2


*
 vC − min v*A , vB* , vC*
*
vC,M = 
2


)  + sgn  v
*
A
(
)
(
)
(
− max v*A , vB* , vC*
ma =
) + δ 
)
(
)
v An = v AZ − vnZ =
The main proposes of a CB-PWMs strategy of a threelevel NPC VSI are to synthesize the desired output
voltages and to verify the modified duty cycles. The output
pole voltages vkZ , which is the voltage at terminal k with
respect to the neutral point Z of Fig. 1, can be expressed as,
vBn = vBZ − vnZ
(
)
(
)
(
)
(
vCn = vCZ − vnZ
*
A
*
B
*
C
)
(
)
(
)
(11)
(12)
where vnZ is the voltage between the neutral point of the
load n and the neutral point of the dc-link capacitor Z ,
which can be calculated as,

 v − max v , v , v


 + sgn 
+ δ 
2







 vB* − max v*A , vB* , vC*


 + sgn 
+ δ 
2







 vC* − max v*A , vB* , vC*


 + sgn 
+ δ 
2






(9)
*
A
Vdc
1
( 2vAZ − vBZ − vCZ )
3
1
= ( 2vBZ − v AZ − vCZ )
3
1
= ( 2vCZ − v AZ − vBZ )
3
3.3 Output voltages synthesis
* * *
 *
V  vA − min vA , vB , vC
vAZ = d 
2 
2

* * *
 *
V  vB − min vA , vB , vC
vBZ = d 
2 
2

* * *
 *
V  vC − min vA , vB , vC
vCZ = d 
2 
2

2VˆkZ ,1
where VˆkZ ,1 is the fundamental of output pole voltage
(peak value), and the possible the modulation index in the
linear range can be increased beyond ma = 1 to the
maximum modulation ma = 1.15 before over-modulating.
Considering the inverter circuit shown in Fig.1, it can be
seen that if the load is star-connected, the line-to-line
voltages do not clearly define the respective output phase
voltages v An , vBn , vCn , may be expressed in terms of the
phase-to-ground voltages by,
2







 vB* − max v*A , vB* , vC*

 + sgn 
+δ 
2






*
*
*
*

 vC − max vA , vB , vC

 + sgn 
+δ 
2






(8)
(
(10)
vnZ =
1
( vAZ + vBZ + vCZ )
3
(13)
3.4 Calculation of duty cycles
A basic idea of this proposed CB-PWM strategy only
requires the calculation of the independent duty cycles,
which is to consider the output phase voltage in terms of
the modified duty cycles d A , d B , dC may be described by,
where Vd is the dc-link voltage.
Form the above equation, these output pole voltages
v AZ , vBZ , vCZ are determined by the modified reference
*
*
*
voltages v A, M , vB , M , vC , M , directly. In the linear modulation
index range, if the peak value of the line-to-line voltage
is 3maVd / 2 . Therefore, the instantaneous value of the
output line-to-line voltages v AB , vBC , vCA can be expressed
as,
Vd
V
( d AP + d AN ) = d d A
2
2
Vd
Vd
=
( d BP + d BN ) = d B
2
2
Vd
Vd
=
( dCP + dCN ) = dC
2
2
v AZ =
vBZ
vCZ
745
(14)
Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters
v*A
d AP
d AN
v*B
d BP
d BN
vC*
dCP
d CN
δ
Fig. 2. Proposed modified CB-PWM scheme for threelevel neutral-point-clamped voltage source inverter.
Fig. 3. The modified duty cycles for leg A of the
proposed CB-PWM strategy under the condition of
ma = 1.0, sgn = +1, and δ = +1.
where d AP , d BP , dCP are positive duty cycles, and d AN ,
d BN , dCN are negative duty cycles of the modified duty
cycles.
From above expressions, the equations show the
relationships between effective duty cycles and output pole
voltages. Commanded voltages are obtained by first
defining a three-phase set of duty cycles which will be
offset so that they range from 0-100%. By solving (14), the
modified duty cycles for output pole voltage, that is to
divide the dc-link voltage, can be described as,
2v AZ
Vd
2vBZ
+ d BN =
Vd
2vCZ
+ dCN =
Vd
d A = d AP + d AN =
d B = d BP
dC = dCP
Fig. 4. The modified duty cycles for leg A of the
conventional CB-PWM strategies (a) Conventional
CB-PWM 1: ma =1.0, sgn = +1, and δ = 0 (b)
(15)
Conventional CB-PWM 2: ma = 1.0, sgn = -1, and
δ = 0.
where d kP , d kN are the modified upper and lower duty
cycles, respectively.
The modified duty cycles defined by (15) can be
compared to a set of single triangular carrier wave in order
to produce a generalized switching state for the additional
leg. Therefore, the algorithm can be simply implemented
with a triangular carrier and the duty cycles calculation as
shown in block diagram of Fig. 2.
The modified duty cycles of the proposed CB-PWM
strategy are given in Fig. 3. In Fig. 3 (a), the original
sinusoidal modulation signals v*A , vB* , vC* are used to generate
the modified duty cycles in the proposed method. Fig. 3 (b)
shows the modified duty cycle waveforms d AP and d AN
for leg A obtained from application of (6) and (7) to a
sinusoidal set of balanced modulation signals, which a line
period, ma = 1.0, sgn = +1, and δ = +1. The duty cycles
for phase B and C are the same but phase shifted by
± 2π / 3 . From these figures, it can be shown that the
waveforms of the modified duty cycles in phase A
comparative with single triangular wave, which are in the
range 0 to 1. The expression for modified duty cycle d AN
is the same as d AP but inverted and phase shifted of π
radian.
For comparative purposes, the simulated duty cycles of
conventional CB-PWM strategies for three-level NPC VSI
are illustrated in Figs. 4 (a) and (b), which developed in
[17] and [18], respectively. Fig. 4 (a) shows the simulation
duty cycles of conventional CB-PWM 1 for leg A in the
case that ma = 1.0, sgn = +1, and δ = 0. From this result,
it can be seen that the comparison of the duty cycles with
two carriers, which consist of the upper and lower carriers
( vcr1 and vcr 2 ). The positive signals will be compared to
the upper carrier wave vcr1 , while the negative signal will
be compared with the lower carrier wave vcr 2 . In the same
way, the upper duty cycles for double signals of
conventional CB-PWM 2 with ma =1.0, sgn = -1, and δ =
0 are illustrated in Fig. 4 (b). The results indicate that the
duty cycle d AP is the same as d AN but phase shifted of
π radian. This method can also be implemented by using
upper duty cycles but two phase shift carrier waves ( vcr1
and vcr 2 ). The two carrier waves are the same amplitude
and frequency, but out of phase.
From the simulation duty cycles in Figs. 3 (b) and Fig. 4,
all CB-PWM strategies give the same results for the output
voltages, which are good performance. However, the
746
Watcharin Srirattanawichaikul, Suttichai Premrudeepreechacharn and Yuttana Kumsuwan
Fig. 5. Block diagram of the neutral-point voltage control
for proposed modified CB-PWM scheme.
Table 2. The neutral-point voltage control algorithm for
proposed modified CB-PWM scheme, k ∈
{ A, B, C}
d kN > doffset
doffset ≥ 0
d kN < d offset
d kP > d offset
doffset < 0
d kP < d offset
Fig. 6. Simulation waveforms for leg A (a) the modified
duty cycles d AP and d AN (b) gating pulses vS A1 − vS A 4 .
′ = d kP
d kP
′ = d kN − doffset
d kN
′ = d kP − doffset
d kP
d′iN = 0
′ = d kP − doffset
d kP
d′kN = 0
d′kP = 0
(
′ = d kN + d offset − d kP
d kN
)
proposed method is simple and easy to implementation due
to the modified duty cycles utilized only single of the
triangular carrier wave for generates the gating pulse in
three-level NPC VSI.
One of the essential problems of the three-level NPC
VSI is the neutral-point voltage balancing. The improved
neutral-point voltage unbalance by neutral-point voltage
control algorithm is used to solve a problem associated in
[24]. The block diagram of the controller is given in Fig. 5.
The neutral-point voltage unbalanced can be controlled by
changing the offset voltage ( d offset ) which is generated by
the PI controller [31]. The neutral-point voltage control
algorithm for proposed modified CB-PWM can be
formulated as shown in Table 2. The control algorithm is
achieved by applying the magnitude of the offset voltage to
the modified duty cycles of each phase ( d kP , d kN ), which is
′ , d kN
′ ).
generated the duty cycles ( d kP
Fig. 7. Simulation waveforms of dynamic response
operation for a ramp modulation index reference (a)
line-to-line voltage v AB (b) modulation index ma .
For example, Fig. 6 shows the proposed CB-PWM
strategy for the application of a three-level NPC VSI. Fig.
6 (a) shows the simulated waveforms in leg A with
modified duty cycles under the condition of the modulation
index ma = 1.0 and the low switching frequency f s = 550
Hz. In the proposed CB-PWM strategy, only one of
triangular carrier wave vcr is used to generate the gating
pulses vS A1 − vS A 4 , for power switches S A1 and S A 4 , which
are generated by comparing the modified duty cycle
waveforms d AP and d AN with the triangular carrier wave
vcr . The logic of gating pulses for power switches is very
simple as follows: if d AP > vcr ⇒ S A1 = ON , S A3 = OFF
and if d AN > vcr ⇒ S A 2 = ON , S A 4 = OFF . Since the inner
gating pulses S A3 and S A 4 operate are complementary
with S A1 and S A 2 , respectively.
The proposed CB-PWM strategy, operating in dynamic
response, the output voltages of the three-level NPC VSI
system are controlled by adjusting the modulation index ma .
Fig. 7 (a) illustrates the dynamic response for a ramp
output line-to-line voltage v AB . The modulation index
reference increases starting from zero to maximum value (0
to 1.15) for the linear operation mode in 500 ms, with a
switching frequency of 2.5 kHz, as shown in Fig. 7 (b). As
can be seen from simulated waveform, the line-to-line
voltage has five voltage levels at high modulation index
4. Simulation Results
In this section, some simulation results of the proposed
method are presented. The modeling of the three-level
NPC VSI using the proposed CB-PWM strategy has been
implemented in Matlab/Simulink. The general conditions
for the simulations are given as follows: the dc-link voltage
Vd = 550 V and the dc-link capacitors Cd 1 , Cd 2 =4700 µF,
and the fundamental frequency f1 =50 Hz. The three-level
NPC VSI feeds a 4-pole wye-connected induction motor,
with nominal values of 1 kW, 1500 r/min, 220/380 V, 50
Hz.
747
Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters
and three voltage levels at low modulation index and the
result proves that smooth output voltage can be obtained
over the whole range of operation.
The output voltage and current waveforms are given in
Fig. 8 and Fig. 9 with both high ( ma = 0.8) and low
modulation ( ma = 0.5) indexes in steady-state conditions.
Fig. 8 shows the simulated output voltage and current
waveforms of the three-level NPC VSI in high modulation
index, at a switching frequency of 2.5 kHz. The pole
voltage, line-to-line voltage and phase currents iA , iB , iC of
the inverter are illustrated in Fig. 8 (a)-(c), respectively.
This is three voltage levels on the pole voltage v AZ and
the five voltage levels on the line-to-line voltage v AB at
high modulation indexes. The simulated waveforms agree
with the theoretical analysis. The feasibility of the
proposed CB-PWM method and the good quality of the
voltage and control signals are verified. It can be seen that
the voltages are well balanced in the steady-state operation,
while the output phase currents are balanced and almost
sinusoidal even fundamental frequency switching under
high modulation indexes.
As the low modulation index, the output voltages and
currents of the three-level NPC VSI are illustrated in Fig. 8.
Three voltage levels are generated on the output pole
voltage v AZ , and three voltage levels are achieved on the
line-to-line voltage v AB , as shown in Figs. 9 (a) and (b),
respectively. In Fig. 9 (c), the phase currents shown are
high quality sinusoids and are well balanced despite the
open-loop nature of the proposed method algorithm.
The total harmonic distortion (THD) for line-to-line
voltages of three-level NPC VSI with both high and low
modulation indices are about 43.40% and 58.09%,
respectively, as simulated by MATLAB/Simulink. In Fig.
10 (a) and (b), the output line-to-line voltage harmonics
around the switching frequency for the three-level NPC
VSI are 379.6 V and 237.6 V at high and low modulation
indexes, respectively. As all simulation results, it can be
seen that the proposed CB-PWM is good of a three-level
NPC VSI and the voltage balance of the dc-link is
controlled fairly well in the whole modulation index range
of the steady-state operation, even though the proposed
Fig. 8. Simulation waveforms at high modulation index,
ma =0.8 (a) pole voltage v AZ , (b) line-to-line
voltage v AB (c) phase currents iA , iB , iC .
Harmonic Order
(a)
Harmonic Order
(b)
Fig. 10. Simulation harmonic spectrum of line-to-line
voltage v AB with proposed CB-PWM strategy (a)
ma = 0.8 (b) ma = 0.5.
Fig. 9. Simulation waveforms at low modulation index,
ma =0.5 (a) pole voltage v AZ , (b) line-to-line voltage
v AB (c) phase currents iA , iB , iC .
748
Watcharin Srirattanawichaikul, Suttichai Premrudeepreechacharn and Yuttana Kumsuwan
equal to 0.57.
The inverter voltage and current waveforms in steadystate are shown in Fig. 14 for high and low modulation
indices. It can be seen that from both figures there is good
agreement between simulations and experiments, which
obtained in the conditions of Figs. 8 and Fig. 9. Fig. 14 (a)
shows the steady-state waveforms of the pole voltage v AZ ,
line-to-line voltage v AB , and output phase currents iA , iC
when the inverter operates at the modulation index ma = 0.8.
CB-PWM method is simple in its structure.
5. Experimental Results
The experimental set-up of the proposed CB-PWM
strategy for the three-level NPC VSI is represented by the
block diagram shown in Fig. 11. It consists of a dSPACE
DS1104 controller board with TMS320F240 slave
processor, I/O interface board CP1104, a 1 kW four-pole
induction motor. A prototype induction motor drive with a
front-end three-phase diode bridge rectifier and three-level
NPC VSI was built in the laboratory. The setup parameters
are the same as those used for the simulation. The inverter
output is connected to an induction motor using a standard
constant open-loop control method. The machine was
unloaded, operating at 50 Hz.
Fig. 12 shows measured waveforms of duty cycles and
gating pulse for power switches. Fig. 12 (a) shows the duty
cycles d AP and d AN of the conventional CB-PWM 2 at
the modulation index ma = 0.8. It can be seen that the
upper duty cycles for double signals, which indicate that
the duty cycle d AP is the same as d AN but the phase is
shifted of π radian. This conventional method requires
two triangular carriers to generate the gating pulses. Fig. 12
(b) shows the proposed modified duty cycles d AP and
d AN for leg A at the modulation index ma = 0.8, which
use only one of triangular carrier wave for generate the
gating pulses. It can be seen that the experiments resemble
the simulation results. The gating pulses of the power
switches for leg A in the three-level NPC VSI can be
represented in Fig. 12 (c), which generated by the proposed
CB-PWM strategy. It shows an example of gating pulse
arrangements, where vS A1 to vS A 4 be the gating pulses for
power switches S A1 to S A 4 , respectively.
Fig. 13 shows the experimental waveforms of the
dynamic response operation for a ramp modulation index
reference, which increases from zero to the maximum
modulation index ( ma = 1.15). It can be seen that the
output line-to-line voltage waveform proves that smooth
output voltage for the linear operation. Therefore, the low
modulation index becomes limited to a value which is
Fig. 12. Experiment waveforms for leg A : (a) the
conventional CB-PWM 2 duty cycles d AP and
d AN (Scale: 2 V/div), (b) the proposed modified
CB-PWM duty cycles d AP and d AN (Scale: 2
V/div), and (c) the proposed modified CB-PWM
gating pulses for power switches vS A1 , vS A 2 , vS A 3 ,
and vS A 4 (Scale: 20 V/div).
Fig. 11. Experimental set-up.
749
Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters
shown that the line-to-line voltage v AB of the inverter
under steady-state operation is generated by the three-level
voltage and has a amplitude of Vd / 2 . The line-to-line
voltage is identical to that of a conventional two-level
inverter. The closely match of simulation and experimental
results well verify the feasibility and validity of the
proposed strategy. In addition, from both simulation and
experimental results, it can be seen that the voltage
waveforms generated by the proposed CB-PWM strategy
are stable in the steady-state condition.
Fig. 15 shows the steady-state voltage and current
waveforms of the conventional CB-PWM 2 for high and
low modulation indices. It can be seen from both figures
that there is good agreement and the experimental results
of the proposed method in Fig. 14 are close to conventional
CB-PWM 2. Again, the conventional method requires two
triangular carriers for generate the gating pulses, which is a
complex implementation.
Fig. 16 shows the harmonic spectrum of the line-to-line
voltages of three-level NPC VSI using the proposed CBPWM strategy with a switching frequency f s = 2.5 kHz.
The fundamental output line-to-line voltage under the
The line-to-line voltage of the inverter under steady-state
operation generated by the five-level inverter can be clearly
appreciated in the voltage waveform.
Similarly, Fig. 14 (b) also show voltage and current
waveforms of the proposed method can be applied for low
modulation index, ma = 0.5. From these results, it can be
Fig. 13. Experimental waveforms of dynamic response
operation for a ramp modulation index reference
(a) line-to-line voltage v AB (Scale: 250 V/div), (b)
modulation index ma (Scale: 5 V/div).
Fig. 14. Experiment waveforms of the proposed modified
CB-PWM: pole voltage v AZ (Scale: 500 V/div),
Fig. 15. Experiment waveforms of the conventional CBPWM 2: pole voltage v AZ (Scale: 500 V/div), line-
line-to-line voltage v AB (Scale: 250 V/div), and
to-line voltage v AB
output phase currents iA , iC at no load (Scale: 1.5
output phase currents iA , iC at no load (Scale: 1.5
A/div) (a) modulation index
ma = 0.8 (b)
(Scale: 250 V/div), and
A/div) (a) modulation index
modulation index ma = 0.5.
modulation index ma = 0.5.
750
ma = 0.8 (b)
Watcharin Srirattanawichaikul, Suttichai Premrudeepreechacharn and Yuttana Kumsuwan
Table 3. The output voltage and THD for line-to-line
voltages between simulation and experimental
results under various modulation index.
Modulation
index
1.15
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
(a)
Simulation
results
Experimental results
VˆAB ,1
%THD
VˆAB ,1
%THD
545.40
540.51
518.45
428.70
379.60
335.30
292.80
237.60
186.60
144.50
98.45
42.15
45.89
46.38
47.42
47.64
44.40
40.66
41.11
58.09
88.03
121.74
158.89
209.56
551.35
544.63
520.22
433.40
384.50
336.33
298.43
238.90
191.55
148.89
108.95
49.92
47.21
47.22
48.53
48.21
46.13
41.39
42.21
58.88
89.05
123.35
160.64
210.62
(b)
Fig. 16. Experimental harmonic spectrum of line-to-line
voltage with proposed CB-PWM strategy (a) ma =
0.8 (b) ma = 0.5.
Fig. 17. THD for the output line-to-line voltages with
modulation index of the three-level NPC VSI for
different CB-PWM strategies.
condition of ma = 0.8 and 0.5 had a value of 384.5 V and
238.9 V, respectively. The THD was showed from 46.13%
in the high modulation index and 58.88% in the low
modulation index. Experimental results and simulated ones
presented in Fig.16 and Fig. 10 are in close agreement.
Furthermore, in order to verify the proposed CB-PWM
strategy for three-level NPC VSI by the simulation results
and compared with experimental results, as shown in Table
3. It can be observed that the differences of the output
voltage and THD for line-to-line voltages between
simulation and experimental are a very good agreement the
whole modulation index ranges (0.1-1.15) and their
corresponding the graph in Fig. 17.
Fig. 17 summarizes the comparison results of the line-toline voltage total harmonic distortion for the conventional
and proposed CB-PWM strategies. The THD is evaluated
in the whole linear modulation index ranges (0.1-1.15)
with incremental step size of 0.1 under 2.5 kHz switching
frequency condition. It can be seen that the experimental
results of the proposed method are close to conventional
CB-PWM strategies (CB-PWM 1 and CB-PWM 2). In the
all experimental, the output line-to-line voltages THD
between the proposed and other conventional CB-PWM
strategies are almost no difference values. However, the
advantage of the proposed method can be implemented
easily than other conventional strategies because it is used
only one of the triangular carrier wave for generating the
gating pulses in the three-level NPC VSI.
6. Conclusion
This paper presented a novel CB-PWM strategy for the
three-level NPC VSI. The novelty of the proposed CBPWM strategy is that only single of the triangular carrier
wave is employed to for generate the gating pulses in the
three-level NPC VSI and significantly simplify the
modulation strategy. Experimental results confirmed the
good performance with quality to the output voltages and
the almost sinusoidal output phase currents in the dynamic
and steady-state operations under high and low modulation
indices. The feasibility and reliability of the proposed
modulation strategy has been verified by both computer
751
Modified Unipolar Carrier-Based PWM Strategy for Three-Level Neutral-Point-Clamped Voltage Source Inverters
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drive system. Finally, the main advantages associated were
simple PWM algorithm, reduce capacitor voltage ripple,
lower switching frequencies, and easily hardware
implemented.
Acknowledgements
The work was supported by the Thailand Research Fund
(TRF) through the Royal Golden Jubilee Ph.D. Program
and National Research University (NRU) Project from
Office of the Higher Education Commission of Thailand.
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power electronics, energy conversion systems, and electric
drives.
Suttichai Premrudeepreechacharn
received the B.Eng. degree in electrical
engineering
from
Chiang
Mai
University, Chiang Mai, Thailand, in
1988 and the M.S. and Ph.D. degrees
in electric power engineering from
Rensselaer Polytechnic Institute, Troy,
New York, USA, in 1992 and 1997,
respectively. Since 2002, he has been an Associate
Professor with the Department of Electrical Engineering,
Faculty of Engineering, Chiang Mai University. His
research interests include power quality, high-quality utility
interfaces, power electronics, and artificial-intelligenceapplied power systems.
Yuttana Kumsuwan received the
M.Eng. degree in electrical engineering
from King Mongkut’s Institute of
Technology Ladkrabang, Bangkok,
Thailand, in 2000 and the Ph.D.
degrees in electrical engineering from
Chiang Mai University, Chiang Mai,
Thailand, in 2007.
Since 2011, he has been an Assistant Professor in the
Department of Electrical Engineering, Faculty of
Engineering, Chiang Mai University. He was a visiting
professor at the Texas A&M University, College Station,
United States, from October 2007 to May 2008, and at
Ryerson University, Toronto, ON, Canada in March to May
2010. His research interests include power electronics,
energy conversion systems, and electric drives.
Watcharin Srirattanawichaikul
received the B.Eng degree in electrical
engineering (First class honors) from
King Mongkut’s Institute of Technology Ladkrabang, Bangkok, Thailand,
in 2006 and the M.Eng. degree in
Electrical Engineering from Chiang
Mai University, Chiang Mai, Thailand,
in 2008. He is currently working toward his Ph.D. at
Chiang Mai University. His research interests include
753