Cache
What you
will Learn
Cache
• What are the 603ev caches?
• How the caches process fetch, load, and store
• What is write-through and write-back?
• What is snooping?
• How data cache processes a snoop hit
• How to enable cache from hard reset
• How to invalidate cache
8-1
What is the 603e Cache? (1 of 3)
The Data and Instruction Caches are both 16 KByte, four way set associative
physically addressed caches. The caches have 128 sets, 4 lines per set, and a 8
word line (block) size. I-cache is read only. D-cache is read/write.
19 20
0
26 27 29 30 31
Cache
Instruction/Data Pointer
Structure
Byte
D
A
20
select-D
7
Word select-I
Definition
way0
way1
B
way2
8 words E
8 words
tag
L
R
U
tag
way3
8 words
tag
8 words
tag
C
MMU
hit
line mux
A. 20 bits of the instruction or data pointer indexes into the MMU to find translated (physical)
address while 7 bits of the pointer indexes into cache to find the set tags to be compared.
B. Physical address from MMU is compared to all four ways of indexed set.
C. If the tag of a way matches, a hit occurs and the associated 8 words are multiplexed to a line
buffer.
D. For instruction cache, bits 27 thru 29 select which of the 8 words goes on to the dispatch
queue. For data cache, bits 27 thru 31 select which of the 32 bytes are returned.
•If no tag matches, a miss occurs and an external burst read occurs with the critical double word
(the one requested by the instruction unit) accessed first, followed by the sequential access of the
other three double words in the line.
E. The new line is written to the way determined by the LRU (least recently used).
•The instruction cache is not snooped, but the data cache is.
Cache
8-2
What is the 603e Cache? (2 of 3)
Way
Structure
Instruction
Cache Line
States
set 0
set 1
set 2
set 3
tag
tag
tag
tag
state
state
state
state
words 0 - 7
words 0 - 7
words 0 - 7
words 0 - 7
set 124
set 125
set 126
set 127
tag
tag
tag
tag
state
state
state
state
words 0 - 7
words 0 - 7
words 0 - 7
words 0 - 7
Each line may be in one of two states:
1. Invalid: line is invalid data.
2. Exclusive: line contains valid instructions.
1. Each “way” consists of three fields: a tag, a state, and 8 words.
2. The tag field contains a 20 bit value which will be compared with the most significant 20
bits of the physical address.
3. The 8 words are the data of this line.
4. The state field indicates the state of this line; for example, is the line valid.
5. In the instruction cache, each line is in one of two states: invalid or exclusive.
Cache
8-3
What is the 603e Cache? (3 of 3)
Data
Cache
Line
States
Cache
Each line may be in one of three states:
1. Invalid: line is invalid data.
2. Exclusive: line contains valid data which is the same as in memory.
3. Modified: line contains valid data which has been written to the cache, but
not written to memory.
8-4
How the Instruction Cache Processes a Fetch
Introduction The diagram below shows the response of the instruction cache to a fetch.
Flow
Diagram,
Instruction
Fetch
Start
Fetch request occurs
Cache
hit?
Y
Return
instruction
End
N
Executes a burst read;
fills cache line*
line state set to
exclusive
End
State Description
E
Exclusive
I
Invalid
* Specific line determined by bits 20-26 and LRU
Cache
8-5
How the Data Cache Processes a Load
Introduction The diagram below shows the response of the data cache to a load.
Flow
Diagram,
Data
Load
Start
Load instruction occurs
Cache
hit?
Y
Return
data
End
N
Determines line*
State=M?
Y
Moves line to
write buffer
N
Executes a burst read;
fills cache line
line state set to
exclusive
End
State Description
M
Modified
E
Exclusive
I
Invalid
* Specific line determined by
bits 20-26 and LRU
1. The line in the write buffer will be written to memory when the 603e has the resources
available.
Cache
8-6
How the Data Cache Processes a Store, Write-Through (1 of 2)
Introduction Here the meaning of “write-through” is defined and the response of the data
cache to store to a page with the write-through attribute is shown.
WRITE CACHE HIT
WriteThrough
Flow
Diagram
MMU
Integer
Unit
6
WRITE CACHE MISS
Integer
Unit
Cache
5
5/6
Cache
Main
Memory
5/6
Main
Memory
6
No memory is
allocated in
cache for the 6
(no-allocate)
5/6
A page is assigned the write-through attribute in an MMU page descriptor.
1. For a write hit, the data is written to the cache and also to the external memory.
2. For a write miss, data is written only to external memory.
Cache
8-7
How the Data Cache Processes a Store, Write-Through (2 of 2)
Start
Data
Cache
Flow
Diagram,
WriteThrough
Store instruction occurs
Cache
hit?
N
Write data to
memory
End
Cache
Y Write data to
cache line
line state set to
exclusive
State Description
M
Modified
E
Exclusive
I
Invalid
8-8
How the Data Cache Processes a Store, Write-Back (1 of 2)
Introduction Here the meaning of “write-back” is defined and the response of the data cache
to store to a page with the write-back attribute is shown.
WriteBack
Flow
Diagram
WRITE CACHE HIT
Integer
Unit
6
WRITE CACHE
MISS (1/2)
Integer
Unit
Integer
Unit
6
Cache
5/6
cache miss
Cache
5
5/6
Main
Memory
5
Cache
Burst read
from memory
Main
Memory
MMU
6
WRITE CACHE
MISS (2/2)
Main
Memory
5
A page is assigned the write-back attribute in an MMU page descriptor.
1. For a write hit, data is written only to the cache.
2. For a write miss, the line of data in external memory is loaded into the cache and the data is
written only to the cache.
Cache
8-9
How the Data Cache Processes a Store, Write-Back (2 of 2)
Start
Store instruction occurs
Data
Cache
Flow
Diagram,
Write-Back
Y
Cache
hit?
Writes data to
cache line
N
End
Determines line*
State=M?
Y
N
Executes a burst read;
fills cache line
Moves displaced
line to
write buffer
State Description
M
Modified
E
Exclusive
I
Invalid
Write data to cache line
line state set to
modified
line state set to
modified
End
* Specific line determined by
bits 20-26 and LRU
1. The line in the write buffer will be written to memory when the 603e has the resources
available.
Cache
8 - 10
What is Snooping?
Definition
Block
Diagram
If a bus master (not 603ev) has the bus and asserts pins for a global memory
access, 603ev “snoops” the access and checks for a matching data cache entry.
Snooping ensures that the bus master will get current data that 603ev may have
updated.
603ev
Master
RAM
Address Bus
Data
Cache
Control Signals
1. If no match, it is a snoop miss.
2. If a match, it is a snoop hit.
1. If the master has the bus and accesses RAM and if the access is global as indicated on the
control signals, 603ev will check if this address is cached in the data cache.
2. If it is a snoop miss, 603ev does nothing.
3. If it is a snoop hit on a line with M, 603ev executes a snoop push.
4. If it is a snoop hit on a line with E, and if the master processor indicates caching, then 603ev
invalidates the line.
Cache
8 - 11
How the Data Cache Processes a Snoop
Introduction The diagram shown below shows how data cache processes a snoop.
Start
Data
Cache
Snoop Hit
Flow
Diagram
Global external access is asserted
Snoop
hit?
N
State Description
M
Modified
E
Exclusive
I
Invalid
End
Y
line
state?
M
Execute a
snoop push
E
N
End
To be
cached?
Y
line state set to
invalid
To be
cached?
N
line state set to
exclusive
Y
End
1. A snoop push will be described in another chapter, but basically it means that the data in the
cache line will be written to memory.
Cache
8 - 12
Programming Model (1 of 2)
HID0 - Hardware Implementation Register 0
p. 2-11
7
0
1
2
3
4
5
6
EMCP
0
EBA
EBD
SBCLK
0
ECLK
PAR
8
9
10
11
12
13
14
15
DOZE
NAP
SLEEP
DPM
RISEG
0
0
NHR
16
17
18
19
20
21
22
23
ICE
DCE
ICFI
DCFI
0
0
24
25
26
27
28
29
30
31
IFEM
0
0
FBIOB
ABE
0
0
NOOPTI
ILOCK DLOCK
• In the 603, bit 5 is EICE, but this function has been removed for the 8260.
• IFEM and ABE have been added to the 603 model.
ABE - Address Broadcast Enable: if ABE=1, the dcbf, dcbi, and dcbst instructions
will broadcast. Otherwise, only dcbz will broadcast. Setting ABE is necessary to
properly manage an L2 cache.
1. Enabling, locking, and flushing of cache can be controlled by the user with
the special purpose register, HID0.
2. Although it is a 32-bit register, only 6 bits are used to control these
functions.
3. ICE and DCE control enabling, ILOCK and DLOCK control locking, and
ICFI and DFCI control flushing.
Cache
8 - 13
Programming Model (2 of 2)
HID2 - Hardware Implementation Register 2
0
1
2
3
4
5
6
12
13
14
p. 2-15
7
8
9
10
11
-
16
17
18
19
SFP
20
IWLCK
24
25
15
21
22
23
30
31
26
DWLCK
27
28
29
-
• IWLCK and DWLCK allow the cache to be locked one way at a time.
xWLCK
000
100
110
111
Cache
Result
No ways locked
Way 0 locked
Way 0-1 locked
Way 0-2 locked
8 - 14
How to Load and Lock I-Cache, Way 0
Example
Code
/*
/*
/*
/*
/*
/*
/*
/*
/*
Assumptions: interrupts are turned off, cache */
has been flushed, executing from cache*/
inhibited memory, and MMU on.
*/
LR and r6 = starting address of code to lock */
CTR = number of cache blocks to lock
*/
r2 = nonzero numerator and denominator
*/
‘loop’ must begin on an 8-byte boundary to en-*/
sure that the divw and beqlr are fetched with */
the same cycle.
*/
mfspr r5,HID2
ori
r5,r5,0x8000
loop:
divw. R2,r2,r2
beqlr+
addi r6,r6,32
mtlr r6
bc 17,0,loop
mtspr HID2,r5
isync
Cache
/* get HID2
/* lock temp way 0
/*
/*
/*
/*
/*
/*
*/
*/
divide <>0 result
*/
cause the pre-load */
next blk to pre-load*/
set next block
*/
dec ctr & branch=0 */
lock way 0
*/
8 - 15
How to Enable Instruction Cache from Hard Reset
Example
Code
From hard reset, the caches are invalidated and disabled. The instruction
cache can be enabled using the following program:
mfspr r5,HID0
ori
r5,r5,______
andi r6,r5,______
_____________
isync
sync
_____________
isync
sync
Cache
;copy HID0 to gpr
;set ICE and ICFI
;save ICFI off
;invalidate and enable
;clear flash invalidate
8 - 16
Cache Instruction Summary
Instruction
dcbt rA,rB
dcbtst rA,rB
dcbz rA,rB
dcbst rA,rB
dcbf rA,rB
icbi rA,rB
dcbi rA,rB
Cache
Description
Data cache line touch
Data cache line touch for store
Data cache line zero
Data cache line store
Data cache line flush
Instruction cache line invalidate
Data cache line invalidate
Useful for ...
Performance improvement
Performance improvement
Quick init of scratch area
Update memory
Update memory, cache invalid
8 - 17