Operational Amplifier Stability
Part 10 of 15: Capacitor Loop Stability: Riso with Dual Feedback
by Tim Green
Linear Applications Engineering Manager, Burr-Brown Products from Texas Instruments
Part 10 of this series is the sixth and final verse of our familiar electrical engineering tune, “There must
be six ways to leave your capacitive load stable.” The six ways are Riso, High Gain & CF, Noise
Gain, Noise Gain & CF, Output Pin Compensation, and, what we cover here: Riso w/Dual Feedback.
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This topology is very often used to buffer a precision reference integrated circuit. As a voltage buffer,
the op amp circuit provides higher source and sink currents than can be originally driven from the
precision reference. Although we will look specifically at the gain of one, voltage follower
configuration, the Riso w/Dual Feedback can be used with gains greater than one with slight
modifications to the formulae provided. We will look at the two dominant types of op amp topologies,
bipolar emitter-follower and CMOS RRO. The analytical and synthesis steps and techniques will be
similar, but there are subtle differences -- enough to warrant looking at each respective output
topology. As an added bonus we will purposely violate our rule-of-thumb guide and create the BIG
NOT to see the effects of improper stability compensation.
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EN
From our stability analysis tool kit the Riso w/Dual Feedback technique will be presented by firstorder analysis, confirmed through TINA-TI (a fully functional SPICE program loaded with TI models)
loop stability simulation, checked by the Vout/Vin ac transfer function analysis in TINA-TI, and
finally sanity-checked by the Transient Real World Stability Test run in TINA-TI. This Cload stability
technique has been confirmed to work as predicted in real-world, actually-built circuits at some time
over the last 25 years. However, due to resource limitations, each circuit specifically presented here
has not been built, but rather is left to the reader as an exercise or the application of each technique to
his/her own individual application (ie analyze, synthesize, simulate, build and test).
Bipolar Emitter-Follower: Riso w/Dual Feedback
As
The bipolar emitter-follower we will choose to analyze the Riso w/Dual Feedback technique is the
OPA177, as detailed in Fig. 10.1. The OPA177 is a low drift, low input offset voltage op amp capable
of being powered from ±3 V to ±15 V.
OPA177
Precision Operational Amplifier
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Specification
+/-3V to +/-15V
1.3mA typical
10uV typical
0.1uV/C typical
+/-0.5nA typical
85nVrms (1Hz to 100Hz)
(V-)+2V to (V+)-2V
600kHz
140dB
60 ohms
0.3V/us
2V typical (RL=2k)
DIP-8, SO-8
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Parameter
Supply Voltage
Quiescent Current
Offset Voltage
Offset Drift
Input Bias Current
Input Voltage Noise
Input Voltage Range
Gain-Bandwidth Product
Open Loop Gain
Open Loop Output Resistance
Slew Rate
Voltage Output Swing from Rail
Package
EN
Fig. 10.1: Bipolar Emitter-Follower Op Amp Specifications
As
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Note that in a typical bipolar emitter-follower topology (see Fig. 10.2) both the positive and negative
output drives to Vo are bipolar emitter-followers. Very few op amp data sheets today include
equivalent schematics that would tell us the topology of the output stage used inside of the op amp. As
such it is only through factory only information that we are assured of the topology.
Fig. 10.2: Typical Bipolar Emitter-Follower Op Amp Topology
The Riso w/Dual Feedback circuit we will analyze for Bipolar Emitter-Follower op amps is shown in
Fig. 10.3. Through RF direct feedback is provided across the load, CL, and thereby forces Vout to
equal VREF. FB#2, through CF, provides a second feedback path, which dominates at high frequency,
to guarantee stable operation. Riso creates the isolation between FB#1 and FB#2. Notice than in many
of our previous techniques for stabilizing capacitive loads we used the modified Aol approach where
the output impedance of the op amp and capacitive load modified the op amp Aol curve, on which we
plotted a 1/ which would make the circuit stable. With the Riso w/Dual Feedback technique we will
find it easier to leave the op amp Aol curve unmodified and to plot FB#1 1/ and FB#2 1/. We will
then use superposition to arrive at a net 1/ curve which, when plotted on the op amp Aol curve, will
allow us to easily synthesize a solution to this capacitive load stability problem.
RF100k
ne
t
FB#1
CF82n
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FB#2
VEE12
VO 5V
U2REF02
-
VREF 5V
++
5V
CL10u
on
REF02
Trim
Out
EN
U1OPA177E
Vin
Gnd
Vout
Riso26.7
is
he
d
VCC12
Pu
bl
Dual Feedback:
FB#1 through RF forces accurate
Vout across CL
FB#2 through CF dominates at high frequency for stability
Riso provides isolation between FB#1 and FB#2
Fig. 10.3: Riso With Dual Feedback: Emitter-Follower
As
Having a chosen op amp, the Aol Test Circuit (Fig. 10.4) will give us a stability analysis starting point.
VG1
CT1T
R2100k
+
DC = 0Vpk
AC = 1Vpk
LT1T
VEE12
R11k
U1OPA177E
Vout
++
VCC12
Aol = Vou t / VM
104.65uV
Aol Curve Test Circuit:
Almost 0 volts
no DC load across R2
no DC Io
Our Circuit measures unloaded
Aol
R2, R1 provide AC path for high pass filter with CT
R2, R1 provide AC path for low pass filter with LT
Fig. 10.4: Aol Test Schematic: Emitter-Follower
The Aol curve can be obtained from the data sheet, or measured in our TINA-TI simulation as shown
here. This circuit, using dual power supplies, allows us to measure the unloaded Aol curve since Vout
is nearly zero volts and our input common mode voltage specification is easily met. R2 and R1
together with LT provide an ac path for the low-pass filter function, which allows us dc short circuit
and ac open circuit in the feedback path. Remember, TINA-TI must perform a closed-loop dc analysis
to find the operating point of the circuit before it can perform an ac analysis. R2 and R1, together with
CT provide an ac path for the high-pass filter function, which allows us dc open circuit and ac short
circuit into the input. LT and CT are chosen as large values to ensure their respective operations of
shorts and opens at any ac frequency of interest.
In the OPA177 Aol Curve as a result of simulation (Fig. 10.5) the unity gain bandwidth is 607.2 kHz.
T
a
160
140
Aol
120
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80
60
40
20
0
-20
10m
100m
1
10
100
-G
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Gain (dB)
100
1k
10k
100k
1M
100k
1M
Frequency(Hz)
180
Gain :
Aol A:(607.2k; -162.31m)
90
Phase :
Aol A:(607.2k; 51.06)
on
Phase (degrees)
EN
Aol
135
0
10m
100m
is
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d
45
1
10
100
1k
10k
Frequency(Hz)
Pu
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Fig. 10.5: Aol Test Results: Emitter-Follower
As
We must now measure Zo (small signal ac open loop output impedance) as shown (Fig. 10.6). This
TINA-TI test circuit will test the unloaded Zo of the OPA177. R2 and R1 together with LT provide an
ac path for the low-pass filter function which allows us dc short circuit and ac open circuit in the
feedback path. The dc operating point is shown to be nearly zero volts at the output which means no
current is flowing into, or out of, the OPA177. Zo is now easily measured by our application of a
1 Apk ac current generator, which we will sweep over the ac frequency range of 10 MHz to 1 MHz.
Zo = Vout, and if we convert the results from dB to linear or logarithmic, Vout will be Zo in ohms.
R2100k
LT1T
VEE12
Zo = Vout
R11k
U1OPA177E
+
Vout
+
VCC12
IG1
104.65uV
DC = 0A
AC = 1Apk
No Load – Zo Test Circuit:
Almost 0 volts
no DC load across R2
R2, R1 provide AC path for low pass filter with LT
no DC Iout
Fig. 10.6: No Load Zo Test Circuit: Emitter-Follower
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The OPA177 Zo (Fig. 10.7) is seen to be characteristic of bipolar emitter-follower output stages with
Ro dominating the only component of output impedance within the unity-gain bandwidth. Ro is 60 .
EN
Fig. 10.7: Zo, Open Loop Output Impedance: Emitter-Follower
VEE 12
on
VOA
U2REF02
-
U1OPA177E
REF02
Trim
Out
E xternal
VO
Vout
Riso26.7
Model
is
he
d
Vin
Gnd
++
Zo
CL10u
VREF
As
Pu
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VCC12
Zo External Model:
U1 is complete SPICE
macromodel of OPA177 with data sheet
Zo is moved outside of the op amp
macromodel to form a new
Allows for simulation of 1/
with effects of
Zo and external loads
Aol curve and
macromodel
Zo
Fig. 10.8: Zo External Model: Emitter-Follower
In order for our 1/ analysis to include the effects of Zo interacting with Riso, CL, CF and RF, we need
to move Zo outside of our op amp macromodel so we can probe the necessary nodes in our circuit.
This concept (Fig. 10.8) will provide the data sheet Aol curve and be buffered from any effects of
Riso, CL, CF and RF.
RF100k
CF82n
VFB 4.999V
VEE12
Zo ExternalModel
U2REF02
U1OPA177E
Vin
Gnd
VOA 4.9991V
VCV1
REF02
+
Trim
Out
x1
+
VREF 4.999V
VO 4.9991V
Ro60
+
+
-
-
Vout
Rsi o26.7
4.9991V
CL10u
VCC12
Zo External Model:
VCV1 ideally isolates U1 so U1 only provides data sheet
Aol with no effects of
Zo and external loads
Set Ro to match measured Ro
Remove any large DC load
Analyze with unloaded Ro (largest Ro) which creates worst instab
ility
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Fig. 10.9: Zo External Model Details: Emitter-Follower
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The Zo external model (Fig. 10.9) allows us to measure the effects of Zo interacting with Riso, CL, RF
and CF on 1/. In our Zo External Model set Ro = Ro OPA177, measured to be 60 . The voltagecontrolled voltage source, VCV1, isolated our op amp macromodel, U1, from Ro, Riso, CL, CF and
RF. VCV1 is set to x1 to keep the data sheet Aol gain the same. Remove any large dc load since we
want to analyze this circuit under worst case stability conditions which will be with CL only and our
calculated unloaded Zo (Ro=60 for this case). VOA is an internal node to the op amp, which in the
real world cannot be measured. It is also not easy to access this internal node on many SPICE
macromodels. 1/ is analyzed relative to VOA to include the effects of Ro, Riso, CL, CF, and RF.
Final stability simulation in TINA-TI, without using the Zo External Model, cannot plot 1/ but can
plot loop gain to confirm our analysis using the Zo external model.
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First we will analyze FB#1 (Fig. 10.10). Notice that CF is treated as an open since we are only going to
analyze FB#1. Later we will analyze FB#2 and then, using superposition, combine the two feedback
paths for the net 1/. The results of our analysis are shown above with the derivations and details
shown in the next slide. We see a zero in the FB#1 1/ plot at fzx = 183.57 Hz. The low frequency 1/
value is one. If this had gain, the low frequency 1/ value would be greater than one.
As
F B#1
VFB
RF100k
CF
FB#1 1/ :
VEE12
Vtrim
Z o ExternalModel
VOA
U1OPA177E
Vin
Gnd
VO
VCV1
-
U2REF02
REF02
Trim
Out
Ro60
x1
+ +
+
+
-
-
Riso 26.7
Vout
CL10u
VREF
Zero: fzx =
1
2 (Ro+Riso) CL
1
fzx = 2 (60+26.7) 10u
VCC12
fzx = 183.57Hz
FB#1 Analysis:
1/ zero due to combination of CL interacting with RO +
Low frequency 1/
set by open CL and feedback through RF
CF is treated as an open since we are using superposition and an
Riso
1/ = 1 (f=0) for Low-f 1/
alyzing FB#1 only
Fig. 10.10: FB#1 Analysis: Emitter-Follower
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Fig. 10.11: FB#1 1/ Derivation: Emitter-Follower
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In Fig. 10.11 the derivation for FB#1 is shown on the left. Since 1/ is the reciprocal of , FB#1 1/
calculation is easily derived as shown on the right. We see that the pole, fpx, in the derivation
becomes the zero, fzx, in the 1/ derivation.
A ol = V OA
F B#1
VFB
LT1T
4. 999V
RF100k
CT1T
F B#1: 1/ B et a1= V OA / V FB
Loop Gain = V FB
As
+ VG1
Vtrim
VEE12
1. 2298V
Z o Ext ernal Model
VOA
U2REF02
-
Vin
Gnd
REF02
+
++
Trim
Out
VREF
Ro60
VCV1
U1OPA177E
VO
4. 9991V
4. 9991V
x1
Vout
Riso26.7
4. 9991V
+
-
CL10u
4. 999V
VCC12
Fig. 10.12: FB#1 Analysis Ac Circuit: Emitter-Follower
We will use the circuit in Fig. 10.12 to perform ac analysis, using TINA-TI, to find 1/ for FB#1, Aol,
and loop gain for this circuit using only FB#1. Because of this we eliminate CF from the schematic.
FB#1 1/ results are plotted (Fig. 10.13) on the OPA177 Aol curve. At fcl, where loop gain goes to
zero, we see that the rate-of-closure is 40dB/decade:
[(–20 dB/decade from Aol) – (+20 dB/decade from FB#1 1/) = –40 dB/decade rate-of-closure]
which, from our rate-of-closure rule-of-thumb indicates instability. Our analysis of FB#1 was low
frequency 1/ = one, with a zero, fzx, at 183.57 Hz. As can be seen (Fig. 10.13) our first-order analysis
predicted accurately FB#1 1/.
a
T
160
b
140
OPA177 Aol
120
100
fcl
FB#1 1/ :
A:(197.4488m; 5.1139u)
B:(183.57; 3.0107)
60
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Gain (dB)
80
FB#1 1/ 20
fz x
0
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40
STABLE
-20
10m
100m
1
EN
-40
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
on
Fig. 10.13: FB#1 1/ Plot: Emitter-Follower
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In Fig. 10.14 we see loop gain analysis of our circuit using only FB#1 and it shows that we have close
to zero phase margin at fcl where loop goes to zero. This is definite confirmation that we have an
unstable circuit. The poles and zeros in the loop gain plot can be predicted, by inspection, from the
FB#1 1/ plot on the Aol curve in Fig. 10.13.
160
FB#1 Loop Gain
140
120
80
40
20
As
Gain (dB)
100
60
a
Pu
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T
0
-20
-40
10m
100m
1
10
100
1k
Frequency(Hz)
10k
100k
1M
10M
100k
1M
10M
fcl
180
Gain :
A:(10.146k; 1.2898)
Phase :
135
STABLE
Phase [deg]
A:(10.146k; 358.0837m)
90
45
0
10m
100m
1
10
100
1k
10k
Frequency(Hz)
Fig. 10.14: FB#1 Loop Gain Analysis: Emitter-Follower
In case we had any doubt, or if we built our reference buffer circuit with only FB#1 we could use our
real world transient stability test using the circuit in Fig. 10.15.
VFB 4.999V
FB#1
RF100k
D C =0V
Transient=10mVpp
f=100H z, 10ns rise/fall
VEE12
VO 4.9991V
U2REF02
Vin
Gnd
REF02
+
+
Trim
Out
Vout
Riso16.2
+
4.9991V
U1OPA177E
Vin
CL10u
VREF 4.999V
VCC12
-G
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R1100k
ne
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Vtrim 1.2298V
Fig. 10.15: FB#1 Transient Stability Test Circuit: Emitter-Follower
100.00m
is
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on
T
EN
The transient stability test results (Fig. 10.16) coincide with both the 1/ on Aol Pot and loop gain plot
in confirming we have an unstable circuit by using only FB#1 in our reference buffer configuration.
0.00
7.00
6.57
STABLE
As
6.14
Pu
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Vin
5.71
VO
5.29
4.86
4.43
4.00
0.00
250.00u
500.00u
750.00u
Time (s)
Fig. 10.16: FB#1 Transient Stability Test: Emitter-Follower
1.00m
T
160
140
Aol
120
100
FB#1 1/ Gain (dB)
80
60
1/ F B#2
B#1
fcl
40
20
fza
fpc
1/ STABLE
0
fzx
-20
Vout/Vin
10m
100m
1
10
100
1k
Adding FB#2 for Stability:
Set FB#2 High -f 1/ = +10db greater than FB#1 Low
Set fza in FB#2 1/ = 0.1fzx in FB#1 1/
10k
100k
1M
10M
-G
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Frequency (Hz)
ne
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-40
-f 1/ : best phase margin within loop gain bandwidth
Fig. 10.17: FB#2 Graphical Analysis: Emitter-Follower
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Now we must figure out how to synthesize a solution to make our reference buffer with capacitive load
stable. At this point we know the Aol curve and the FB#1 1/ (Fig. 10.17). If we add FB#2 1/ we can
see a net 1/ which will be a stable circuit from our stability rule-of thumb for rate-of-closure at fcl.
Additionally, we will force fpc to be less than a decade from fzx in the 1/ curve to ensure phase
margin will be better than 45° for frequencies less than fcl. This is done by setting the high frequency
portion of FB#2 1/ only +10 dB greater than the low frequency 1/ of FB#1. fza is set to be at least
one decade less than fpc to guarantee that as parameters shift in the real world, we can avoid the BIG
NOT. By inspection, the net 1/ curve is formed from FB#1 1/ and FB#2 1/ by choosing the path
with lowest 1/.
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Remember, in dual feedback paths the largest voltage fed back from the op amp output to the negative
input will dominate the feedback. The largest feedback voltage implies the largest or the smallest
1/ . Fig. 10.18 reminds us of this key trick.
As
As a final point we see that the Vout/Vin transfer function is predicted to follow FB#1 until FB#2
dominates, at which point Vout/Vin will roll off at –20 dB/decade until FB#2 intersects with the Aol
curve where it would then follow the Aol curve on down.
Fig. 10.18: Dual Feedback, Superposition & 1/: Emitter-Follower
Fig. 10.18 reminds us when using dual feedback paths around op amp circuits the largest path will
dominate. An easy analogy to remember is that if two people are talking to you in one ear, which
person do you hear the easiest? The one talking the loudest! So the op amp will listen to the feedback
path with the largest or smallest 1/. The net 1/ plot the op amp sees is the lower one at any
frequency of FB#1 1/ or FB#2 1/.
FB#1
CF82n
VFB
U1OPA177E
RF100k
VO
+ +
VCV1
Riso26.7
Ro60
x1
+
-
-
Pu
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FB#2 1/ Calculation:
Pole: At Origin
Zero:
As
Vout
CL
is
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d
+
EN
VOA
on
-
-G
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As shown in Fig. 10.19 there are some key assumptions we will make that apply to almost all Riso
w/Dual Feedback circuits. First we will assume that CL > 10 * CF, which means that CL will become
a short at high frequencies long before CF does. We will, therefore, short CL to eliminate FB#1 so as
to analyze FB#2 independently. In addition, we will assume that RF > 10 * Riso, which implies that
that RF has little to no effect as a load across Riso. From Fig. 10.19, and the detailed derivations in
Fig. 10.20, we see FB#2 will have a pole at the origin with a zero, fza, at 19.41 Hz caused by RF and
CF. The high frequency 1/ portion of FB#2 is a ratio of Ro + Riso to Riso since CF and CL are both a
short at high frequency. The derivation of FB#2 1/ is shown in Fig. 10.20 with the results computed
in Fig. 10.19. The high frequency 1/ for FB#2 is set to be 3.25 dB or 10.24 dB, with a pole at the
origin and a zero at 19.41Hz.
Zero:
1
2 RF CF
1
2 100k 82nF
Zero: fza = 19.41Hz
FB#2 Analysis:
1/ pole at the origin
1/ zero set by RF and CF
High - f 1/ set by RO and
Riso
CL = zero since we are using superposition
and only analyzing FB#2
Assume:
CL > 10 CF
RF > 10 Riso
VFB
=
VOA
VOA
1/ =
VFB
High Frequency :
CL = short
By Inspection:
Ro+Riso
for High-f 1/ 1/ =
Riso
60+26.7
1/ =
for High-f 1/ 26.7
1/ = 3.25 or 10.24dB for High-f 1/
Fig. 10.19: FB#2 Analysis: Emitter-Follower
FB#2 Derivation:
FB#2 Calculation:
VOA RF
VOA
VFB
VOA
RF
=
RF +
=
1
SCF
High Frequency :
CL = short
By Inspection:
Riso
=
: High-f
Ro+Riso
SCF RF
SCF RF+1
S
1
VFB
=
VOA
1/ =
S+CF RF
Ro+Riso
: 1/ High-f
Riso
This Implies:
Zero: At Origin
Pole: fpa =
ne
t
VFB
VFB
VOA
VOA
1/ =
VFB
=
XCF+RF
-G
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s.
VFB =
FB#2 1/ Derivation:
Assume:
CL > 10 CF
RF > 10 Riso
1
2 RF CF
EN
Fig. 10.20: FB#2 1/ Derivation: Emitter-Follower
is
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on
The derivation for FB#2 is shown on the left in Fig. 10.20. Since 1/ is the reciprocal of , FB#1 1/
calculation is easily derived as shown on the right. We see that the pole, fpa, in the derivation
becomes the zero, fza, in the 1/ derivation.
LT1T
RF100k
CT1T
Aol=VOA
FB#1: 1/Beta1=VOA / VFB
Pu
bl
Loop Gain = VFB
Vtrim
As
REF02
Trim
Out
CF82n
Zo ExternalModel
VOA 4.9991V
VCV1
U1OPA177E
FB#2
+ VG1
VEE12
1.2298V
U2REF02
Vin
Gnd
VFB 4.999V
+ +
VREF
Vout
Ro60
+ x1 +
-
Rsi o26.7
VO 4.9991V
4.9991V
CL10G
4.999V
VCC12
FB#2 Analysis:
Set CL = 1GF
AC Short for any frequency of interest
Fig. 10.21: FB#2 Analysis Ac Circuit: Emitter-Follower
To check our first order analysis of FB#2 we can use the TINA-TI circuit shown in Fig. 10.21. For
ease of analysis we set CL to 10 GF so it will be a short for any frequencies of interest but will still
allow a proper dc operating point to be found by SPICE before the ac Analysis is performed.
The results of our TINA-TI simulation are shown in Fig. 10.22. The FB#2 1/ plot is as predicted by
our first-order analysis with fza = 19.41 Hz and a high frequency 1/ of 10.235 dB. We also plot the
OPA177 Aol curve to see how FB#2 will intersect with it at high frequency.
a
T
160
b
140
Aol
120
FB#2 1/ :
A:(19.41; 13.2419)
B:(709.0051; 10.235)
100
FB#2 1/ 60
ne
t
Gain (dB)
80
20
-G
en
iu
s.
40
fz a
0
EN
-20
-40
10m
100m
1
10
100
1k
10k
100k
1M
10M
on
Frequency (Hz)
is
he
d
Fig. 10.22: FB#2 1/ Plot: Emitter-Follower
Pu
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We will analyze if the predicted superposition results of FB#1 and FB#2 will produce the desired net
1/ by using the TINA-TI circuit (Fig.10.23). This same circuit will allow us to plot Aol, net 1/ and
loop gain.
Aol = VOA
VFB
LT1T
As
FB #1: 1/ Beta1= VOA / VF B
4. 999V
RF100k
CT1T
Loop Gain = V FB
+ VG1
CF82n
VEE12
Vtrim
1. 2298V
Zo E xt ernal Model
VOA 4. 9991V
U2REF02
U1OPA177E
Vin
Gnd
REF02
Trim
Out
VCV1
+ x1 +
++
VREF
-
Ro60
VO
4. 9991V
Riso26.7
Vout
CL10u
4. 999V
VCC12
Fig. 10.23: Final Loop Gain Analysis Circuit: Emitter-Follower
4. 9991V
In Fig. 10.24 we see our analysis results confirm our predicted net 1/ plot. At fcl, where loop gain
goes to zero, we see our expected 20 dB/decade rate-of-closure.
T
160
140
Aol
120
100
80
Gain (dB)
STABLE
60
fcl
40
1/ ne
t
20
-G
en
iu
s.
0
-20
-40
10m
100m
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
EN
Fig. 10.24: Final Net 1/: Emitter-Follower
T
on
The loop gain phase plot for our final circuit, which uses FB#1 and FB#2 (Fig. 10.25) shows it never
dips to less than 58.77° (as seen at 199.57 kHz) and at fcl, 199.57 kHz, the phase margin is 76.59°.
160
is
he
d
120
80
60
Loop Gain : A:(333.8948; 60.4135) B:(199.5744k; -54.5547m)
Loop Gain Phase : A:(333.8948; 58.7725) B:(199.5744k; 76.5915)
40
20
0
-20
-40
100m
1
10
100
1k
10k
fcl
1M
10M
1M
10M
a
135
Phase [deg]
100k
Frequency(Hz)
As
10m
Pu
bl
Gain (dB)
100
180
b
Loop Gain
140
STABLE
90
45
0
10m
100m
1
10
100
1k
10k
100k
Frequency(Hz)
Fig. 10.25: Final Loop Gain Analysis: Emitter-Follower
We do our final check on our stabilized circuit by running a transient stability test using the TINA-TI
circuit in Fig. 10.26.
RF100k
CF82n
D C =0V
Tran sie nt=10mVpp
f=1 00H z, 1 0ns ris e/fall
VO
U2REF02
Vin
Gnd
VEE12
1.22 98V
REF02
-
Vin
Trim
Out
+
VREF
++
4.99 91V
Vout
Riso26.7
4.99 91V
U1OPA177E
CL10u
4.99 9V
-G
en
iu
s.
VCC12
ne
t
Vtrim
Fig. 10.26: Final Transient Stability Test Circuit: Emitter-Follower
T
EN
The results of our transient stability test on our final circuit (see Fig. 10.27) agree with all of our other
predictions, resulting in a good, stable circuit we can put into production with confidence that we will
not have any failures or real world operation anomalies.
on
5.01
is
he
d
VO
4.99
10.00m
As
-10.00m
5.01
Pu
bl
Vin
Vout
4.99
0.00
2.50m
5.00m
7.50m
Time (s)
Fig. 10.27: Final Transient Stability Test: Emitter-Follower
10.00m
RF100k
CF82n
VEE12
Vtrim 1.2298V
VO 4.9991V
D C =0V
AC=1Vpk
U2REF02
Vin
Gnd
REF02
-
Vin
Trim
Out
+
Vout
Riso26.7
++
4.9991V
U1OPA177E
CL10u
VREF 4.999V
VCC12
ne
t
Fig. 10.28: Final Vout/Vin Transfer Function Circuit: Emitter-Follower
a
0
b
EN
T
-G
en
iu
s.
The TINA-TI circuit in Fig. 10.28 will allow us to confirm if our prediction of Vout/Vin is correct. We
see (Fig. 10.29) that the results of our Vout/Vin test match our predicted first-order results with a
single pole roll off at 625.53 Hz and a second pole appearing at about 200 kHz where FB#2 intersects
the OPA177 Aol curve.
-20
-80
-100
Gain:
Vout/Vin: A:(9.93; 58.82m) B:(615.53; -3)
-120
-140
10m
100m
-45
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
Frequency(Hz)
As
-90
-135
1
Pu
bl
0
Phase [deg]
on
-60
is
he
d
Gain (dB)
-40
-180
10m
100m
1
10
100
Frequency(Hz)
Fig. 10.29: Final Vout/Vin Transfer Function: Emitter-Follower
Fig. 10.30 summarizes an easy to use step-by-step procedure to easily use the Riso w/Dual Feedback
capacitive load stability technique on bipolar emitter-follower output op amps.
FB#2 1/ Formulae:
FB#1 1/ Formulae:
1
Zero: fzx =
2 (Ro+Riso) CL
1/ = 1 (f=0) for Low-f 1/
Assume:
CL > 10 CF
RF > 10 Riso
Pole: At Origin
Zero: fza=
1
2 RF CF
-G
en
iu
s.
ne
t
High Frequency 1/ :
CL = short
By Inspection:
Ro+Riso
for High-f 1/ 1/ =
Riso
Measure Aol of op amp
Measure & Plot Zo of op amp
Determine RO
Create Zo external model
Compute FB#1 Low-f 1/: equals 1 for unity gain voltage buffer
Set FB#2 High-f 1/ = +10 dB higher than FB#1 Low-f 1/ (For best Vout/Vin transient
response and least amount of phase shift within loop-gain bandwidth)
7) Choose Riso from FB#2 High-f 1/ and RO
8) Compute FB#1 1/ fzx from CL, Riso, RO
9) Set FB#2 1/ fza = 1/10 fzx
10) Choose RF and CF with practical values to yield fza
11) Run simulation with final values for Aol, 1/, loop gain, Vout/Vin, transient analysis to
confirm design
12) Check for loop-gain Phase shift NOT to dip more than 135° (>45° phase margin)
13) For low noise applications: check for flat Vout/Vin response to avoid gain peaking
leading to noise peaking in Vout/Vin
As
Pu
bl
is
he
d
on
EN
1)
2)
3)
4)
5)
6)
Fig. 10.30: Riso w/Dual Feedback Compensation Procedure: Emitter-Follower
WARNING: This can be
hazardous to your circuit!
100
Aol
80
A (d B)
FB#1
60
FB#2
40
1/Beta
fcl
1/Beta
20
0
1
10
100
1k
10k
100k
1M
10M
Frequency(Hz)
Dual Feedback and the BIG NOT :
1/_ Slope changes from +20db/decade to -20dB/decade
ne
t
Im plies a “com plex conjugate pole
” in the 1/ _ Plot.
Im plies a “com plex conjugate zero ” in the Aol _ (Loop Gain Plot).
+/ -90 ° phase shift at frequency of com plex zero/com plex pole.
Phase slope from +/ -90 °/decade slope to +/ -180 ° in narrow band near frequency
of com plex zero/com plex pole depending upon dam ping fact
or.
Com plex zero/com plex pole can cause
severe gain peaking in closed loop response.
-G
en
iu
s.
Fig. 10.31: Dual Feedback and the BIG NOT
Pu
bl
is
he
d
on
EN
When using dual feedback paths around an op amp there is one extremely important case to avoid – the
“BIG NOT”. As demonstrated in Fig. 10.31, there are op amp circuits that can result in feedback paths
that create the BIG NOT, which is seen in the net 1/ plot that contains a net 1/ slope which changes
from +20 dB/decade to –20 dB/decade abruptly. This rapid change implies a complex conjugate pole
in the 1/ plot which is, therefore, a complex conjugate zero in the loop-gain plot. Complex zeros and
poles create a ±90º phase shift at the frequency of the complex zero/complex pole. Also, the phase
slope around a complex zero/complex pole can range from ±90º to ±180º in a narrow frequency band
around the frequency location of the occurrence. Complex zero/complex pole occurrences can cause
severe gain peaking in the closed-loop op amp response. This can be very undesirable, especially in
power op amp circuits.
T
160
140
100
As
Aol
120
FB#1 1/ Gai n (d B )
80
60
1/ FB#2
FB#1
40
fcl
20
fpc
???
STABLE
???
fza
0
1/ The BIG NOT
-20
-40
10m
100m
1
10
100
1k
10k
100k
Frequency (Hz)
Create the BIG NOT:
Change CF to 220pF which moves
fza to 7.23kHz
Fig. 10.32: Create the BIG NOT Graphically
1M
10M
Let’s return to our plot of FB#1 and FB#2 on the OPA177 Aol curve (Fig. 10.17, again). We can easily
create the BIG NOT by simply changing the location of fza (Fig. 10.32).. At fcl our rate-of-closure
rule-of-thumb would indicate that this circuit is stable -- but is it?
In Fig. 10.33 we modify our TINA-TI circuit used to analyze FB#1 and FB#2 together to create the
BIG NOT, as described in Fig. 10.32. CF is changed from 82 nF to 220 pF to move fza to the desired
BIG NOT creation location.
VFB
LT1T
4. 999V
RF100k
Aol = VOA
CT1T
FB #1: 1/ Beta1= VOA / VF B
Loop Gain = V FB
+ VG1
CF220p
VEE12
Zo E xt ernal Model
VOA
U2REF02
4. 9991V
-
REF02
+
++
Trim
Out
VREF
Riso26.7
Ro60
VCV1
x1
+
4. 9991V
Vout
-G
en
iu
s.
U1OPA177E
Vin
Gnd
VO
1. 2298V
ne
t
Vtrim
-
4. 999V
VCC12
4. 9991V
CL10u
EN
Fig. 10.33: Loop Gain Analysis Circuit: BIG NOT
T
on
160
140
is
he
d
Aol
120
100
Pu
bl
Gain (dB)
80
60
As
40
20
fcl
???
STABLE
???
BIG NOT
BIG NOT 1/ 0
-20
-40
10m
100m
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
BIG NOT1/ : At fcl rate -of -closure rule
-of -thumb says circuit is stable but is it?
Fig. 10.34: 1/: BIG NOT
The 1/ plot of the BIG NOT (Fig. 10.34) shows a 20 dB/decade rate of closure, but there is quick
turnaround from +20 dB/decade to –20 dB/decade slope in the 1/ plot; peaking is not a good thing and
we should question if this circuit will be stable.
a
T 160
140
L o o p Ga n
i
120
100
Gain (dB)
80
60
40
Loop Gain : A:(199.5744k; -61.1988m) B:(1.0344k; 38.4074)
Loop Phase : A:(199.5744k; 78.662) B:(1.0344k; 12.6382)
20
0
-2 0
-4 0
100m
10m
1
10
100
1k
10k
100k
10k
100k
Fre q u e n cy(Hz)
1M
10M
b
180
???
STABLE
???
135
Phase [deg]
fcl
90
ne
t
45
0
10m
100m
1
10
100
1k
Fre q u e n cy(Hz)
10M
Loop Gain phase shift >135 degrees (<45 degrees from 180 degree phase
fcl which violates the loop gain phase shift rule
-of -thumb. But is it stable?
-G
en
iu
s.
BIG NOT Loop Gain:
shift) for frequencies <
1M
Fig. 10.35: Loop Gain Analysis: BIG NOT
EN
A loop gain plot of our circuit (Fig. 10.35) shows phase shift to be 167° at 1.034 kHz, only 13° away
from a 180° phase shift. Also note how loop gain is sharply spiking downwards toward zero loop gain
in this same region. Again, at fcl there is plenty of phase margin, but are we stable?
is
he
d
on
Assume we are inexperienced in the wisdom of stability analysis (which we are not), and built this
circuit; what can we expect a real-world transient stability test to look like? The TINA-TI circuit in
Fig. 10.36 allows us to see the result of putting this circuit into production and then out into the world.
Pu
bl
DC=0V
VFB
4. 999V
RF100k
Transient=10m V pp
CF220p
f =100Hz, 10ns rise/f all
Vtrim
1. 2298V
As
U2REF02
Vin
Gnd
VEE12
REF02
+
VREF
++
+
U1OPA177E
VO
4. 9991V
4. 9991V
VCV1
-
Vin
Trim
Out
Zo E x t ernal Model
VOA
-
x1
Ro60
Riso26.7
Vout
+
-
CL10u
4. 999V
VCC12
Fig. 10.36: Transient Stability Test Circuit: BIG NOT
4. 9991V
Don’t tell your boss we put this circuit into production or, worse yet, the customer who received the
equipment you shipped with this circuit which causes weird and intermittent problems when poweredup sometimes, or when something else abruptly loads this reference buffer. Time to update our
resumés? Despite the fact that this is not an oscillator, the excessive ringing and long settling time from
our transient stability test (Fig. 10.37) indicate an extremely marginally-stable circuit.
T
5.38
VO
4.34
6.10
3.04
100.00m
-G
en
iu
s.
STABLE
ne
t
VOA
Vin
EN
-100.00m
5.17
4.76
0.00
is
he
d
2.50m
on
Vout
5.00m
7.50m
10.00m
Time (s)
BIG NOT Transient Stability Test:
Excessive ringing and marginal stability
are apparent. Real world
implementation and use may cause even more severe oscillations.
We do not want this in production!
Pu
bl
Fig. 10.37: Transient Stability Test: BIG NOT
As
Depending upon where the BIG NOT occurs, the duration and amplitude of the ringing can easily be
worse than this example. From a board and system level view we call this circuit unstable, especially
since our analysis does not account for real world parasitics in our PCB layout, component and op amp
parameter and temperature variances. Fortunately, we only put this into virtual production and can
apply our Riso w/Dual Feedback technique properly to the circuit, which will go into real production.
CMOS RRO: Riso w/Dual Feedback
We choose to analyze the Riso w/Dual Feedback technique with the OPA734 (Fig. 10.38). It is a zerodrift, low input offset voltage op amp powered from +2.7 V to +12 V. Low drift of 0.05 V/°C, plus a
super low initial input offset voltage of 1 V, make it an ideal single supply reference buffer. It is not
rail-to-rail on the input so we need to observe the input voltage range of (V–) –0.1 V to (V+) –1.5 V.
OPA734
0.05uV/C Max, Single-Supply, CMOS Operational Amplifier,
Zero-Drift Series
-G
en
iu
s.
ne
t
Specification
+2.7V to +12V
600uA typical
1uV max
0.05uV/C max
+/-100pA typical
0.8uVp-p (0.1Hz to 10Hz)
135nV/rt-Hz
(V-)-0.1V to (V+)-1.5V
1.6MHz
130dB (RL=10k)
125 ohms @ f=1MHz, Io=0A
1.5V/us
20mV max (RL=10k to Vs/2)
SOT23-5, MSOP-8, SO-8
EN
on
Parameter
Supply Voltage (Vs)
Quiescent Current
Offset Voltage
Offset Drift
Input Bias Current
Input Voltage Noise
Input Voltage Noise Density
Input Voltage Range
Gain-Bandwidth Product
Open Loop Gain
Open Loop Output Resistance
Slew Rate
Voltage Output Swing from Rail
Package
As
Pu
bl
is
he
d
Fig. 10.38: CMOS RRO Op Amp Specifications
MOSFET Drain
Outputs
Fig. 10.39: Typical CMOS RRO Op Amp Topology
In a typical CMOS RRO equivalent schematic (Fig. 10.39) the output of the op amp is connected to the
drains of the MOSFETs. This type of drain output op amp will exhibit a Zo which is both resistive and
capacitive requiring some slightly different techniques for analysis.
From the outside (Fig. 10.40) our CMOS RRO reference buffer looks the same as the bipolar emitterfollower example. This application uses a single 5 V supply and we will be buffering a 2.5 V reference
which is under our input voltage range specification (input voltage range: 5 V – 1.5 V = 3.5 V). An
accurate reference voltage will be at Vout due to FB#1. FB#2 will provide the required feedback at
high frequency for good stability. Riso will provide the needed isolation between the two feedbacks.
FB#1
RF100k
CF150n
-
Riso13
+ +
R EF 5025
Vout
2.5V
-G
en
iu
s.
U1OPA734
ne
t
FB#2
EN
CL47u
Vref 2.5
EN
Vs 5
is
he
d
on
Dual Feedback:
FB#1 through RF forces accurate
Vout across CL
FB#2 through CF dominates at high frequency for stability
Riso provides isolation between FB#1 and FB#2
Fig. 10.40: Riso w/Dual Feedback: CMOS RRO
As
Pu
bl
With a single supply here, a few new circuit (Fig. 10.41) tricks are used to get the unloaded Aol curve.
Fig. 10.41: Aol Test Schematic: CMOS RRO
First we need to ensure the OPA734 output, after a dc operating point analysis, is in the linear region
of operation. Typically, saturated outputs of op amps do not give correct ac performance since they are
not in the linear region, and this is also true for most op amp macromodels. At dc, LT is a short and CT
is an open. The non-inverting input of the OPA734 is tied to Vs/2 (2.5 V). Thus, the output will also be
at 2.5 V. With RL connected as shown, there is no dc load on the output of the op amp. RL together
with LT provides an ac path for the low-pass filter function, which allows a dc short circuit and ac
open circuit in the feedback path. Remember, TINA-TI must perform a closed-loop dc analysis to find
the operating point of the circuit before it can perform an ac analysis. RL, together with CT, provides
an ac path for the high-pass filter function which allows us dc open circuit and ac short circuit into the
input. LT and CT are chosen as large values to ensure their respective operations of shorts and opens at
any ac frequency of interest.
The OPA734 Aol curve (Fig. 10.42) from the simulation shows the unity-gain bandwidth as 1.77 MHz.
a
140
ne
t
T
OPA734 Aol
120
Gain :
A:(1.77M; 4.1m)
Phase :
A:(1.77M; 69.05)
-G
en
iu
s.
100
Gain (dB)
80
60
40
20
0
-20
1
10
100
1k
10k
100k
1M
10M
100k
1M
10M
EN
Frequency(Hz)
on
45
is
he
d
Phase [deg]
90
0
10
100
1k
10k
Frequency(Hz)
Pu
bl
1
Fig. 10.42: Aol Test Results: CMOS RRO
As
LT1T
Zo = Vout
RL100k
No Load – Zo Test Circuit:
RL tied to Vs/2 with
Vout = Vs/2 yield No DC
RL provides AC path for low pass filter with LT
Iout
U1OPA734
+ +
Vout
EN
Vs/22.5
Vs5
2.5V
Change Y -A xis to Logarithm ic s c ale to rem ove db s cale fac tor
Y -A xis (dB ) = 20 Log (V out / IG1)
IG1
D C=0A
AC =1Apk
Y -A xis (Logarithm ic) = V out / IG1 = Zo
B ut IG1 = 1A pk
Y -A xis (Logarithm ic) = V out = Zo
Fig. 10.43: TINA-TI Circuit For Modified Aol Effects By Zo, CCO, RCO, CL
We must now measure Zo (small signal ac open-loop output impedance) as shown in Fig. 10.43.
This TINA-TI circuit will test the unloaded Zo of the OPA734. Remember that we chose to put the
output at 2.5 V to ensure linear operation. RL, together with LT, provides an ac path for the low-pass
filter function which allows us dc short circuit and ac open circuit in the feedback path. No current is
flowing into or out of the OPA734 since RL is tied between Vout (2.5 V) and Vs/2 (2.5 V). Zo is now
easily measured by our application of a 1 Apk ac current generator which we will sweep over the ac
frequency range of 10 MHz to 1 MHz.
T
100k
10k
Zo Magnitude :
A:(1.004701M; 129.606967)
Zo Phase :
B:(92.029668; -44.945329)
1k
100
10
1
100
1k
EN
-45
is
he
d
on
Zo Phase [deg]
100k
-G
en
iu
s.
b
0
10k
Frequency(Hz)
fz
ne
t
Zo Magnitude (ohms)
OPA734 Zo
Fig. 10.44: Zo, Open-Loop Output Impedance: CMOS RRO
Pu
bl
The OPA734 Zo (Fig. 10.44) is characteristic of CMOS RRO output stages with Ro dominating at high
frequency, and the capacitive effect represented by Co dominating at frequencies less than 92 Hz.
As
CO
+
-IN
-
+IN
+
Aol
VOUT
+
-
fz =
RO
GM2
2*
RO
129 CO
13.4 μF
-
No Load
fz
92Hz
1
*RO*CO
GMO
Fig. 10.45: Zo Model: CMOS RRO
In Fig. 10.45 we build our Zo model of the OPA734 based on simulation test results from the previous
slide. RO was measured directly to be 129 and fz was measured directly to be 92 Hz. From fz and
RO we can easily compute CO to be 13.4 F and our Zo model is complete as shown.
RF100k
CF150n
VFB
VOA
Zo
-
U1OPA734
Riso13
Vout
External
+ +
REF5025
Model
EN
Vref2.5
CL47u
VO
Vs5
ne
t
Zo External Model:
U1 is complete SPICE macromodel of OPA734 with data sheet Aol curve and Zo
Zo is moved outside of the op amp
macromodel to form a new macromodel
Allows for simulation of 1/ with effects of Zo and external loads
-G
en
iu
s.
Fig. 10.46: Zo External Model: CMOS RRO
For our 1/ analysis to include the effects of Zo interacting with Riso, CL, CF and RF, we need to
move Zo outside of our op amp macromodel so we can probe the necessary nodes in our circuit
concept (see Fig. 10.46). U1 will provide the data sheet Aol curve and be buffered from any effects of
Riso, CL, CF and RF.
F B#1
CF150n
2.5V
VOA
GM2
-
U1OPA734
REF 5025
CO13.4u
-
is
he
d
+ +
x1/RO
CLP12.3u
Vout
1
2.5V
GMO
CL47u
RL1M
+
x1/(Riso+RL)
f LP = 0.1Hz
f LP =
Riso 13
-
RO129
x7.75E-3
Pu
bl
Vs 5
Z o Externa l M od el
RLP129k
EN
+
Vref2.5
F B#2
2.5007V
on
VFB
EN
RF100k
VO
2.5V
x1e-6
2 RLPCLP
Zo and external loads
As
Zo External Model:
GM2 ideally isolates U1 so U1 only provides data sheet
Aol with no effects of
Set GM2 = x1/RO to maintain data sheet
Aol gain characteristic
RLP, CLP, GMO provide a path for DC Analysis
Set RLP = 1000 * RO to avoid loading RO to any level of concern
Set CLP to yield
fLP = 0.1* fLOW , where fLOW is the lowest frequency of interest
Set GMO = 1/(Riso+RL) to maintain proper data sheet
Aol DC gain
Fig. 10.47: Zo External Model Details: CMOS RRO
The Zo External Model (Fig. 10.47) allows for us to measure the effects of Zo interacting with Riso,
CL, RF and CF on 1/. RO and CO are parameters we measured in an earlier slide. GM2 isolates U1,
the OPA734 op amp macromodel, from our Zo External Model. GM2 is set to 1/RO to preserve the
proper Aol gain to match the original OPA734 op amp macromodel and data sheet Aol. TINA-TI must
perform a dc analysis before it can perform an ac analysis. Therefore, we need to make sure our
expanded op amp model will have the correct dc operating point without saturating U1. To do this we
add a low-frequency path around CO to VO. GMO will be controlled by the voltage across RO which
matches VOA. GMO is set to 1/RL to preserve the overall gain at dc to match the original OPA734
Aol. A low-pass filter is formed by RLP and CLP and set to be 0.1 * fLOW where fLOW is our lowest
frequency of interest. RLP is set to 1000 * RO to prevent any loading on RO, or interaction, to cause
the Zo transfer function to be wrong.
First we will analyze FB#1 (see Fig. 10.48) and notice that CF is treated as an open since we are only
going to analyze FB#1. Later we will analyze FB#2 and then, using superposition, combine the two
feedback paths for the net 1/. The results of our analysis are shown Figure 10.48 with the derivations
and details in Fig. 10.49. We see a zero in the FB#1 1/ plot at fzx = 107.49 Hz. The low frequency 1/
value is 4.5 or 13 dB and is determined by a capacitor divider between CO and CL. If this circuit were
changed to have gain, the low frequency 1/ value would be greater than one.
FB#1 1/ :
F B#1
RF100k
1
CO CL
)(Riso+RO)
2 (
CL+CO
1
fzx =
13.4u 47u
) (13+129)
2 (
47u+13.4u
fzx =
CF
VFB
VOA
GM2
-
U1OPA734
Riso 13
Vout
EN
+
Vref2.5
x1/RO
Vs 5
RO129
VO
fzx = 107.49Hz
CL47u
1 CL+CO
for Low-f
= CO
x7.75E-3
FB#1 Analysis:
1/ zero due to series combination of CO and CL interacting with RO
Low frequency 1/
set by capacitive divider between CO and CL
CF is treated as an open since we are using superposition an ana
ne
t
REF 5025
CO13.4u
-
+ +
1 47u+13.4u
=
for Low-f
13.4u
-G
en
iu
s.
+ Riso
1
= 4.5 or 13dB for for Low-f
lyzing FB#1 only
Fig. 10.48: FB#1 Analysis: CMOS RRO
FB#1 Derivation:
EN
1 Vout
= VOA
VOA
XCL
RO+XCO+R iso+XCL
is
he
d
=
FB#1 1/ Derivation:
VFB
on
=
is series com bination of C O and C L
As
CO CL
Note:
Pu
bl
After Algebraic M anipulation:
1
(Riso+RO)
CL
=
1
S+
CO CL
)(Riso+RO)
(
CL+CO
CL+CO
Pole: fpx =
1
CO CL
)(Riso+RO)
2 (
CL+CO
CO
for f = 0 (Low-f )
CL+CO
CO and CL form a Capacitive Divider
=
1 RO+XCO+R iso+XCL
=
XCL
After Algebraic Manipulation:
1
S+
CO CL
)(Riso+RO)
(
CL+CO
1
=
1
CL (Riso+RO)
CO CL
Note:
CL+CO
Zero: fzx =
is series combination of C O and C L
1
CO CL
)(Riso+RO)
2 (
CL+CO
1 CL+CO
=
for f = 0 (Low-f 1/ )
CO
CO and CL form a Capacitive Divider
Fig. 10.49: FB#1 1/ Derivation: CMOS RRO
The derivation for FB#1 is shown on the left in Fig. 10.49. Since 1/ is the reciprocal of , FB#1 1/
calculation is easily derived as shown on the right in the same Fig. We can see that the pole, fpx, in the
derivation becomes the zero, fzx, in the 1/ derivation.
We will use the circuit in Fig. 10.50 to perform ac analysis, using TINA-TI, to find 1/ for FB#1, Aol
for the OPA734, and loop gain for this circuit using only FB#1.
VFB
FB#1
RF100k
2.5V
Aol=VOA
1/ =VOA/VFB
L11T
Loop Gain =VFB
CT1T
VOA
+ VG1
2.5V
U1OPA734
AC=1Vpk
+
+
Zo Ex ternal M odel
CO13.4u
GM2
-
DC=0V
+
Vref2.5
REF5025
2.5V
RL1M
+
CLP12.3u
x7.75E-3
x1(/Riso+RL)
f LP = 0.1Hz
VO 2.5V
x1e-6
1
2 RLP CLP
ne
t
f LP =
CL47u
-
RO129
x1R
/O
Vs5
Vout
GMO
RLP129k
EN
Riso13
-G
en
iu
s.
Fig. 10.50: FB#1 Analysis Ac Circuit: CMOS RRO
EN
FB#1 1/ results are plotted on the OPA734 Aol curve (see Fig. 10.51). At fcl, where loop gain goes to
zero, we see that the rate-of-closure is 40 dB/decade:
[(–20 dB/decade from Aol) – (+20 dB/decade from FB#1 1/) = –40 dB/decade rate-of-closure]
which, from our rate-of-closure rule-of-thumb, indicates instability.
a
T
b
is
he
d
140
120
Aol
1/ FB#1:
A:(1.4424; 13.0953)
B:(107.49; 16.0961)
Pu
bl
100
80
fcl
1/ FB#1
60
As
Gain (dB)
on
Our analysis of FB#1 was low frequency 1/ = 13.09 dB with a zero, fzx, at 183.57 Hz, and as can be
seen (Fig. 10.51) our first-order analysis predicted accurately FB#1 1/.
40
fz x
20
STABLE
0
-20
1
10
100
1k
10k
100k
Frequency (Hz)
Fig. 10.51: FB#1 1/ Plot: CMOS RRO
1M
10M
T
a
120
Loop Gain
100
80
Gain :
Gain (dB)
60
VFB A:(6.73k; -14.49m)
Phase :
40
VFB A:(6.73k; 831.33m)
20
fcl
0
-20
-40
1
10
100
1k
10k
100k
1M
10M
Frequency(Hz)
90
STABLE
Phase [deg]
45
-45
10
100
1k
10k
100k
1M
10M
-G
en
iu
s.
1
ne
t
0
Frequency(Hz)
Fig. 10.52: FB#1 Loop Gain Analysis: CMOS RRO
on
EN
In Fig. 10.52 the loop-gain analysis of our circuit using only FB#1 shows that we have close to zero
phase margin at fcl where gain goes to zero. This is definite confirmation that we have an unstable
circuit. The poles and zeros in the loop-gain plot can be predicted, by inspection, from the FB#1 1/
plot on the Aol curve (Fig. 10.51, again).
VFB 2.5V
Pu
bl
is
he
d
RF100k
VO 2.5V
-
Riso13
Vout
2.5V
As
U1OPA734
+ +
EN
CL47u
Vref 2.5
RL1M
Vs 5
R EF 5025
+ Vin
D C =0V
Square Wave = +/-10mVpk
f =100H z
Fig. 10.53: FB#1 Transient Stability Test Circuit: CMOS RRO
In case we had any doubt, or if we built our reference buffer circuit with only FB#1, we could use our
real world transient stability test using the circuit in Fig. 10.53.
The transient stability test results (Fig. 10.54) coincide with both the 1/ on Aol Plot and loop-gain plot
in confirming we have an unstable circuit by using only FB#1 in our reference buffer configuration.
T
2.51
VFB
2.49
2.76
VO
2.24
10.00m
STABLE
Vin
ne
t
-10.00m
2.51
-G
en
iu
s.
Vout
2.49
2.50m
0.00
5.00m
7.50m
10.00m
Time (s)
Fig. 10.54: FB#1 Transient Stability Test: CMOS RRO
140
120
EN
T
on
Aol
100
1/ FB#1
Gain (dB)
is
he
d
80
60
40
fcl
Pu
bl
1/ FB#2
FB#1
fza
20
1/
fpc
fzx
0
As
Vout/Vin
STABLE
-20
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Adding FB#2 for Stability:
Set FB#2 High -f 1/ = +10db greater than FB#1 Low
Set fza in FB#2 1/ = 0.1fzx in FB#1 1/
-f 1/ : best phase margin within loop gain bandwidth
Fig. 10.55: FB#2 Graphical Analysis: CMOS RRO
Now we must figure out how to synthesize a solution to make our reference buffer with capacitive load
stable. At this point we know the Aol curve and the FB#1 1/ (Fig. 10.55). If we add FB#2 1/ (Fig.
10.55) we can see a net 1/ which will be stable from our rule-of thumb for rate-of-closure at fcl.
Moreover, we will force fpc to be less than a decade from fzx in the 1/ curve to ensure phase margin
better than 45° for frequencies less than fcl, by setting the high frequency portion of FB#2 1/ only
+10 dB greater than the low frequency 1/ of FB#1. Fza is set to be at least one decade less than fpc to
guarantee that as parameters shift in the real world we can avoid the BIG NOT. By inspection, the net
1/ curve is formed from FB#1 1/ and FB#2 1/ by choosing the path with lowest 1/.
Remember, in dual-feedback paths the largest voltage fed back from the op amp output to the negative
input will dominate the feedback. The largest feedback voltage implies the largest or the smallest 1/.
As a final point, we see that the Vout/Vin transfer function is predicted to follow FB#1 until FB#2
dominates at which point Vout/Vin will roll off at –20 dB/decade until FB#2 intersects with the Aol
curve where it would then follow the Aol curve on down.
FB#2
CO
-
x1R
/O
EN
VFB
RF100k
Riso13
+
U1OPA734
+ +
CF150n
GM2
RO129
VO
x7.75E-3
CL
FB#2 1/ Calculation:
Pole: At Origin
1
2 RF CF
1
Zero:
2 100k 150n
Zero: fza = 10.6Hz
on
EN
Zero:
VFB
VOA
VOA
1/ =
VFB
=
-G
en
iu
s.
FB#2 Analysis:
1/ pole at the origin
1/ zero set by RF and CF
High - f 1/ set by RO and
Riso
CL = zero since we are using superposition
and only analyzing FB#2
Assume:
CL & CO > 10 CF
RF > 10 Riso
ne
t
VOA
High Frequency :
CO & CL = short
By Inspection:
RO+Riso
1/ =
for High-f 1/ Riso
129+13
1/ =
for High-f 1/ 13
1/ = 10.92 or 20.76dB for High-f 1/
is
he
d
Fig. 10.56: FB#2 Analysis: CMOS RRO
As
Pu
bl
There are some key assumptions (see Fig. 10.56) we will make that apply to almost all Riso w/Dual
Feedback circuits. First we will assume that CL > 10 * CF, which means that CL will become a short
at high frequencies long before CF does. We will, therefore, short CL to eliminate FB#1 so as to
analyze FB#2 independently. Furthermore, we will assume that RF > 10 * Riso which implies that that
RF has little-to-no effect as a load across Riso. From Fig. 10.56 and the detailed derivations in Fig.
10.57, we see FB#2 will have a pole at the origin with a zero, fza, at 19.41 Hz caused by RF and CF.
The high frequency 1/ portion of FB#2 is a ratio of Ro+Riso to Riso since CF and CL are both a short
at high frequency. The derivation of FB#2 1/ is shown in the next figures. The high frequency 1/ for
FB#2 is set to be 10.92 or 20.76 dB with a pole at the origin and a zero at 10.6 Hz.
The derivation for FB#2 is shown on the left in Fig. 10.57. Since 1/ is the reciprocal of , FB#1 1/
calculation is easily derived as shown on the right. We see that the pole, fpa, in the derivation
becomes the zero, fza, in the 1/ derivation.
FB#2 Derivation:
FB#2 1/ Derivation:
Assume:
CL & CO > 10 CF
RF > 10 Riso
FB#2 Calculation:
VOARF
VFB
=
VOA
XCF+RF
VFB
VOA
VOA
1/ =
VFB
=
RF
RF +
1
SCF
VOARF
XCF+RF
1
SCF
RF
RF +
VOA SCF RF+1
=
SCF RF
VFB
-G
en
iu
s.
S
1
S+CF RF
VOA
=
VFB
RO+Riso
: 1/ High-f
1/ =
Riso
Zero:fza =
on
1
2 RF CF
1
S+CF RF
S
This Implies:
Pole: At Origin
EN
This Implies:
Zero: At Origin
Pole: fpa =
VOA
=
VFB
High Frequency :
CO & CL = short
By Inspection:
= Riso : High-f
RO+Riso
SCF RF
VFB
=
VOA SCF RF+1
VFB
=
VOA
VFB =
ne
t
VFB =
FB#2 1/ Calculation:
1
2 RF CF
is
he
d
Fig. 10.57: FB#2 Analysis: CMOS RRO
2.5V
RF100k
Ao l= VO A
As
VFB
Pu
bl
To check our first-order analysis of FB#2 we can use the TINA-TI circuit of Fig. 10.58. For ease of
analysis we set CL to 10 GF so it will be a short for any frequencies of interest, but will still allow a
proper dc operating point to be found by SPICE before the ac analysis is performed.
C1150n
L11T
CT1T
+ VG1
D C= 0V
AC =1 Vpk
VOA
2.5V
-
G M2
U1OPA734
+ +
Zo Ex ternal Model
CO1G
-
R EF 5025
Vs5
x1R
/O
x1(/Riso+RL)
1
f LP =
2.5V
RL1M
+
CLP12.3u
f LP = 0 .1 Hz
Vout
CL1G
-
RO129
x7.75 E-3
Riso13
G MO
RLP129k
EN
+
Vref2.5
1/ = VO A/VF B
F B#2
x1e -6
2 R LP C LP
FB#2 Analysis:
Set CO = 1GF and CL = 1GF
AC Short for any frequency of interest
Allows for GM2 and GMO to remain unchanged for this analysis
Fig. 10.58: FB#2 Analysis Ac Circuit: CMOS RRO
VO
2.5V
The results of our TINA-TI simulation(Fig. 10.59) show the FB#2 1/ plot is as predicted by our firstorder analysis with fza = 10.6 Hz and a high frequency 1/ of 23.78 dB. We also plot the OP734 Aol
curve to see how FB#2 will intersect with it at high frequency.
a
T
b
140
120
Aol
FB#2 1/ :
A:(10.6; 23.7853)
100
B:(227.0182; 20.7804)
Gain (dB)
80
60
ne
t
40
fz a
-G
en
iu
s.
20
FB#2 1/ 0
-20
10
1
100
1k
10k
100k
1M
10M
EN
Frequency (Hz)
on
Fig. 10.59: FB#2 1/ Plot: CMOS RRO
VFB 2.5V
RF100k
CT1T
+ VG1
VOA
2.5V
GM2
-
U1OPA734
DC=0V
AC=1Vpk
As
+ +
Vref2.5
REF5025
Aol=VOA
1/ =VOA/VFB
Loop Gain =VFB
C1150n
Pu
bl
L11T
is
he
d
We will use the TINA-TI circuit in Fig. 10.60 to analyze if the predicted superposition results of FB#1
and FB#2 will produce the desired net 1/. It will also allow us to plot Aol, net 1/ and loop gain.
Zo Ex ternal M odel
CO13.4u
-
RLP129k
EN
+
Vs5
x1R
/O
x7.75E-3
CL47u
-
RO129
CLP12.3u
f LP = 0.1Hz
1
f LP = 2 RLPCLP
Riso13
Vout
2.5V
GMO
+
x1(/Riso+RL)
VO 2.5V
x1e-6
Fig. 10.60: Final Loop-Gain Analysis Circuit: CMOS RRO
RL1M
We see our analysis results (Fig. 10.61) confirm our predicted net 1/ plot. At fcl, where loop gain
goes to zero, we see our expected 20 dB/decade rate-of-closure.
T
140
120
Aol
100
Gain (dB)
80
60
fcl
40
ne
t
1/ 20
-G
en
iu
s.
0
STABLE
-20
1
10
100
1k
10k
100k
1M
10M
1M
10M
1M
10M
Frequency (Hz)
T
120
Loop Gain
100
40
20
0
Loop Gain : A:(172.64k; 40.12m) B:(146.43; 65.52)
Loop Phase : A:(172.64k; 87.79) B:(146.43; 66.54)
-20
-40
10
100
Pu
bl
1
1k
10k
100k
Frequency(Hz)
fcl
b
As
90
Phase [deg]
is
he
d
Gain (dB)
60
45
a
on
80
EN
Fig. 10.61: Final Net 1/: CMOS RRO
STABLE
0
1
10
100
1k
10k
100k
Frequency(Hz)
Fig. 10.62: Final Loop-Gain Analysis: CMOS RRO
The loop-gain phase plot for our final circuit, which uses FB#1 and FB#2 (Fig. 10.62) shows phase
shift never dips to less than 66.54° (at 146.43 Hz) and at fcl, 172.64 kHz, the phase margin is 87.79°.
We will do our final check on our stabilized circuit with a transient stability test using the TINA-TI
circuit of Fig. 10.63.
VFB 2.5V
RF100k
C1150n
VO 2.5V
-
Riso13
+ +
EN
CL47u
Vref2.5
2.5V
Vout
U1OPA734
RL1M
REF 5025
ne
t
Vs5
+ Vin
-G
en
iu
s.
DC=0V
Square Wave = +/-10mVpk
f =100Hz
Fig. 10.63: Final Transient Stability Test Circuit: CMOS RRO
T
on
EN
The results of our transient stability test on our final circuit (Fig. 10.64) agrees with all of our other
predictions resulting in a good, stable circuit we can put into production with confidence that we will
not have any failures or real world operation anomalies.
is
he
d
2.51
VFB
VOA
As
2.49
10.00m
Pu
bl
2.49
2.51
Vin
-10.00m
2.51
Vout
2.49
0.00
2.50m
5.00m
7.50m
Time (s)
Fig. 10.64: Final Transient Stability Test: CMOS RRO
10.00m
The TINA-TI circuit of Fig. 10.65 will allow us to confirm if our prediction of Vout/Vin is correct.
2.5V
VFB
RF100k
C1150n
-
Riso13
Vout
U1OPA734
+ +
ne
t
EN
Vref 2.5
-G
en
iu
s.
CL47u
Vs 5
R EF 5025
VO
+ Vin
RL1M
2.5V
EN
D C =0V
2.5V
on
AC=1Vpk
is
he
d
Fig. 10.65: Final Vout/Vin Transfer Function Circuit: CMOS RRO
We see that the results of our Vout/Vin test (Fig. 10.66) match our predicted first-order results with a
single pole roll-off at 253.88 Hz and a second at about 167 kHz where FB#2 intersects the Aol curve.
a
Pu
bl
T
0
-20
Vout / Vin
-60
-80
-100
As
Gain (dB)
-40
b
-120
-140
1
10
100
1k
10k
100k
1M
10M
Frequency(Hz)
0
Gain :
Vout/Vin A:(22.0022; 270.0877m) B:(253.8847; -2.7077)
Phase :
-45
Phase [deg]
Vout/Vin A:(22.0022; -4.057) B:(253.8847; -45.4605)
-90
-135
-180
1
10
100
1k
10k
100k
1M
Frequency(Hz)
Fig. 10.66: Final Vout/Vin Transfer Function: CMOS RRO
10M
Fig. 10.67 summarizes an easy-to-use step-by-step procedure for the Riso w/Dual Feedback capacitive
load stability technique on CMOS RRO output op amps.
FB#1 1/ Formulae:
1
Zero: fzx =
2 (
Note:
FB#2 1/ Formulae:
CO CL
CL+CO
CO CL
CL+CO
Assume:
CL & CO > 10 CF
RF > 10 Riso
) (Riso+RO)
is series combination of CO and CL
Pole: At Origin
1 CL+CO
=
for Low-f 1/ CO
Zero: fza =
1
2 RF CF
ne
t
CO and CL form a Capacitive Divider
12
13
EN
on
is
he
d
Pu
bl
7
8
9
10
11
Measure Aol of op amp
Measure & Plot Zo of op amp
Determine RO
Create Zo external model
Compute FB#1 Low-f 1/: equals 1 for unity gain voltage buffer
Set FB#2 High-f 1/ = +10 dB higher than FB#1 Low-f 1/ (For best Vout/Vin transient
response and least amount of phase shift within loop-gain bandwidth)
Choose Riso from FB#2 High-f 1/ and RO
Compute FB#1 1/ fzx from CL, Riso, RO
Set FB#2 1/ fza = 1/10 fzx
Choose RF and CF with practical values to yield fza
Run simulation with final values for Aol, 1/, loop gain, Vout/Vin, transient analysis to
confirm design
Check for loop-gain Phase shift NOT to dip more than 135° (>45° phase margin)
For low noise applications: check for flat Vout/Vin response to avoid gain peaking
leading to noise peaking in Vout/Vin
As
1
2
3
4
5
6
-G
en
iu
s.
High Frequency 1/ :
CO & CL = short
By Inspection:
RO+Riso
1/ =
for High-f 1/ Riso
Fig. 10.67: Riso w/Dual Feedback Compensation Procedure: CMOS RRO
About The Author
As
Pu
bl
is
he
d
on
EN
-G
en
iu
s.
ne
t
After earning a BSEE from the University of Arizona, Tim Green has worked as an analog and mixedsignal board/system level design engineer for over 23 years, including brushless motor control, aircraft
jet engine control, missile systems, power op amps, data acquisition systems, and CCD cameras. Tim's
recent experience includes analog & mixed-signal semiconductor strategic marketing. He is currently
the Linear Applications Engineering Manager at Burr-Brown, a division of Texas Instruments, in
Tucson, AZ and focuses on instrumentation amplifiers and digitally-programmable analog
conditioning ICs. He can be contacted at green_tim@ti.com