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ELECTRONICS
PHX 3205
DR. MIKE L. SEETI
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ELECTRONICS
[PHX3205 (3CU)]
CONTENTS
PART A: ANALOG ELECTRONICS
Lecture 1:
Linear Circuit Elements
Lecture 2:
Network Theorems: Kirchhoff’s Laws
Lecture 3:
Network Theorems: Potential Divider and Current Divider
Lecture 4:
Network Theorems: Superposition Principle
Lecture 5:
Network Theorems: Thevenin’s Theorem and Norton’s Theorem
Lecture 6:
AC Signals
Lecture 7:
Three-Phase Power Supply
Lecture 8:
Semiconductors
Lecture 9:
Diodes
Lecture 10:
Tuned Circuits and Filters
Lecture 11:
Bipolar Transistors: Structure
Lecture 12:
Bipolar Transistors: Small-Signal Equivalent Circuits
Lecture 13:
Common Emitter Amplifier
Lecture 14:
Emitter Follower
Lecture 15:
Two-Stage Amplifier
Lecture 16:
Field Effect Transistors
Lecture 17:
Feedback
Lecture 18:
Operational Amplifiers
Lecture 19:
DC Power Supplies
Lecture 20:
Regulated Power Supplies
PART B: DIGITAL ELECTRONICS
Lecture 21:
Digital Circuits
Lecture 22:
Logic Gates
Lecture 23:
Logic Algebra
Lecture 24:
Minimization of Logic Functions
Lecture 25:
Logic Families
Lecture 26:
Multivibrators
Lecture 27:
Flipflops
Lecture 28:
Binary Counters
Lecture 29:
Binary Adders
Lecture 30:
Multiplexers and Demultiplexers
Lecture 31:
Digital-to-Analog Converters
Lecture 32:
Analog-to-Digital Converters
3
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LECTURE 1
LINEAR CIRCUIT ELEMENTS
Introduction
In this lecture we briefly remind ourselves of the basic facts about three linear circuit
elements or components, namely, the resistor, the capacitor and the inductor.
Objectives
By the end of this lecture, you should be able to:

Calculate the resistance of a given material;

Calculate the resistance, capacitance or inductance of a series or parallel
connection;

Write down the relationship between voltage and current in a resistor, capacitor or
inductor;

Tell the resistance and tolerance of a given resistor by use of a color code;

Write down the expression for the capacitance of a parallel plate capacitor in
terms of its geometrical quantities;

Write down the expression for the energy stored in a capacitor or an inductor;

Write down the capacitive and inductive reactance;
RESISTANCE
A resistor is a device that obeys Ohm’s law (or nearly does so). The resistance of a device
is equal to the voltage across the device divided by the current flowing through it. The
unit of resistance is the ohm (). Resistance = Voltage / Current or R=V/I.
Calculation of resistance
Experiments show that the resistance R of a given material increases linearly with length
l of the material and is inversely proportional to the cross-sectional area A. The constant
of proportionality is called the resistivity  of the material.
R
l
A
(1.1)
The reciprocal of resistivity,   1 /  , is called the conductivity of the material. Equation
(1.1) shows that the thinner the wire (smaller diameter, since A  d 2 / 4 ) the larger the
resistance and also the longer the wire, the larger the resistance.
Temperature dependence
All resistance materials have a temperature dependence which can be approximated by
R(T )  R0 (1   .T )
(1.2)
where T  T  T0 is the change(rise) in temperature from T0 to T. R0 is the resiatnce at
temperature T0, and  is a constant called the temperature coefficient of resistance of the
material. For example copper has   57  10 6  1m 1 and   4.7  10 3 K 1 .
Circuit symbol
Figure 1.1 shows the circuit symbol of a resistor.
Fig. 1.1: circuit symbol of a resistor
5
If the current flowing through the resistor is I and the potential difference across the
resistor is V, then according to Ohm’s law the resistance R is given by R=V/I. The
reciprocal G=1/R is called the conductance. Its unit is the Siemen(S). Materials or devices
which obey Ohm’s law are often called ohmic devises. Thus a resistor is an ohmic device.
Power rating of a resistor
The power consumed or dissipated as heat in a resistor is given by P=VI. Hence by use
of R=V/I we can write the power as P=I2R or P=V2/R. Resistors are manufactured
according to how much power they can withstand or work normally without heating up
too much or burning out. The larger the size of the resistor the more power it can
withstand.
Series and parallel connection of resistors
Figures 1.2 (a) and 1.2(b) show a series and a parallel connection of three resistors R 1, R2
and R3.
R1
R1
R2
R3
R2
R3
Rseries= R1+R2+R3
Rparallel=1/(1/R1 +1/R2 +1/R3)
(a)
(b)
Fig. 1.2: Connection of three resistors R1, R2 and R3: (a) in series, and (b) in parallel.
6
The formulas for series and parallel connections can be extended to any number of
resistors, Rseries   Rk and G parallel   Gk , where Gk=1/Rk.
k
k
Resistance color code
The resistance values and their tolerance (or uncertainty) are usually indicated by a series
of colored bands or rings marked on the resistor as shown in Figure 1.3.
SF SF M T
Fig. 1.3: Resistance color code: SF=Significant Figure, M=Multiplier, T=Tolerance.
The first two bands (left to right) give the significant figures (SF), while the third and
fourth bands give the multiplier (M) and the tolerance (T) respectively. The value of the
resistance R can be expressed as
R  SF  10 M  T
7
(1.3)
Table 1.1 shows the resistance color code.
Table 1.1: Resistance Color Code
Color
SF
M
T
(%)
BLACK
0
0
20
BROWN
1
1
1
RED
2
2
2
ORANGE
3
3
3
YELLOW
4
4
4
GREEN
5
5
5
BLUE
6
6
6
VIOLET
7
7
7
GREY
8
-2
8
WHITE
9
-1
9
GOLD
-
-1
5
SILVER
-
-2
10
NO COLOR
-
-
20
Example
Suppose band1=brown, band2=green, band3=orange, band4=black.
Then SF=1 (brown)
SF=5 (green)
M=3 (orange)
T=20% (black)
Hence R  15  103  20% . Thus R lies between 12 and 18 k.
More accurate resistors have more than four bands. In this case the first three bands give
the significant figures (SF).
8
Standard resistance series
It is not possible to manufacture all resistors. Therefore practical values are produced in a
standardized series (see Seeti). Circuit designers have to use only these values unless they
make a special order from the manufacturers, which is cotly.
CAPACITORS
Capacitors are essential in nearly every circuit application They are used for waveform
generation, filtering, and blocking and bypass applications. They are used in integrators
and differentiators. In combination with inductors, they make possible sharp filters for
separating desired signals from background.
The capacitor
The capacitor is an ac (alternating current) passive element whose current I is
proportional to the rate of change of the potential difference, dv/dt, across it.
iC
dV
dt
(1.4)
The constant of proportionality C is called the capacitance of the capacitor (also called
condenser). It is a geometrical constant.
We know that electric current is the rate of flow of electric charge q, that is, i=dq/dt.
Therefore it follows from equation (1.4) that
q=CV
(1.5)
Thus when a voltage V is applied across a capacitor, a charge q proportional to V is
deposited on the capacitor. We say that the capacitor has been charged.
9
Circuit symbol and units
Figure 1.4 shows the circuit symbol of a capacitor.
C
Fig. 1.4: Circuit symbol of a capacitor
We see from equation (1.5) that the unit for capacitance is given by C=q/V, that is
coulomb per volt. However, the unit commonly used is the farad (F), so that a farad is
one coulomb per volt. Typical values of capacitance are always much less than 1F, so that
capacitances are normally quoted in microfarads (F), nanofarads (nF) or picofarads
(pF), where =10-6, n=10-9, and p=10-12.
Series and parallel connection of capacitors
Figures 1.5(a) and 1.5(b) show three capacitors C1, C2 and C3 connected in series and in
parallel respectively.
C1
C1
C2
C3
C2
C3
Cseries =1/(1/C1 +1/C2 +1/C3)
Cparallel = C1+C2+C3
(a)
(b)
Fig. 1.5: Connection of three capacitors C1, C2 and C3: (a) in series, and (b) in parallel.
10
We note that the formulas for series and parallel connections for capacitors are the
opposite of the corresponding connections for resistors. The consequence of this is that
capacitors in parallel carry more charge than capacitors in series, the capacitors in series
carry same charge. The above formulas can extended to any number of capacitors.
C parallel   C k and
k
1
C series

k
1
.
Ck
Capacitive reactance
Reactance is purely imaginary resistance, since no energy is dissipated in a capacitor. The
capacitor only stores the energy. The reactance of a capacitor is inversely proportional to
both its capacitance C and the angular frequency  of the voltage across the capacitor.
XC 
1
jC
(1.6)
Note that =2f, where f is the frequency in Hertz (Hz). The current I through a
capacitor and the voltage V across it are out of phase by 900, since
I  V / X C  jCV  CVe j 90 . Thus if V is drawn horizontally (pointing to the right),
0
then I points upwards perpendicular to V.
Parallel plates capacitor
There are two basic forms of practical capacitors, the parallel plates capacitor and the
cylindrical capacitor. A parallel plates capacitor consists of two parallel conductive plates
each of surface area A, separated by a short distance d. Short refers to d compared to the
dimensions of the plates (e.g. length or width). If the capacitor is charged by connecting
a voltage V across the plates, a charge Q=CV will accumulate on the plates (+Q on one
plate and –Q on the other). We see that if V is constant then Q is proportional to the
capacitance C of the geometrical setup. Thus we can use Q experimentally as a measure
for C.
11
Experiments show that C is proportional to A and inversely proportional to d. C also
depends on the medium (material) between the plates. Thus
C   0 r
A
d
(1.7)
where  0  8.855 pF m-1, is a constant known as the permittivity of free space (or
vacuum).  r is called the relative permittivity (or dielectric constant) of the insulator
between the plates. It gives the ratio of capacitances with a dielectric and without a
dielectric (in vacuum).  r is approximately unity for air at standard temperature and
pressure, about 7 for mica and about 80 for water. The quantity    0 r is the
permittivity of the material. It has the same units as  0 .
Cylindrical capacitor
The cylindrical capacitor consists of two conducting concentric cylinders which form the
plates. For cylinders of length l and radii r1 and r2 (r2>r1), the capacitance C is given by
C
2 l
ln( r2 / r1 )
(1.8)
where    0 r is the permittivity of the dielectric between the cylinders. For a derivation
of the formula see, for example Seeti, M.L.
Energy of a capacitor
Suppose we charge a capacitor to a voltage V. What will be the energy stored in the
capacitor? If we use equation (1.4), we can write the power P as P  Vi  CV
dV
. But
dt
since P is the rate of doing work, we can calculate the energy stored WC by use of the
integral W   Pdt   CV
dV
dt  C  VdV and assuming that the capacitor has no
dt
voltage initially (i.e., it is energy-free at t=0).
12
1
WC  CV 2
2
(1.9)
INDUCTORS
Inductors or coils find a lot of use in radio-frequency (RF) circuits, serving as tuned
circuits and as “chokes.” Coupled-inductors form transformers to step-down or step-up ac
voltage to match loads in amplifiers.
An inductor is an ac passive element whose voltage across it is proportional to the rate of
change of the current passing through it.
V L
di
dt
(1.20)
The constant of proportionality L is called the inductance of the inductor. It is measured
in a unit called a henry (H). One henry is equal to 1 VsA-1 or 1 s, as can be seen from
equation (1.20). An inductor is a coil of wire and its inductance L depends upon the
number of turns in the coil and the nature of the magnetic path (determined by the
permeability of the medium inside the coil). Equation (1.20) is called Fraday’s law (of
induction) and V is called the induced electro-motive force or e.m.f.
Circuit symbol
Figure 1.6 shows the circuit symbol of an inductor of inductance L.
L
Fig. 1.6: Circuit symbol of an inductor
The circuit symbol for an inductor looks like a coil of a wire; that is because, in its
simplest form, that is what it is. Variations include coils wound on various core materials,
the most popular being iron (or iron alloys, laminations, or powder) and ferrite, which is a
black, non-conducting, brittle magnetic material. These are all attempts to increase the
13
inductance of a given coil by increasing the permeability. The core may be in the shape of
a rod, a toroid or other shapes.
Series and parallel connection of inductors
Figures 1.7(a) and 1.7(b) show three inductors L1, L2 and L3 connected in series and in
parallel respectively.
L1
L1
L2
L3
L2
L3
Lseries =L1 +L2 +L3
Lparallel =1/(1/L1+1/L2+1/L3)
(a)
(b)
Fig. 1.7: Connection of three capacitors L1, L2 and L3: (a) in series, and (b) in parallel.
Inductors in series or in parallel combine like resistors. The formulas in Figure 1.7 can be
extended to any number of inductors.
Lseries   Lk and
k
1
L parallel

k
1
.
Lk
Transformers
A transformer is a device consisting of two closely coupled coils (primary and secondary
coils). An ac voltage applied to the primary coil appears across the secondary coil, with a
voltage multiplication proportional to the turns ratio (number of turns in primary to
number of turns in secondary coil) of the transformer and a current multiplication
inversely proportional to the turns ratio. Power is conserved. Figure 1.8 shows the circuit
symbol for a laminated-core transformer.
Fig. 1.8: Circuit symbol of a transformer
14
Transformers serve two important functions. They change the ac line voltage to a useful
(usually lower) value that can be used by the circuit, and they “isolate” the electronic
device from actual connection to the power line, because the windings of a transformer
are electrically insulated from each other.
Inductive reactance
Inductive reactance is a purely imaginary resistance of an inductor, since no energy is
dissipated in an inductor. The inductor only stores the energy. The reactance of an
inductor is directly proportional to both its inductance L and the angular frequency  of
the voltage across the inductor or the current through it.
X L  jL
(1.21)
Note that =2f, where f is the frequency in Hertz (Hz). The current I through an
inductor and
the voltage
V
across it
are out
of phase by 900, since
I  V / X L  V / jL  LVe  j 90 . Thus if V is drawn horizontally (pointing to the right),
0
then I points downwards perpendicular to V.
Energy in an inductor
Suppose we supply a current i(t) to an inductor of inductance L. What will be the energy
stored in the inductor? If we use equation (1.4), we can write the power P as
P  iV  Li
di
. But since is the rate of doing work, we can calculate the energy stored
dt
WL by use of the integral W   Pdt   Li
di
dt  L  idi and assuming that the inductor
dt
has no current initially (i.e., it is energy-free at t=0).
WL 
1 2
Li
2
(1.22)
15
Questions
1. A 240V/10A- fuse is made out of 40.0cm of constantan wire. Estimate the gauge
(diameter) of the wire. Take the conductivity of constantan to be approximately
equal to 2.0  10 6  1m 1 .
2.
[Ans: 0.1mm]
If the temperature coefficient of resistance of copper is 4.3x10-3 K-1, estimate the
largest temperature drift allowed if the resistance of a copper conductor should
not change by more than 5%. [Ans: 11.6K]
3. A given resistor has the following color code: Yellow/Violet/Red/Silver.
Determine the lower and upper possible values of the resistance. [Ans: 4230 5170]
4. A battery of emf VS=6V is connected across a parallel connection of two
capacitors C1=20F and C2=30F. Sketch the circuit and calculate the charge on
each capacitor.[Ans: 72C]
5. A capacitor C=10F is charged through a series resistor R=100 by connecting a
battery of emf VS=3V across the series connection of R and C.
(a) Find a differential equation for the voltage VC(t) across the capacitor.
[Ans: VC  10 3 VC  3  10 3 ]
(b) Solve the differential equation, given that the capacitor was energy-free


before it was charged. [Ans: VC (t )  3 1  e 10 t ]
(c) What is the time constant of the circuit?
3
[Ans: 1 ms]
(d) How long does it take the capacitor voltage to reach 98% of its end-value.
[Ans: t=ln503.9 ms]
(e) Calculate the energy stored in the capacitor.[Ans: 45x10-6 J]
6. (a) Explain how the inductance of a given coil can be increased.
(b) Give two applications of inductors.
7. A current source of amplitude Iˆ  20 mA and frequency f=1kHz, feeds an
inductor of inductance L=100mH.
(a) Calculate
the
magnitude
[Ans: 200628 ]
16
of
the
reactance
of
the
inductor.
(b) Calculate the amplitude of the voltage across the inductor.
[Ans: 412.6 V]
8. A battery of emf equal to 6V is connected across a series connection of a resistor
R=100 and an inductor L=10mH. After a long time (t>>L/R) the battery is
disconnected.
(a) What is the current at the instant when the battery is disconnected? What
is the voltage across the inductor at the same instant? [Ans: 0.06A]
(b) Find the current i(t) through the inductor and the voltage V(t) across it.
Sketch i(t) and V(t). [Ans: i(t )  0.06e 10 t , V (t )  6e 10 t ]
4
4
(c) Fall-time is defined as the time for the amplitude of a signal to fall from
90% to 10% of its maximum value. Show that the fall-time for i(t) is given
by tf=ln9, where  is the time constant of the circuit.
(d) If rise-time tr is defined as the time for the amplitude of a signal to rise
from 10% to 90% of its maximum value, show that the rise-time for the
voltage V(t) is equal to the fall-time for the current i(t).
Further Reading
Seeti, M.L.: Basic Electronics 2003.
17
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LECTURE 2
NETWORK THEOREMS: KIRCHHOFF’S LAWS
Introduction
The lectures under the title Network Theorems introduce some useful tools or methods of
circuit analysis. In this lecture we introduce Kirchhoff’s laws and give some examples
how the laws can be applied. To the majority of readers, Kirchhoff’s laws may not be
new to them as the laws appear in a course in Electricity & Magnetism. We repeat the
laws here to emphasize their importance.
Objectives
By the end of this lecture, you should be able to:

State Kirchhoff’s current law;

Sate Kirchhoff’s voltage law;

Give a physical explanation of Kirchhoff’s current law;

Write down node equations of simple circuits;

Write down loop equations of simple circuits;
Kirchhoff’s laws
Kirchhoff’s laws are two simple, and intuitively obvious, laws concerning currents at a
node and potential differences across elements in a closed loop.
Kirchhoff’s current law
Kirchhoff’s current law is a result of the conservation of charge. The fact that no charge
can accumulate at a node leads to the implication for circuit analysis, that no current can
accumulate at a node. The law states that the algebraic sum of the currents at a node is
zero. Mathematically we can write this as:
n
i
k 1
k
0
(2.1)
Figure 2.1 shows an example of a node with n=4 branches.
i1
i2
i3
i4
2.1: Kirchhoff’s current law; example of node with four currents
If we choose the currents going into the node to be positive and the currents going out of
the node to be negative, then an algebraic sum of the currents gives the equation
i1  i2  i3  i4  0
If we choose the currents going out of the node to be positive and the currents going into
the node to be negative, then the algebraic sum of the currents gives the equation
 i1  i2  i3  i4  0
These two equations are equivalent. This means that the direction for the currents chosen
to be positive is arbitrary. Equation (2.1) is usually referred to a node equation. The
labeling of the directions of the currents in Figure 2.1 is also arbitrary. In practice we
choose any directions, for example as in Figure 2.1, and then we use Kirchhoff’s current
law. If the value of any of the current turns out to be negative, this simply means that the
actual direction of flow of the current is opposite to that shown in the diagram.
Kirchhoff’s voltage law
19
Kirchhoff’s voltage law states that the algebraic sum of the voltages around any loop of a
circuit is zero. Mathematically we can write the law in the form
n
V
k 1
k
0
(2.2)
The voltages Vk include all voltage sources and potential differences across all
components in a given loop. Figure 2.2 show two simple examples of circuit loops, a
series circuit with a single loop and a parallel circuit with several possible loop.
i
Z1
Z2
Z3
i
ZS
i1
VS
V1
V2
V3
VS
(a)
i2
Z1
Z2
i3
Z3
(b)
Fig. 2.2: Examples of Kirchhoff’s voltage law
In Figure 2.2(a) the voltages across the components or branches Z1, Z2 and Z3 are given
by V1=iZ1, V2=iZ2 and V3=iZ3, in the directions indicated (determined by the direction of
the current). If we run through the loop in a clockwise direction, the loop (or mesh)
equation becomes:
V1  V2  V3  VS  0
or
i(Z1  Z 2  Z 3 )  VS  0 .
Note that if we had run through the loop in the opposite (anticlockwise) direction, the
loop equation would be
 i(Z1  Z 2  Z 3 )  VS  0 .
This equation is obviously equivalent to the first one. This means that the direction in
which we traverse or run through the loop can be chosen arbitrarily.
20
The circuit in Figure 2.2(b) contains several loops. For example:

The loop containing the voltage source VS and the branches Z1 and Z2 has the
loop equation: iZ S  i1 Z1  VS  0

The loop containing the voltage source VS and the branches ZS and Z2 has the
loop equation: iZ S  i2 Z 2  VS  0

The loop containing the voltage source VS and the branches ZS and Z3 has the
loop equation: iZ S  i3 Z 3  VS  0

The loop containing the branches Z1 and Z2 has the loop equation:
 i1 Z1  i2 Z 2  0

The loop containing the branches Z1 and Z3 has the loop equation:
 i1 Z1  i3 Z 3  0

The loop containing the branches Z2 and Z3 has the loop equation:
 i2 Z 2  i3 Z 3  0
However, not all these equations are independent. Suppose we were interested in finding
the currents i, i1, i2 and i3. This would necessitate four equations in the four unknowns.
One of the equations would be obtained by writing down the node equation (Kirchhoff’s
first law), namely, i  i1  i2  i3  0 . This leaves us with a need for three more equations.
Example:
Calculate using Kirchhoff’s laws the currents i1, i2, and i3 in Figure 2.3.
i1 A
4
6V
i2
L1
10
21
i3
L2
15
We have three unknown, namely, i1, i2, and i3. Therefore we need three equations in these
three unknowns. The first equation is obtained from a node equation and the remaining
two equations are obtained from loop equations. We use the following loops: The loop
containing only i1 and i2, and the loop containing only i2 and i3. Writing the above
mentioned equations gives
Node A:
i1  i2  i3  0
Loop L1:
4i1  10i2  6
Loop L2:
10i2  15i3  0
or
i1  i2  i3  0
2i1  5i2  3
2i2  3i3  0
This system of linear equations can be solved in several ways. For example we can use
Cramer’s rule to solve the equations, if we first write the equations in the matrix form:
 1  1  1  i1   0 

   
0  i2    3 
2 5
 0 2  3 i   0 

 3   
 1  1  1


0  , so that   A , the determinant of matrix A, then according
If we let A   2 5
 0 2  3


to Cramer’s rule
i1  1 /  , i2   2 /  and i3   3 /  ,
where  k is the determinant of the matrix A after the kth column has been replaced by the
 0
 
column vector  3  . From above we get   25 , 1  15 ,  2  9 , and  3  6 .
 0
 
22
Hence i1  15 /  25  0.6 A, i2  9 /  25  0.36 A, and i3  6 /  25  0.24 A.
You can check these results by solving the above equations using a different method of
solving simultaneous equations.
Questions
1. (a) State Kirchhoff’s laws.
(b) Use Kirchhoff’s laws to determine the currents i1, i2, and i3 in the circuit
below. [Ans: 0.1A, 0.06A, 0.04A]
i2
i3
i1
100
5
150
6.5V
2. Show that the potential difference across R3 in the circuit below is given by
V3 
( R1VS 2  R2VS1 ) R3
R1 R2  R1 R3  R2 R3
R1
VS1
R2
R3
VS2
3. A 12V/dc power supply having a 2 internal resistance feeds a network of
resistors as shown in the circuit diagram below.
23
Power supply
+
2
10
20
12V
20
10
-
(i) Calculate the current supplied by the power supply. [Ans: 0.5A]
(ii) What is the power lost inside the power supply. (Hint: P=i2R).
Further Reading
Banda, E.J.K: Electricity and Magnetism
24
[Ans: 0.5W]
LECTURE 3
NETWORK THEOREMS:
POTENTIAL DIVIDER AND CURRENT DIVIDER
Introduction
The this lecture we introduce two simple rules for determining the voltages across two
resistors connected in series and the current in two resistors connected in parallel.
Objectives
By the end of this lecture, you should be able to:

State the potential divider rule;

Sate the current divider rule;

Use the potential divider rule to determine the voltage across components in
series;

Use the current divider rule to determine the currents in two parallel components;

Calculate the shunt for a moving coil movement meter;
The potential divider
Let us consider two resistors R1 and R2 in series connected across a voltage V0 as shown
in Figure 3.1.
i
R1
V1
R2
V2
V0
Fig. 3.1: The potential divider
25
Since the circuit is a series circuit, the current flowing throughout the circuit is the same.
That is, the current in R1 is the same as the current in R2. therefore by use of Ohm’s law
we can write down the potential differences V1 and V2:
V1=iR1, V2=iR2
By use of Kirchhoff’s voltage law, we can write the loop equation and use it to determine
the series current i:
V1+V2-V0=0
iR1+iR2-V0=0
i(R1+R2)=V0
Therefore
i=V0/( R1+R2)
If we substitute for i in the expressions for V1 and V2 we finally get
V1 
R1
V0
R1  R2
(3.1)
V2 
R2
V0
R1  R2
(3.2)
V1 and V2 are the voltages of the potential divider in Figure 3.1. We see that the voltage
across R1 is given by the ratio of R1 divided by the sum R1+R2 of the two resistors in
series, multiplied by the potential difference across the two resistors. In a similar way we
can also write down the voltage across R2. thus we can easily write down V1 and V2 using
the above rules.
Potential dividers are used to vary voltage or tap off a small voltage from a larger voltage.
For example suppose need a voltage of 1.5V but we have a supply or source of 6V. We
can design a potential divider to give the required voltage. For example can make
26
R1
R
1
or simplified 2  3 . The actual values for R1 and R2 are determined by

R1  R2 4
R1
the current (or power) capability of the circuit.
Example: Suppose we need to use a battery of emf 12V and internal resistance 1.0 to
supply power to 4V/4mA small hand radio set. We can design a potential divider for this
purpose. Figure 3.2 shows the circuit diagram.
Battery
r=1
+
R2
E=12V
V0
R1
V1
-
Fig. 3.2
We need to find the values of the potential divider (or potentiometer) R1, R2. Now the
potential difference V0 across the potential divider is given by V0 
R1  R2
E.
R1  R2  r
Therefore we must choose R1 and R2 such that R1  R2 >>r in order to ensure that almost
all the emf E appears across the potential divider. For example if both R 1and R2 are in
kilo-ohms (k), the above condition is easily satisfied. The required voltage V1=4V is
then approximately given by
V1 
R1
R1
R
E or 4 
 12 or 2  2 .
R1  R2
R1  R2
R1
27
Another condition we use is that the current for the radio should not exceed 4mA. The
current supplied by the battery is given by
i
E
E

r  R1  R2 R1  R2
Therefore i=40mA, if R1  R2 =3 k. We now have two simultaneous equations in R1
and R2, namely:
R2
 2 and R1  R2  3000 .
R1
A solution for R1 and R2 gives R1=1 k and R2=2 k.
Note that the voltage drop across the internal resistance r is
r
12
E
 4mV
r  R1  R2
3001
. This is negligible compared to 12V, so that the potential difference across the
potentiometer is approximately equal to 12V.
The size of the resistors R1 and R2 for the potentiometer is determined by their power
rating. The power dissipated in form of heat in the potentiometer is given by
P  i 2 R  (4  10 3 ) 2 x3000  0.048 W or 48mW.
This means that we can use ¼-W resistors R1 and R2.
The current divider
The current divider consists of two resistors in parallel as shown in Figure 3.3.
R0
i0
i1
i2
L1
V0
R1
28
R2
Fig. 3.3: Current divider
The current i0 is divided into two currents i1 and i2 flowing through the parallel resistors
R1 and R2 respectively. As we shall soon find out, the larger of the two currents will flow
through the smaller resistance. We need to find expressions for i1 and i2 in terms of R1, R2
and i0. We start by writing the node equation and the loop equation for the loop
containing only the components R1 and R2 (loop L1):
i0  i1  i2  0
i1 R1  i2 R2  0
These are two linear simultaneous equations in two unknowns i1 and i2. Solving for i1 and
i2 we get
i1 
R2
i0
R1  R2
(3.3)
i2 
R1
i0
R1  R2
(3.4)
Thus i1 is given by the “other resistor” divided by the sum of the two parallel resistors,
times the current feeding the parallel combination of resistors. The “other resistor” means
not the resistor carrying i1. We can make similar statements for i2. The expressions above
are easy to remember and can make circuit analysis easier if a current divider is
identified.
Current dividers are used in ammeters to extend the ammeter’s range. A parallel resistor
(called a shunt) is used to make some of the current bypass the movement coil of the
meter.
29
Example: A dc ammeter with a full-scale deflection (fsd) current of 100mA has a coil for
the meter movement with a resistance of 1000. What shunt is needed to make
the ammeter measure currents up to 1.0A?
Figure 3.4 shows the current divider, where Rm=1000 is the resistance of the movingcoil meter, and RP is the required shunt.
I0=1A
0.1A
Rm
0.9A
RP
Fig. 3.4: Adding a shunt resistor to a basic meter
Since the fsd current is 0.1A and the ammeter is required to read 1.0A, the rest of the
current, 1.0-0.1=0.9A, must be diverted to through the shunt RP. By use of the current
divider rule we have that
0.9 
Rm
 1.0
Rm  R P
RP 
Rm 1000

 111.
9
9
Hence
30
Questions
1. (a) What is a potential divider? What characterizes a potential divider?
(b) What is a current divider? What characterizes a current divider?
2. (a) State the potential divider rule.
(b) A battery of 12V is connected across a series connection of two resistors of
resistances 100 and 500.
(i)
Sketch the circuit.
(ii)
Use the potential divider rule to determine the voltages across the two
resistors. [Ans: 2V, 10V]
3. (a) State the current divider rule.
(b) A battery of emf V0=12V and internal resistance R0=5 is connected across a
parallel combination of two resistors R1=100 and R2=300.
(i)
Sketch the circuit.
(ii)
Determine the current i0 through R0.
(iii)
Use the current divider rule to find the currents through R1 and R2.
[Ans: 150mA]
[Ans: 112.5mA, 37.5mA]
4. What value of series resistance is required for a 50A, 2000 meter movement if
the full-scale deflection voltage of the overall meter is to be 100V? What will be
the overall meter resistance? [Ans: 1998k, 2M]
5. What value of parallel resistance (shunt) is required for a 50A, 2000 meter
movement if the full-scale deflection current of the overall meter is to be 1.0A?
What will be the overall meter resistance?
Further Reading
Seeti, M.L.: Basic Electronics 2003.
31
[Ans: 2000/19105.3, 100]
LECTURE 4
NETWORK THEOREMS: THE SUPERPOSITION PRINCIPLE
Introduction
In this lecture we first introduce the equivalent circuits of voltage and current sources and
derive the relationship between a voltage source and its current source equivalent circuit.
We then state the superposition principle and use examples to illustrate how the principle
can be applied.
Objectives
By the end of this lecture, you should be able to:

Represent a voltage source by an equivalent circuit;

Represent a current source by an equivalent circuit;

Convert a voltage source a current source and vice-versa;

State the superposition principle;

Use the superposition principle to calculate the current in any branch of a network
of linear circuit elements.

Use the superposition principle to calculate the voltage across any branch of a
network of linear circuit elements;
Voltage and current sources (or generators)
The most common voltage source we meet very often is the dry cell, for example 1.5V
dry cell for a torch light. We can represent the battery as an ideal emf source in series
with a series resistor, called the internal resistance. Figure 4.1(a) shows the equivalent
circuit of a battery. The circuit is also known as Thevenin’s equivalent circuit of a
battery.
32
RS
IS
RS
VS
(a)
(b)
Fig. 4.1: (a) Voltage Source, (b) Current Source
The voltage source is said to be ideal if the internal resistance RS is zero. The output
voltage of an ideal voltage source remains the same whatever the load may be. The
internal resistance is usually relatively small compared with the normal range of the load
resistance, so that the load voltage is approximately equal to the voltage source emf.
Another equivalent circuit of a battery (or any dc source) is the current source, shown in
Figure 4.1(b). The current source, also known as Norton’s equivalent circuit, consists of
an ideal current source IS and an internal resistance RS in parallel with the ideal current
source. If the internal resistance RS is infinitely large (zero conductance) the current
source is said to be ideal. The current of an ideal current source remains the same
whatever the load may be.
We can deduce the relationship between the voltage source quantities VS and RS, and the
current source quantities IS and RS , by considering both circuits under two different load
conditions. The first load condition is when the load is zero (RL=0), a condition called a
short circuit. The second circuit condition is when the load in infinite (RL= ), a circuit
33
condition called an open circuit. The two circuit conditions are shown in Figures 4.2(a)
and 4.2(b).
RS
IS
VS
RS
IS
IS
(a) Short circuits: IS=VS/RS
RS
IS
RS
VS
VS
IS
(b) Open circuits: VS=IS RS
Fig. 4.2: Voltage and current sources under, (a) short circuit, (b) open circuit.
Under a short circuit the short-circuit current is given by IS=VS/RS, and under an open
circuit, the open-circuit voltage is given by VS=IS RS . Comparing these two equations
show that we must have that RS =RS, that is, the series internal resistance RS of the
voltage source is equal to the parallel internal resistance RS of the current source. This
means that the two equivalent circuits of a dc source in Figures 4.1(a) and 4.1(b)
represent the same source if RS =RS, where IS=VS/RS or VS=ISRS. These relationships are
important in converting a voltage source into a current source and vice-versa.
34
The superposition principle
The superposition principle is widely used in physics. For example the resultant effect of
two or more waves at a point can be found by determining the effects due to the
individual waves and then adding them algebraically to obtain the overall effect. This
principle may also be used to determine the current in a circuit component, or voltage
across it, due to several (multiple) sources. However, the principle can only be applied to
linear circuits, that is, circuits containing only linear circuit components. We may state
principle as follows.
In a linear network with multiple sources, the current in a given branch (or
voltage across it) is equal to the algebraic sum of the currents in the branch (or
voltages across it) due to the individual sources acting alone.
Example 1:
Figure 4.3 shows two voltage sources VS1 and VS2, having internal resistances R1 and R2
respectively, feeding a resistor R3. Suppose that we need to find the current I3 flowing
through the resistor R3 as indicated in the diagram.
R1
R2
VS1
R3
I3
Fig. 4.3
35
VS2
We first eliminate the voltage source VS2 by shorting (or short-circuiting) it and call the
current in R3, I 3 . Then we short VS1 and call the current in R3, I 3 . The two resulting
circuits are shown in Figure 4.4.
I1
R1
I2
I 3
I 3
VS1
+
R3
R2
R2
VS2
R1
R3
Fig. 4.4: Example of the superposition principle: I3= I 3 + I 3
According to the superposition principle the circuit diagram in Figure 4.3 is equivalent to
the two circuit diagrams in Figure 4.4, so that I3= I 3 + I 3 . We use the two circuits in
Figure 4.4 to determine I 3 and I 3 . Note that we made the directions of I 3 and I 3 in R3
the same as that of I3 in Figure 4.3. This is important in order to make use of I3= I 3 + I 3
simple. If for example we reversed the direction, say I 3 , then the correct equation to use
would be I3=- I 3 + I 3 .
To determine I 3 and I 3 we can use any method which is most convenient. For example
to determine I 3 we can use the current divider rule:
I 3 
R2
I1
R2  R3
The current I1 is given by
36
I1 
where RP  R2 // R3 
VS 1
R2  R P
R2 R3
, the parallel combination of R2 and R3.
R2  R3
Example 2:
We modify the circuit in Figure 4.3, so that the circuit has a voltage source VS1 of internal
resistance R1 and a current source IS2 of internal resistance R2 as shown in Figure 4.6.
R1
IS2
VS1
R3
R2
I3
Fig. 4.5
A current I 3 due to VS1 alone is obtained by “removing” the ideal current source IS2, as
shown in the circuit on the left in Figure 4.6.
I1
R1
I 3
I 3
VS1
IS2
+
R3
R2
R1
Fig. 4.6:
37
R3
R2
The ideal current source is “removed,” meaning that the two terminal of the ideal current
source IS2 are disconnected. The current I 3 due to the current source alone is obtained by
shorting the ideal voltage source VS2, as shown in the circuit on the right in Figure 4.6.
To determine I 3 we can use the same method as we did in Example 1. To determine I 3
we can use the current divider rule by first combining the parallel resistors R1 and R2, into
a resistor RP  R1 // R2 
R1 R2
RP
. Then I 3 becomes I 3 
IS2 .
R1  R2
RP  R3
Questions
1. A dc voltage source has an emf of 12V and internal resistance 50.
(a) Draw the equivalent circuit (Thevenin’s equivalent circuit) of the dc voltage source.
(b) Determine and draw an equivalent current source (Norton’s equivalent circuit).
[Ans: I=0.24A]
2. (a) Define an ideal voltage source and an ideal current source.
(b) Are ideal sources possible in reality?
3. (a) State as clearly as possible the Superposition Principle concerning currents in a
network.
(b) What are the limitations of the principle?
4. Given is the circuit in Figure 4.7 in which two ideal current sources feed a network of
three resistors.
I3
470
0.5A
0.3A
10
20
Fig. 4.7
38
(a) By converting the current sources into voltage sources, determine
the current I3 through the 470 resistor. [Ans: 22mA]
(b) Use the superposition principle to determine the current I3 through
the 470 resistor. [Ans: I 3  I 3  I 3  10  12  22 mA]
Further Reading
Seeti, M.L.: Basic Electronics 2003.
39
LECTURE 5
NETWORK THEOREMS: THEVENIN’S THEOREM
Introduction
In this lecture we introduce Thevenin’s theorem, one of the most important network
theorems. We start by stating the theorem and then by use of example learn how to
determine Thevenin’s equivalent circuit. At the end we show the relationship between
Thevenin’s theorem and Norton’s theorem.
Objectives
By the end of this lecture, you should be able to:

State Thevenin’s theorem;

State Norton’s theorem;

Determine Thevenin’s equivalent circuit of a given network;

Determine Norton’s equivalent circuit of a given network by use of Thevenin’s
theorem.
Thevenin’s theorem
We start by stating Thevenin’s theorem as follows:
Any linear network of sources and impedances, having a two-terminal output
load, is equivalent to a voltage source (Thevenin’s equivalent circuit) in series
with the load.
The above statement is very brief and needs some clarification. A linear network will
consist of only linear circuit elements (R, L, C). Sources include voltage and current
sources. Impedance means the complex resistance in general. The load of the network can
be chosen to be any two-terminal element. Figure 5.1 illustrates Thevenin’s theorem.
40
A
RTh
A
LINEAR
NETWORK
RL

VTh
B
RL
B
Fig. 5.1: Thevenin’s equivalent circuit
Thevenin’s equivalent circuit consists of a voltage source of emf VTh, called the Thevenin
voltage, and an internal impedance RTh, called the Thevenin resistance, in series with the
load RL. Although here we have used resistances for R L and RTh, the theorem is true for
impedances ZL and ZTh in general.
Thevenin’s theorem reduces the network circuit to a simple series circuit. The theorem is
only useful if we can find VTh and RTh. This is usually the major limitation. So how do
we find VTh and RTh?
Finding VTh
Let us look at Thevenin’s equivalent circuit in Figure 5.1. If we remove the load, we get
an open circuit (RL=) whose open-circuit voltage is equal to VTh measured between the
terminals A and B. This gives us a way of determining the Thevenin voltage VTh. VTh is
the open-circuit voltage between the load terminals A and B of the network, as indicated
in Figure 5.2(a).
41
A
NETWORK
WITHOUT
SOURCES
NETWORK
VTh
B
A
RTh
B
(a)
(b)
Fig. 5.2: Using open-circuit network to determine, (a) VTh, (b) RTh.
Finding RTh
Again we look at Thevenin’s equivalent circuit in Figure 5.1 by considering an open
circuit at the output. We see that if the Thevenin voltage VTh is shorted, then if we
measured the resistance between the output terminals A and B, we would get RTh.
Shorting VTh is equivalent to replacing all the sources in the network with their internal
resistances. This is true because without the sources there cannot be VTh. Therefore we
obtain RTh by considering the network without any sources and then measuring the
resistance at the output, as illustrated in Figure 5.2(b).
There is another method of finding RTh. We again look at Thevenin’s equivalent circuit in
Figure 5.1. If we consider a short circuit (i.e., RL=0), we see that the short circuit current
is given by
I SC  VTh / RTh
Therefore if can determine VTh and ISC, then we can calculate RTh as
RTh  VTh / I SC
Thus the method depends on being able to determine VTh correctly first. The short-circuit
current ISC is obtained from the network by shorting the load and then calculating ISC.
42
Examples
Let us consider the network in Figure 5.3.
R1
D
R3
A
VS
C
R2
R4
I2
B
Fig. 5.3
(a) Determine the current I2 through R2 using Thevenin’s theorem.
We consider R2 as the load giving Thevenin’s equivalent circuit as shown in Figure
5.4(a).
RTh
A
I2
I2 
VTh
R2
B
Fig. 5.4(a)
43
VTh
RTh  R2
R1
R3
R1
A
VS
A
VTh
R4
 VS
RS
B
VTh
B
Fig. 5.4(b): Determining Thevenin voltage VTh:
VTh 
R1
RS
VS , RS  R3  R4
RS  R1
R3
R1
A
A
R4

B
RTh  R1 // RS
RS
B
RTh
Fig. 5.4(c): Determining Thevenin resistance RTh.
Figure 5.4(b) shows how VTh is determined by an open-circuit voltage, while Figure
5.4(c) shows how RTh is determined by an open-circuit at the output after short-circuiting
the voltage source VS. The required current, as seen from Figure 5.4(a), is then given by
I2 
VTh
.
RTh  R2
44
(b)
Determine the current (from C to B) through R4.
Figure 5.5 shows the required equivalent circuits.
RTh
R1
R3
C
C
I4
VTh
R4
VS
R2
B
B
Fig. 5.5(a)
Fig. 5.5(b)
R1
R3
C
R2
RTh
B
Fig. 5.5(c)
(c)
VTh
Determine the current (from D to A) through R1.
Figure 5.6 shows the necessary circuits.
45
RTh
R3
D
D
VTh
A
C
I1
VTh
R1
VS
R2
A
R4
B
Fig. 5.6(a)
Fig. 5.6(b)
RTh
R3
D
A
C
R2
R4
B
Fig. 5.6(c)
(d)
Draw the circuits for determining the current through R3. The currents through R3
and R4 should be the same, since the two resistors are in series.
In all the above examples we have tried to determine the currents in different circuit
elements. We could as well have tried to determine the voltages across these elements. As
46
we can see from Thevenin’s equivalent circuit in Figure 5.1, the voltage across the load
may be written down by use of the potential divider rule as
VL 
RL
VTh
RL  RTh
It is also important to note that the current through the load is given by
IL 
VTh
VL
.

RL RL  RTh
Norton’s theorem
Norton’s theorem is similar to Thevenin’s theorem except that we use a current source
instead of a voltage source.
Any linear network of sources and impedances, having a two-terminal output
load, is equivalent to a current source in series with the load.
A
A
LINEAR
NETWORK
IN
RL

RN
B
RL
B
Fig. 5.7: Norton’s equivalent circuit
47
Figure 5.7 illustrates Norton’s theorem. To determine the current source IN and its
internal resistance RN, we use Thevenin’s theorem and convert Thevenin’s voltage source
into a current source. We then find that
IN=VTh/RTh
RN=RTh
But VTh/RTh=ISC, the short-circuit current of the network. Therefore to find Norton’s
equivalent circuit we need to determine IN=ISC and RN=RTh.
Questions
1. (a) State in very clear terms, Thevenin’s theorem.
(b) A linear network has a load ZL. Draw Thevenin’s equivalent circuit and describe
how the Thevenin voltage VTh and the Thevenin impedance ZTh can be determined.
2. (a) State in very clear terms, Norton’s theorem.
(b) How is Norton’s theorem related to Thevenin’s theorem.
3. A voltage source of emf 12V and internal resistance R1=50 feeds a network of
resistors R2=150, R3=300 and R4=200, as shown in the circuit diagram in Figure
5.8.
R1
R2
12V
R3
Fig.5.8
48
R4
(a) Use Thevenin’s theorem to determine the current through R3.
[Ans: VTh=6V, RTh=100, I3=15mA]
(b) What is the voltage across R4? [Ans: VTh=7.2V, RTh=150,
V4=28.8/74.1V15mA]
4. Determine Norton’s equivalent circuit for the network in Figure 5.8 with R2 as the
load. [Ans: IN=ISC=(12/170)A, RN=170]
5. The circuit in Figure 5.9 shows a Wheatstone bridge. The resistor R5 represents the
resistance of a galvanometer.
R2
R1
R5
I5
VS
R3
R4
Fig. 5.9
(a) Use Thevenin’s theorem to find an expression for the current I5 through the
galvanometer.
49
[Ans:
I5 
VTh 
R2 R3  R1 R4
VS ,
( R1  R3 )( R2  R4 )
RTh  ( R1 // R3 )  ( R2 // R4 ) ,
VTh
, etc.]
RTh  R5
(b) Hence find the condition for null deflection in the galvanometer.
[Ans: R2R3=R1R4 or R1/R2=R3/R4]
Further Reading
Seeti, M.L.: Basic Electronics 2003.
50
LECTURE 6
A.C. SIGNALS
Introduction
In this lecture we review the sinewave and introduce new quantities related to the
sinewave and other waveforms. We introduce the idea of a complex amplitude and its
graphical representation by a phasor diagram. Power in ac circuits is discussed and the
distinction is made between active and reactive power. Lastly transient currents and
voltages, resulting from switching on or off an energy source, are discussed using
examples.
Objectives
By the end of this lecture, you should be able to:

Determine the root-mean-square (rms) value and the mean absolute value of an ac
signal;

Calculate the time-varying current or voltage of a linear component in an ac
circuit;

Calculate the phase difference between the current and voltage of a component in
an ac circuit;

Draw a phasor diagram of an a.c.circuit;

Calculate the power involved in an ac circuit;

Calculate the step(unit step function) response of RC- and RL-circuits.
Sinusoidal signal
The sinusoidal signal is one of the commonest ac (alternating current) signals. The signal
has several characteristics and can be written down in form of a wave, sinewave, as
A(t )  Aˆ sin(t   )
51
where  is the maximum value of A(t) called its amplitude, =2f is the angular
frequency (s-1), f is the frequency in Hertz(Hz), and  is called the phase angle or simply
the phase. A(t) could be a voltage or a current (or even power). Figure 6.1 shows the
sinewave A(t) for =0.
A(t)
Â
0
T
2
T
3T
2
2T
t
- Â
Fig. 6.1: Sinewave signal
T is called the period, and it is related to the frequency f by f=1/T. Other quantities which
characterize a siewave include the following:

The root-mean-square (rms) value, or effective value, defined by
Arms 
1 t 0 T 2
A (t )dt
T t0
Â
For a sinewave A(t )  Aˆ sin(t   ) , Arms 
.
2

APP=2  is called the peak-to-peak value. The amplitude  is also
sometimes called the peak-value (also denoted by AP).
52

The average absolute value or mean modulus is defined by
A
1 t0 T
A)t ) dt
T t0
For a sinewave we have in general that A  Arms  Aˆ  APP .
The ratio of peak voltage  to rms-value Arms,  /Arms, is called the
“crest factor.”
Complex amplitude
From the theory of complex numbers we have that e jx  cos x  j sin x , so that we can
write cosx=Re(ejx) and sinx=Im(ejx). That is, cosx is the “real part of” ejx and sinx is the
“imaginary part of” ejx. In a similar way we can write a sinewave signal either as a real or
imaginary part of a complex signal quantity.
If for example a(t )  Aˆ cos(t   ) , then we can write a(t) as

a(t )  Re Aˆ e j (t  )

But since e j (t  )  e jt .e j , we can rewrite the above expression as

a(t )  Re Aˆ e j .e jt

or


a(t )  Re Ae jt , A  Aˆ e j .
The quantity A  Aˆ e j is called the complex amplitude. The complex amplitude is useful
in drawing phasor diagrams. We can use complex amplitude in calculations and then win
back the time-dependent (rotating phasor) signal by either taking the real or imaginary
part.
53
Example
A sinusoidal voltage V (t )  Vˆ sin t is connected to a series circuit of a resistor R and a
capacitor C as shown in Figure 6.2. Find the voltage VC(t) across the capacitor.
R
i(t)


V(t)
C
VC(t)
Fig. 6.2


Since V (t )  Im Vˆe jt , we can write the complex amplitude for V(t) as V= Vˆ . Therefore
by use of the potential divider rule (see Lecture 3), we can write the complex amplitude
of the capacitor voltage as
VC 
where
VˆC 
1 / jC
V
V
 VˆC e  j
R  1 / jC
1  jCR
Vˆ
1   2C 2 R 2
and   arctan(CR) .
Hence




VC (t )  Im VC e jt  Im VC e j (t  )  VˆC sin(t   ) .
We have used the imaginary part because the voltage source V (t )  Vˆ sin t can be
written as the imaginary part. If instead we had V (t )  Vˆ cos t , we would use the real
part.
54
It is advisable to differentiate between the time-varying quantities and the complex
quantities or amplitudes (frequency-dependent quantities). We usually do this by using
lower-case letters for the time-varying signals, e.g. i(t), and upper-case letters for
complex amplitudes, e.g. I. In the circuit diagram we may then simply indicate the
complex amplitudes for both currents and voltages.
Phasor diagram
We have seen that the complex amplitude of a sinewave can be specified by the
magnitude and its phase. The complex amplitude may be represented graphically by a
line of length proportional to the magnitude of the amplitude and an angle, measured
from the horizontal (or phase reference axis). Such a representation of a sinewave as
shown in Figure 6.3 is called a phasor diagram.
Â

(phase-reference axis)
Fig. 6.3: Phasor A  Aˆ e j
Examples
1. A sinusoidal voltage V (t )  Vˆ sin t feeds a series connection of a resistor R and a
capacitor C as shown in Figure 6.4(a). The voltages and currents shown in the diagram
are all complex amplitudes.
55
R
VR
I

I
VR
V
V
C
VC
VC
(a)
(b)
I
IR
IC
IL
I
V
R
C
L
IC-IL

IR
(c)
V
(d)
Fig. 6.4: Examples of a phasor diagram
In a series circuit we usually draw the current I parallel to the phase-reference axis. The
voltage VR across R is given by VR=IR, which is parallel to I. The voltage across the
capacitor is given by VC =IZC=I/jC=
I  j 900
e
, which is perpendicular to I. VC points
C
downward, since it has a phase of –900 relative to I. Hence the phasor diagram in Figure
6.4(b) showing V=VR+VC. Note that the phase angle  between I and V is given by the
angle of the impedance Z=R+ZC=R+1/jC=R-j/C. That is, =arctan(-1/CR)=arctan(1/CR).
56
The phasor diagram in Figure 6.4(b) can be drawn on a scale diagram by using the
magnitudes of the complex amplitudes.
2. A sinusoidal voltage V (t )  Vˆ sin t is connected across a parallel combination of a
resistor R, a capacitor C and an inductor L, as shown in Figure 6.4(c).
The quantities V, I, IR, IC, IL refer to complex amplitudes. In a parallel circuit we
usually draw the voltage across the parallel components parallel to the phase-reference
axis. Hence we draw V horizontal. We determine the currents IR, IC and IL using Ohm’s
law:
IR=V/R
0
IC=V/ZC=jCV=CV e j 90
IC=V/ZL=V/jL=
V  j 900
e
L
We see that IR is parallel to V, IC points upward perpendicular to V, and IL points
downward perpendicular to V. Figure 6.4(d) shows a possible phasor diagram for the case
that I C  I L (or 2LC>1). Note that the phase  between V and I is given by the angle
of the admittance of the parallel combination of R, C and L. The admittance is given by
Y
1
1
1


R ZC Z L
=
1
1
 jC 
R
jL
=
1
1 

 j  C 

R
L 

Therefore
1 

tan   C 
R
L 

57
or


  arctan C 
1  
R .
L  
Power
If the voltage across a component is V (t )  Vˆ cos(t   V ) and the current through it is
i(t )  Iˆ cos(t   i ) , then the instantaneous power in the component is given by
p(t )  V (t )i(t )  VˆIˆ cos(t  V ) cos(t   i )
We make use of the mathematical formula, CosACosB 
1
Cos( A  B)  Cos( A  B) , to
2
get
1
1
p(t )  VˆIˆ cos( V   i )  VˆIˆ cos(2t   V   i )
2
2
The first term on the right hand side is a constant and the second term is a sinusoidal
wave of frequency 2. Since the average value of any sinusoidal signal over its period (or
more periods) is zero, we get the average power as
1
P  p(t )  VˆIˆ cos 
2
(6.1)
where =v-I is called the phase difference between the current and the voltage.
Since Vrms  Vˆ / 2 and I rms  Iˆ / 2 , we can also write the average power as
P  Vrms I rms cos 
(6.2)
The factor cos is called the power factor of the device. It is the cosine of the angle
between the voltage across the device and the current through it. The power factor ranges
58
from 0 for a purely reactive circuit, to 1 for a purely resistive circuit. A power factor less
than 1 indicates some component of reactive current.
If we let V and I be the complex amplitudes, we can write in general the complex power
S as
1
S  VI *  P  jQ
2
P is a real quantity, the power dissipated in a resistor, and Q is imaginary, it is the power
stored in a reactive component (also called blind or virtual power). If a current I flows
through an impedance Z due to a potential difference V, we can use Ohm’s law to write:
V  IZ  I z e j
2
Therefore
We see that
V
VV *
2
VI 

e j and V * I  Z I * Ie  j  I Z e  j .
 j
Z
Ze
*
   ReV I  
Re VI
*
*
V
Z
2
cos   I Z cos  . Therefore we can
2
also write the average power P as
1

1

P  Re VI *   Re V * I 
2

2

(6.3)
Although P is what we pay for, for domestic use, industries pay according to the power
factor.
Example
Consider an ac voltage source connected across a series combination of a resistor R and a
capacitor C. The impedance of the circuit is given by Z=R+XC=R+1/jC=R-j/C.
therefore we can write P and Q as
59
1

1

1 2  1 2
P  Re VI *   Re IZI *   Re I Z   I R
2

2

2
 2
2
1 I
1

1

1 2 
Q  Im VI *   Im IZI *   Im I Z   
2 C
2

2

2

The power factor is given by
cos  
P
P

.
S
VI
Transients
Transient (or transitory) means lasting for only a short time. Transients are currents or
voltages which last for only a short time. They usually arise from sudden changes in the
circuit conditions, e.g. when a voltage source in a network is switched either ON or OFF.
We shall treat the topic by means of examples.
Example 1
Consider a battery of emf VB connected via a switch to a series combination of a resistor
R and a capacitor C, as shown in Figure 6.5.
S
R
i
VB
C
Fig. 6.5
60
VC
Suppose that at time t=0 the switch S is closed. Let us also assume that at t=0 the
capacitor is energy-free, that is, the voltage VC across the capacitor is zero. How will VC
and i behave after the switch is closed?
To answer the above question, we analyse the circuit in Figure 6.5 by writing down the
loop equation after the switch is closed.
Ri+VC=VB
If we substitute for i  C
dVC
, we obtain for VC a first-order differential equation with
dt
constant coefficients:
dVC
V
1

VC  B
dt
RC
RC
(6.4)
There several methods for solving this differential equation (d.e.). For example the
method of separation of variables gives:
t
dVC
1

0 VB  VC RC 0 dt 
VC
ln VB  VC  0
VC
t

RC

VC (t )  VB 1  e t / RC
The current is then obtained from i  C
t
0

dVC
:
dt
61
(6.5)
i(t )  i0 e t / RC
(6.6)
where i0=VB/R. Figure 6.6 shows the sketch graphs for VC(t) and i(t).
VC(t)
i(t)
VB
0
i0
RC
t
(a)
0
RC
t
(b)
Fig. 6.6: Voltage and current of a charging capacitor
The graphs show an exponential growth for VC and an exponential decay for i. The rate
of growth or decay is determined by the time constant of the circuit =RC. The smaller
the time constant the faster the growth or decay. As a general rule the voltage across a
capacitor growth exponentially according to equation (6.5). If we can write the d.e. in the
form of equation (6.4) we can easily identify the time constant, and therefore be able to
write down the exponential growth using equation (6.5). We also note that at t=0 the
current is maximum, and is given by i0=VB/R. Thus the capacitor behaves like a shortcircuit at t=0.
Let us now suppose that the switch S in Figure 6.5 has been closed for a “long time,” say
t0. Then if the switch is opened at t= t0, the differential equation (6.4) becomes
dVC
1

VC  0
dt
RC
62
(6.7)
Remember that the switch had been closed for a long time [after a long time both voltage
and current of the capacitor have reached their end or terminal values, see Figure 6.6], so
that at t= t0, VC=VB. We use this condition to solve the above homogeneous d.e. and get:
VC (t )  VB e t / RC
(6.8)
and
i(t )  C
dVC
 i0 e t / RC
dt
(6.9)
where i0=VB/R. Figure 6.7 shows the sketch graphs for VC(t) and i(t). Notice the negative
spike (pulse) at t= t0.
VC(t)
i(t)
VB
t0
t
-i0
t0
t
(a)
(b)
Fig. 6.7: Voltage and current of a discharging capacitor
Example 2
Suppose we replace the capacitor in Figure 6.5 with an inductor of inductance L. Let us
assume that the inductor is energy-free at t=0, when the switch is closed. This means that
the current through the inductor is zero at t=0. Noting that the voltage across the inductor
63
is given by VL  L
di
, where i is the current in the inductor, we can write down the loop
dt
equation as:
iR  L
di
 VB
dt
or
V
di R
 i B
dt L
L
(6.10)
This d.e. is similar to equation (6.4). Therefore its solution can be obtained in the same
way we obtained equation (6.5), In equation (6.4) the time constant is equal to the
reciprocal of the coefficient of VC. Similarly the time constant in equation (6.8) must
equal to the reciprocal of the coefficient of the current i, that is, =L/R. Therefore the
solution to equation (8.8) is:

i(t )  i0 1  e  Rt / LC

(6.11)
where i0=VB/R is the maximum (or end-value) current. We can find the voltage VL across
the inductor using VL  L
di
.
dt
VL (t )  VB e  Rt / L
(6.12)
Figure 6.8 shows the sketch graphs for i(t) and VL(t).
i(t)
VL(t)
i0
0
VB
L/R
t
(b)
0
L/R
t
(b)
64
Fig. 6.8: Voltage and current of an inductor energized by a battery of voltage VB.
We note that the current through an inductor grows exponentially while the voltage
across it decays exponentially. In particular, at time t=0 the current is zero but the voltage
across the inductor is equal to the emf of the battery. This means that at t=0, the inductor
behaves like an open-circuit (i.e. no current flowing) with all the emf of the battery
appearing across the inductor.
If after along time t=t0 the switch is opened, the behaviour of the circuit is described by
the homogeneous d.e.
di R
 i0
dt L
(6.13)
Again the solution of this equation is similar to that of equation (6.6), and we get:
i(t )  i0 e  Rt / L
(6.14)
VL (t )  VB e  Rt / L
(6.15)
where i0=VB/R. Figure 6.9 shows the sketch graphs for i(t) and VL(t).
i(t)
VL(t)
i0
t0
t
-VB
t0
t
(a)
(b)
Fig. 6.9: Voltage and current of an inductor de-energized from a battery of voltage VB.
65
Questions
1. Determine the mean V , the mean absolute value V
and the rms-value Vrms, of
the ac voltages in Figures 6.10(a), (b) and (c). Assume that all the waveforms
have the same frequency.
Vˆ
+ Vˆ
0
- Vˆ
(a)
(b)
+ Vˆ
- Vˆ
(c)
Fig. 6.10
2. An ac voltage source of frequency 50Hz and rms-voltage 240V is connected
across a series combination of a resistor R=100 and an inductor L=100mH.
(a) Draw the circuit and sketch a phasor diagram of the circuit.
(b) Use the method of complex amplitudes to determine the voltage VL(t) across
the inductor. What is the amplitude of VL(t)?
(c) Find the power consumed in the circuit and the power factor of the
circuit.
3. Prove that a circuit whose current is 900 out of phase with the driving voltage
consumes no power, averaged over an entire cycle.
66
4. Determine the average voltage of:
(a) a half-wave rectified voltage,
(b) a full-wave rectified wave.
5. (a) What happens to: (i) the voltage across a capacitor, (ii) the current through the
capacitor, when a voltage V0 is connected across the capacitor?
(b) What happens when the dc voltage supply is disconnected?
(c) Repeat parts (a) and (b) for an inductor.
6. A dc voltage source of emf V0 and internal resistance r is connected across a
parallel combination of a resistor R and a capacitor C.
(a) Draw the circuit diagram.
(b) Find a differential equation (d.e.) for the voltage across the capacitor.
What is the time constant of the circuit?
(c) Find a solution for the d.e. in (b) (assume that the capacitor was energyfree at the time the voltage source was connected to it).
(d) Sketch the voltage VC across the capacitor, the voltage Vr across the
internal resistance, and the currents iC, iR and i through C, R and r
respectively.
Further Reading
Seeti, M.L.: Basic Electronics; Makerere 2003.
67
LECTURE 7
THEREE-PHASE POWER SUPPLY
Introduction
Although it is possible to generate a power system of any number of phases (polyphase),
the three phase system is the most common, conventional method of power generation.
Virtually all the generators of electricity throughout the world are three phase
synchronous generators. Synchronous means that when the generators are connected to a
single system they must rotate at exactly the same speed.
In this lecture we introduce the reader to the terminology used in power generation and
transmission, and in electrical machines. The star and delta load configurations for threephase loads will be discussed and simplified examples worked out.
Objectives
By the end of this lecture, you should be able to:

Explain what is meant by a three-phase power system;

Draw a phasor diagram of the three phase voltages;

Determine the relationship between phase and line voltages for a Y-connected
load;

Determine the relationship between phase and line voltages for a -connected
load;

Calculate the power developed in a Y-connected load and in a -connected load;

Differentiate between a three-phase four-wire system and a three-phase five-wire
systems;

Give examples of loads.
Three phase system
Figure 7.1(a) shows a circuit of three voltage sources V1 V2 and V3, of the same angular
frequency , connected over impedances Z1, Z2 and Z3 to a common impedance Z0.
68
V3
I1
Z1
I2
Z2
I3
Z3
I0
Z0
1200
-1200
V0
V1
V1
V2
V3
V2
(a)
(b)
Fig. 7.1: Basic circuit of a three phase system.
Since I1 + I2 + I3 = I0 = Y0V0 and Ik=Yk(Vk-V0), for k=1,2,3, we get for the voltage V0
across Z0:
3
V0 
Y V
k 1
3
k
k
(7.1)
Y
l 0
l
where Ym=1/Zm is the admittance.
Suppose now that all the voltages V1 V2 and V3 have the same amplitude Vˆ but only
differ in phase in a symmetrical manner such that
0
0
V1  Vˆ , V2  Vˆe  j120 , V3  Vˆe  j 240 .
Suppose also that all the impedances Zk (or admittances Yk) are equal. Then we can in
general write:
0
Vk  Vˆe  j ( k 1)120
(7.2)
Yk  Y , k  1,2,3
(7.3)
69
Figure 7.1(b) shows a phasor diagram of the phase voltages Vk. The condition in equation
7.3 is that of a symmetrical or balanced load. Equation 7.1 now gives V0 as
3
V0 
Y  Vk
k 1
Y0  3Y
Let us evaluate the sum of the phase voltages in the numerator of the above expression:
3
3
k 1
k 1

0
0
0
Vk  Vˆ  e  j (k 1)120 = Vˆ 1  e  j120  e  j 240


 

0
0
1

= Vˆ 1  e  j120  e j120 = Vˆ 1  2 cos 120 0 = Vˆ 1  2   =0
2

Hence V0=0 and I0=0, independent of Y0. This means that for a balanced load (i.e. Yk=Y,
for k=,2,3) the current I0 in the neutral line is equal to zero. This means that the neutral
line is unnecessary for a balanced load. However, the neutral line is necessary for a
lighting load because a balanced load is not possible all the time. A balanced load may
only be possible in factories using electric motors.
Instead of the diagram in Figure 7.1(a) the usual or conventional way of representing a
three phase system is shown in Figure 7.2. The two circuit diagrams are equivalent.
Instead of V1, V2 and V3 these phase voltages are named VR, VY and VB, respectively,
and the corresponding impedances are ZR, ZY and ZB. These could represent the line and
load impedances together. The subscripts R, Y and B refer to the Red, Yellow and Blue
phases, as they are conventionally called.
70
I1
VR
R
V0
ZR
I0
VB
VY
Z0
ZB
I2
ZY
B
Y
I3
Fig. 7.2: Conventional circuit diagram of a 3-phase system
To find the relationship between the phase voltages and the line voltages, we draw a
phasor diagram for the phase voltages as shown in Figure 7.3(a).
VB
VBR
VRY
300
1200
-VY
Vline
0
30
VR
300
VY
Vphase
300
1200
Vphase
VYB
(a)
(b)
Fig. 7.3: Diagram showing; (a) the phase voltages VR, VY and VB, and the line voltages
VRY=VR-VY, VYB=VY-VB and VBR=VB-VR, (b) the relationship between the
magnitudes Vphase and Vline
71
We note the line voltages VRY, VYB and VBR all have the same magnitude (lie on a circle
in Figure 7.3) since the phase voltages have the same magnitude. Thus
VR  VY  VB  V phase and VRY  VYB  VBR  Vline . Figure 7.3(b) shows one of the
triangle of phasors, which is an isosceles triangle. To find the relationship between the
phase and line voltage magnitudes we use, for example, the cosine rule which gives the
relationships:
For Y-connected balanced load:
Vline  3  V phase
I line  I phase
The relationship between the currents is evident from Figure 7.3(a) since the current from
the generator is the same as the current through the load (e.g., IR=I1 flows through ZR).
The above results apply equally to a circuit with a neutral line (Z0) as well as to a circuit
without a neutral line.
Delta-connected load
Figure 7.4 shows a delta-connected load of impedances ZR, ZY and ZB.
R
IR
VR
IRY
ZB
VB
VY
ZR
IBR
B
Y
IY
ZY
IB
Fig. 7.4: Delta-connected load
72
IYB
There is no neutral line and there is no need here to distinguish between line and phase
voltages, since the voltage of each load phase is simply the voltage difference of two
phase voltages. Therefore we have that Vline=Vphase.
Here the currents IR, IY and IB are the line currents while the currents IRY, IYB and IBR are
phase currents. If Iline and Iphase are the magnitudes of the line and phase currents, then we
have that
I RY  I YB  I BR  I phase and
I R  I YB  I BR  I line . To find the
relationship between Iline and Iphase we note that
I RY  VR  VY YR  VRY YR
I YB  VB  VY YY  VBY YY
I BR  VB  VR YB  VBR YB
Now we know how to draw the phasors for VRY=VR-VY, VYB=VY-VB and VBR=VB-VR,
see Figure 7.3(a). If we write the impedance Z as Z  Z e j , assuming asymmetrical load
ZR=ZY=ZB=Z, then Y  Y e  j . Therefore we can write
I RY  VRY Y e  j
I YB  VBY Y e  j
I BR  VBR Y e  j
We see that there is a phase difference equal to  between the voltage across the load
phase and the current through it. This is illustrated in Figure 7.5.
73
IB
IYB
VBR
VRY
IBR

IRY

IBR

IR
IYB
IY
IRY
VBY
Fig. 7.5: Phasor diagram for the delta connected load under a symmetrical load
From the phasor diagram in Figure 7.5 we can use the cosine rule to obtain the
relationship between Iline and Iphase. The isosceles triangle with sides Iphase, Iphase and Iline,
and angles 300, 300 and 1200 gives, together with the previous result:
74
For -connected balanced load:
Vline  V phase
I line  3  I phase
Power in a balanced load
Let us consider the power in a balanced three phase system. If we let VR  VY  VB  Vˆ
and I  VY  Iˆ , then we can write for the phase voltages, currents and power:
Vk (t )  Vˆ cos[t  V  (k  1)120 0 ]
ik (t )  Iˆ cos[t  i  (k  1)120 0 ]
pk (t )  Vk (t )ik (t )
Substituting for Vk(t) and ik(t) the instantaneous power becomes:
1
p k (t )  VˆIˆ[cos(V  i )  cos(2t  V  i  2(k  1)120 0 ]
2
The total power delivered by the source is then given by
3
3
p(t )   p k (t )  VˆIˆ cos(V  i )
2
k 1
But this is a constant. This means that the total power delivered y all the sources is a
constant in contrast to the power pk(t) delivered by a single source. This result is of a
major practical importance, because the rotating generators used for the production of
75
electrical energy are moved by a common drive which, according to the above condition,
is under constant power.
The active power of a single phase is given by V phaseI phase cos  , where  is the phase
angle between the voltage and current. The active power of the system is then the sum of
the active powers of the phases.
P  3V ph I ph cos 
To express the above result in terms of line voltage and line current, we note that for Yload Vline  3  V phase and Iline=Iph, but for a -load I line  3  I phase and Vline=Vph. Thus
in both cases V ph I ph  Vline I line / 3 . Thus we also have for the active power
P  3Vline I line cos 
Loads
High voltage distribution to primary substations is used by the electricity supply
companies to supply small industrial, commercial and domestic consumers. The final
connections to plant, distribution boards, commercial or domestic loads are usually by
simple underground radial feeders at 415V/240V. The 415V/240V is derived from the
11kV/415V substation transformer by connecting the secondary winding in star. The star
point is earthed to an earth electrode sunk into the ground below the substation, and from
this point is taken the fourth conductor, the neutral(N). A three phase four wire supply
gives a consumer the choice of a 415V three phase supply and a 240V single phase
supply. Loads connected between phases are fed at 415V, and those fed between one
phase and neutral at 240V. A three phase 415V supply is used for supplying small
industrial and commercial loads such as garages, schools and blocks of flats. A single
phase 240V supply is usually provided for individual domestic consumers. Figure 7.6
shows a three phase four wire distribution with different types of loads.
76
R
Y
B
N
240V Single
415 Single
415V Three
phase load
phase load
phase load
e.g. lighting
e.g. welder
e.g. motor
415V Three phase
+ neutral load
e.g. motor
Fig. 7.6: Three phase four wire distribution with different types of loads
Generation, transmission and distribution
After the power has been generated the voltage is stepped up before transmission to
distant locations, and before the power is distributed to consumers the voltage must be
stepped down. Figure 7.7 illustrates how electrical energy is transmitted and distributed
after generation.
77
Generation
Transmission on
Primary distribution
25kV
supergrid at
to substations at
400kV and 275kV
11kV
Small industrial and
Domestic consumers at
415V/240V
Fig. 7.7: Generation, transmission and distribution of electrical energy
Three phase four wire distribution
R
R
11kV
415V
B
Y
Y
B
N
Fig. 7.8: Configuration of a three phase four wire distribution system
78
Three phase five wire system
In a three phase five wire system there separate neutral (N) and protective conductor (E).
Secondary
R
supply
transformer
Y
B
N
Supply earth
E
electrode
L N
E
R
Y
B
N
E
Exposed metal parts
Consumer installation
Fig. 7.9: Configuration of a three phase five wire distribution system; the
neutral(N) and the protective(E) conductors may be combined
into a single conductor.
Questions
1. (a) Why is ‘balancing’ of loads in a three phase supply desirable?
(b) What are the advantages of using a three phase four wire supply to industrial
premises instead of a single phase supply?
2. A three phase supply with the phase voltages VR  VY  VB  Vˆ and VY  aVR ,
VB  aVY , where a  e  j120 , and angular frequency , feeds a star-connected
0
load as shown in Figure 7.10.
79
I1
R
V0
Z1
V1
I0
N
Z0
Z3
V2
V3
Z2
I2
Y
I3
B
Fig. 7.10
Assuming that Y1=G, Y2=jC with C=G, Y3=1/jL with 1/L=G, determine the
voltages V1, V2 and V3, and the currents I0, I1, I2 and I3, for the following cases:
(a) Y0=0 (no neutral line),
(b) Y0=G,
(c) Y0=
[Ans: In general V0 
(1  3 )GVˆ
:
G  Y0




1
1
(a) I0=0, I1   3GVˆ , I 2  GVˆ 3  j (3  2 3 ) , I 3  GVˆ 3  j (3  2 3 ) ,
2
2


V0  1  3 Vˆ ,





1
V2   Vˆ 3  2 3  j 3 ,
2
V1   3Vˆ ,

1
V3  Vˆ  3  2 3  j 3 .
2
(b) I 0 
I3 


1 ˆ
GV 1  3 ,
2



1
I 1   GVˆ 3  1 ,
2

1 ˆ
GV 3  j (2  3 ) ,
2
80
I2 
1 ˆ
GV 3  j (2  3 ) ,
2



1
V0  Vˆ 1  3 ,
2


1
V1   Vˆ 3  1 ,
2


1
V2   Vˆ 2  3  j 3 ,
2

1
V3  Vˆ  2  3  j 3 .
2






1
1
(c) I1  GVˆ , I 2  GVˆ 3  j , I 3  GVˆ 3  j , I 0  I1  I 2  I 3  GVˆ 1  3 ,
2
2




1
1
V0  0 , V1  Vˆ , V2   Vˆ 1  j 3 , V3  Vˆ  1  j 3 ].
2
2
3. A three phase motor with a balanced load is connected to a symmetrical three phase
generator as shown in Figure 7.11
I1
R
VR
Y
V0
VB
VY
Y
Y
I2
Y
I3
B
Fig. 7.11
Given that:
Y
0
1
(1  j ) -1; VR  Vˆ  240 2 V, VY  a 2VR , VB  aVR , a  e j120 ,
40
(a) Calculate the mechanical power developed by the motor assuming that all the
electrical energy is converted into mechanical energy. [Ans: 4.32 kW]
(b) How big are the currents I 1 , I 2 , I 3 in the individual coils of the motor?
[Ans: V0=0, I1  I 2  I 3  12 A]
81
(c) During the operation of the motor, phase R of the generator fails, i.e., VR=0,
and the motor is run on only two phases. Repeat parts (a) and (b).
[Ans: (a) 4.32 kW, (b) V0  Vˆ , I1  I 2  I 3  12 A]
4. A three phase motor with the following data: Vˆ  240 V, cos=0.866,
Z  R  jL  100 , is connected to a 240V/50Hz three phase generator. The
phases of the motor are connected in a star. It is assumed that the three phases of the
motor are exactly identical and each phase consists of windings of inductance L
together with a resistance R in series. R is responsible for the transformation of
electrical energy into mechanical energy.
(a) Draw the circuit diagram.
(b) Deduce the values of L and R from the given data of the motor. [Ans:
R=86.6, L=1/2159mH]
(c) What power does the motor deliver to the axle if the efficiency of the
motor if 79.5%? [Efficiency is equal to mechanical energy divided by
electrical energy]. [Ans: P1189.7W]
(d) Due to a failure of two phases of the generator, the motor is connected to a
240V/50Hz single phase generator by use of an auxiliary capacitor
C=50F connected as shown in Figure 7.12.
V1
V3
VR
Z
C
VR= Vˆ = 240 2 V
Z
Z
V2
Fig. 7.12
(i) Calculate the voltages V1, V2 and V3 across the windings of the motor.
82
Assume that Z  Z e j 30 . [Hint: The expected values for V2 and V3 are
0
given approximately by V2  256e j 213 and V3  186e j132 . In case
0
0
you don’t get these values, assume them for the rest of the problem].
(ii) If the efficiency is now 73%, calculate the mechanical power of the
motor and compare your result with that obtained in part (c).
[Ans: Pmech679.8W (about 43% decrease)]
Further Reading
Seeti, M.L.: Basic Electronics; Makerere 2003.
83
LECTURE 8
SEMICONDUCTORS
Introduction
In this lecture we first present a brief discussion of the band theory of solids, after which
we discuss semiconductors. The difference between semiconductors and insulators is
made very clear and doping to make p-type and n-type semiconductors is discussed. The
pn-junction is quantitatively discussed with help of sketch graphs. Finally the biasing of a
pn-junction is described and explained, and the diode equation is presented.
Objectives
By the end of this lecture, you should be able to:

Explain the difference between insulators, semiconductors and conductors using
the band theory of solids; explain how p-type and n-type semiconductors can be
made;

Explain how the depletion region of a pn-junction is formed;

Calculate the electric field in the depletion region;

Explain why the flow of current through a junction diode, when a voltage is
connected across it, is unidirectional;

Write down the diode equation and use it to explain the current-voltage
characteristic of a junction diode.
Introduction to the band theory of solids
It is believed that an atom consists of a nucleus surrounded by orbiting electrons. That is,
the electrons in an atom can be imagined as occupying orbitals that surround the nucleus.
Each of the electrons in the atom has a potential energy by virtue of its proximity to both
the positively charged nucleus and the other negatively charged electrons. The allowed
values of energy are quantized and are called energy levels. Each energy level can
accommodate two electrons in what are called quantum states (or the states of that energy
level). The two states in each energy level can be populated, in accordance with Pauli’s
exclusion principle from quantum mechanics, by two electrons, provided that these
electrons have opposite spins.
84
For a system of a large number of identical atoms, because of the electrical interactions
and the exclusion principle, the wave functions get distorted, especially those of the outer
electrons (usually referred to as valence electrons). The energy levels also shift somehow;
some move upward and some downward, depending on the environment of each
individual atom. Each valence electron state for the system splits into an energy band
containing a large number of closely spaced energy levels. Ordinarily the number of
atoms is very large, of the order of Avogadro’s number (1023), so the levels can be
thought of as forming a continuous distribution of energies within a band. Between
adjacent energy bands are gaps or forbidden regions where there are no allowed energy
levels. The inner electrons in an atom are affected much less by nearby atoms than the
valence electrons. Insulators, conductors and semiconductors have different energy band
structures, as illustrated in Figure 8.1. That is, every solid has its own characteristic
energy band structure.
CB
CB
CB
FB
FB
FB
VB
VB
(a) Insulator
VB
(b) Semiconductor
(c) Conductor
Fig. 8.1: Energy band structure of a solid; CB=Conduction Band, FB=Forbidden
Band, VB=Valence Band. The small circles in the VB represent a filled
region with free electrons.
85
In an insulator a completely full band (valence band VB) is separated by a gap (forbidden
band FB) of several electron volts (order of 1 to 5 eV) from a completely empty band
(conduction band CB), and electrons in the full valence band cannot move. At finite
temperatures a few electrons can reach the upper conduction band.
In a semiconductor a completely filled valence band is separated by a smaller gap
(forbidden band FB), and electrons in the valence band are free to move when an electric
field is applied.
The basic difference between semiconductors and insulators is only the size of the band
gap (forbidden band). At some temperature above absolute zero the crystal lattice has
some vibrational motion, and there is some probability that an electron can gain enough
energy from thermal motion to jump to the conduction band. Once in the conduction
band, an electron is free to move in response to an applied electric field because there are
plenty of nearby empty states available. There are always a few electrons in the
conduction band, so no material is a perfect insulator. Furthermore, as the temperature
increases, the population in the conduction band increases very rapidly.
Semiconductors
A semiconductor has an electrical conductivity that is intermediate between those of good
conductors and those of good insulators. The group IV elements (refer to the periodic
table of elements) silicon(Si) and germanium(Ge) are the most common semiconductor
elements used. They both have four electrons in the outermost electron subshell (valence
shell). All the valence electrons are involved in the bonding, and the materials should be
insulators. However, an unusually small amount of energy is needed to break one of the
bonds and set an electron free to roam around the lattice. This energy corresponds to the
energy gap, Eg, between the valence and conduction bands in Figure 8.1. Eg is about
1.1eV for silicon and 0.7eV for germanium. Thus even at room temperature a substantial
number of electrons is dissociated from their parent atoms, and this number increases
rapidly with temperature.
86
Furthermore, when an electron is removed from a covalent bond, it leaves a vacancy. An
electron from a neighboring atom can drop into this vacancy, leaving the neighbor with
the vacancy. In this way the vacancy, called a hole, can travel through the lattice and
serve as an additional current carrier. A hole behaves like appositively charged particle.
In a pure semiconductor, holes and electrons are always present in equal numbers; the
resulting conductivity is called intrinsic conductivity to distinguish it from conductivity
due to impurities.
Doping
Doping is the deliberate addition of impurity elements to semiconductor elements. The
impurity elements are usually from group III or group V elements of the periodic table.
Suppose a small amount of a group V element like arsenic(As) is added to germanium.
Arsenic has five valence electrons and germanium has four. When one of the arsenic
valence electrons is removed, the remaining electron structure is essentially that of
germanium. An arsenic atom can comfortably take the place of a germanium atom in the
lattice. Four of the arsenic atom’s five valence electrons form the necessary covalent
bonds with the nearest neighbors. The fifth valence electron is very loosely bound. Even
at ordinary temperatures this electron can very easily gain enough energy to climb into
the conduction band, where it is free to wonder through the lattice. A small concentration
of arsenic atoms into germanium can increase the conductivity so drastically that
conduction due to impurities becomes by far the dominant mechanism. In this case the
conductivity is due almost entirely to negatively charged carriers (electrons). The
material is called an n-type semiconductor.
Adding atoms from an element in group III, e.g. gallium(Ga), with only three valence
electrons, has an analogous effect. The gallium atom would like to form four covalent
bonds, but it has only three outer electrons. It can, however, steal an electron from a
neighboring germanium atom to complete the bonding. This leaves the neighboring atom
with a hole, or missing electron, and this hole can then move through the lattice just as in
intrinsic conductivity. In this case the conductivity is due almost entirely to holes. The
material is called a p-type semiconductor.
87
The two types of impurities, n and p, are called donors and acceptors respectively.
pn-junction
A pn-junction if formed hen a p-type material and an n-type material are brought into
contact, as illustrated in Figure 8.2(a). In the p-type region the concentration of holes (the
majority carriers) is much greater than the concentration of holes (the minority carriers)
in the n-type region just to the right of the junction. This concentration gradient provides
the driving force for the diffusion of holes to the right. Similarly there is a diffusion of
electrons to the left. In thermal equilibrium a negative space charge accumulates to the
left of the junction and an equal but positive charge accumulates to the right of the
junction. The two regions, one depleted of holes and the other of electrons, are
collectively called the depletion region as shown in Figure 8.2(b). Due to the presence of
uncompensated donor and acceptor ions, an electric field E builds up, as shown in Figure
8.2(d).
The charge density is equal to –qNA to the left of the junction and equal to +qND to the
right of the junction within the depletion region, where NA and ND are the concentrations
of acceptor and donor impurities respectively. The electric field E can be computed using
Gauss’ law,   E   /  , in one dimension:
dE 

dx 
(8.1)
We first note that the charge density  is given by
=-q(NA+n), for -xp<x<0
=+q(ND+p), for 0<x<xn
88
where xp and xn are the extensions of the depletion region into the p- and n-regions from
the pn-junction. If we assume that both n and p are negligible compared to either N A or
ND (depletion approximation), then we have approximately that:
=-qNA,
for -xp<x<0
(8.2)
=+qND,
for 0<x<xn
(8.3)
Therefore the electric field can be determined using the relationship E ( x) 
E ( x) 
 qN A
E ( x) 
 qN D


1

 dx :
x  x ,
for -xp<x<0
(8.4)
x  xn  ,
for 0<x<xn
(8.5)
p
For continuity the two fields must be equal at x=0. The potential V(x) in the depletion
region can be computed from the electric field by using the relation E  dV / dx .
The pn-junction together with metal contacts at the two ends constitute a junction diode.
The amount of current through the device when an external electric field is applied
depends on how the device is biased. In the forward bias an externally applied voltage
acts in opposition to the contact potential (due to the electric field in the depletion region)
and lowers the net potential at the junction. Electrons enter the n-side through the cathode
lead, and as majority carriers in the n-side, drift towards the junction. Because the
potential barrier at the junction is lowered by the forward bias, electrons cross the
junction and, as majority carriers in the p-side, diffuse, towards the anode lead. At the
same time, hoes created at the anode lead by the liberation of bound electrons, drift
through the p-side, cross the junction, and as majority carriers in the n-side, diffuse
toward the cathode lead. At the cathode these holes are filled by electrons from the
89
external wiring. The rather high forward current observed is due to the motion of majority
carriers, which by definition are large in number, so that a large number of charge carriers
should cause a high current. Another consequence of applying a forward bias is the
narrowing of the depletion region.
When the pn-junction is reverse biased, the externally applied voltage acts in the same
direction as the contact potential, thus increasing the net potential barrier across the
depletion region, while at the same time widening the depletion region itself. The external
voltage causes holes in the n-side and electrons in the p-side to move in the direction of
the junction. However, holes in n-type material and electrons in p-type material are both
minority carriers. The resulting current is of necessity very low because minority carriers
are by definition low in numbers.
The diode equation
The current in a diode can be approximated by the diode equation:


I  I 0 eV / VT  1
(8.6)
where I0 is the reverse saturation current which is highly temperature dependent. It also
depends on the doping levels of the p- and n-regions and the geometry of the junction. V
is the biasing applied voltage and VT=kT/q is the temperature-voltage equivalent
(k=Boltzmann’s constant, T=absolute temperature, q=electronic charge). I0 is of the order
of 10-6A for germanium diodes and 10-9A for silicon diodes.
90
(a)
p
n
Depletion region
+
(b)
p
+ +
n
+
Layer of negative ions
Layer of positive ions
(depleted of holes)
(depleted of electrons)

(c)
+qND
-xp
xn
x
xn
x
-qNA
(d)
-xp
91
E
(e)
V
Vn
-xp
xn
x
Vp
Fig. 8.2: (a) pn-junction, (b) Space charge, (c) Charge density, (d) Electric field,
(e) Electric potential
For forward bias, V is positive and V>>VT. Note that VT26mV at room temperature.
Therefore for forward bias we can approximate the current to I  I 0 eV / VT . For reverse
bias, V is negative so that eV / VT  1 , and the current can be approximated to I=I0. Figure
8.3 shows a graph of the diode equation.
I
V
I0
Fig. 8.3: Characteristic of a diode using the diode equation
92
Questions
3. (a) What is mechanism by which conduction takes place inside a semiconductor?
(b) What is energy gap? How can conductors, insulators and semiconductors be
characterized on the basis of the energy gap?
4. Give examples of semiconductors. Why are these materials classified as
semiconductors?
5. Describe the dynamics of the formation of the depletion region.
6. What factors affect the reverse saturation current in a diode? What order of
magnitude is the reverse saturation current at room temperature in silicon or
germanium?
Further Reading
Seeti, M.L.: Basic Electronics; Makerere 2003.
93
LECTURE 9
DIODES
Introduction
In this lecture we introduce the first passive nonlinear circuit device, the diode. We
discuss its current-voltage characteristics and its applications in electrical circuits.
Rectification using diodes is presented and explained. The Zener diode as a special diode
is introduced and its possible applications discussed.
Objectives
By the end of this lecture, you should be able to:

Define a diode in terms of current and electric potential;

Draw the IV-characteristic of an ordinary diode;

Write down the diode equation;

Draw the circuit of a half-wave rectifier;

Draw the circuit of a full-wave rectifier;

Explain how a half-wave rectifier works;

Explain how a full-wave bridge rectifier works.
Diodes
The diode is a two-terminal nonlinear device. Its circuit symbol is shown in Figure 9.1.
A
C
Fig. 9.1: Circuit symbol of a diode; A=anode, C=cathode
The end A is called the anode and the end C the cathode. For small diodes (i.e. small
current diodes), the size of a quarter-watt resistor, the cathode is indicated by a small
94
colored band. When a positive voltage is connected across AC, with A positive with
respect to C, the diode is said to be forward biased, otherwise it is reverse biased. Figure
9.2 shows the IV-characteristic of a diode.
In the forward direction the current starts to flow significantly at a voltage of about 0.6V
for a silicon diode (0.3V for germanium diodes), called the forward voltage drop (VD).
The current in the forward direction has a limit Imax (in mA) given by the manufacturer.
In the reverse direction the current is in the nanoampere(nA or 10-9A) range for a general
purpose diode, and therefore negligible. The reverse voltage may reach tens of volts
without spoiling the diode. But the forward voltage is usually less than 10V.
I
V
Fig. 9.2: I-V Characteristic of a diode.
Ideally we can think of a diode as a one-way conductor, which suddenly starts to conduct
at the forward voltage drop VD. Figure 9.3 shows the I-V characteristic of an ideal diode.
An ideal diode has no resistance in the forward direction (VVD) and infinitely large
resistance in the reverse direction (V<VD).
95
I
0
VD
V
Fig. 9.3: I-V characteristic of an ideal diode
Rectification
One of the simplest and most important applications of diodes is rectification. A rectifier
changes ac to dc. Figure 9.4 shows the circuit of a simple halfwave rectifier , and Figure
9.5 shows the input and output waveforms.
D
Vin
RL
Vout
Fig. 9.4: Halfwave rectifier
96
Vin
t
Vout
0
T/2
T
3T/2
2T
5T/2
t
Fig. 9.5: Input and output voltages of a halfwave rectifier
When the input voltage Vin is positive and greater than 0.6V (the forward voltage drop of
a silicon diode) the diode is forward biased and a current flows into the load resistor RL
resulting into the output voltage Vout across the load. For the second half cycle when Vin
is negative, the diode is reverse biased and no current flows through the load.
Consequently there is no output voltage. Note that if the diode were reversed (anode and
cathode interchanged) only the half cycles of the input voltage with a negative amplitude
would appear across the load as output.
If both half cycles of the input ac voltage are to appear at the output, the rectifier in
Figure 9.4 must be modified. Such a circuit would be called a fullwave rectifier, because
the complete wave (both the positive and negative half cycles) are rectified. A common
fullwave rectifier is the fullwave bridge rectifier shown in Figure 9.6. Figure 9.7 shows
the input and output waveforms of a fullwave rectifier.
97
A
D4
D1
Vin
C
D2
D3
RL
B
Vout
D
Fig. 9.6: Fullwave bridge rectifier
Vin
t
Vout
0
T/2
T
3T/2
2T
5T/2
t
Fig. 9.7: Input and output waveforms of a fullwave rectifier
98
For the positive half cycle when the voltage between AB is positive, diodes D1 and D2 are
forward biased while diodes D3 and D4 are reverse biased. Thus the current flows from A
through diode D1, via C through the load RL, and via D through diode D2, and back to the
source through B. Note that the direction of the current through the load is from C to D,
that is, C is positive and D is negative (dc output). For the negative half cycle when the
voltage between AB is negative, diodes D3 and D4 are forward biased while D1 and D2
are reverse biased. In this case current flows from B through diode D3, via C through the
load RL, D through diode D4, and back to the source through A. Also in this case the
current through the load is from C to D. hence the output voltage Vout is a dc voltage.
There are other ways of carrying out fullwave rectification. Figures 9.8 and 9.9 show two
methods using a center-tapped transformer. The circuit in Figure 9.9 produces two
separate dc power supplies, a positive one and a negative one.
Transformer
RL Vout
Vin
CT
Fig. 9.8: Fullwave rectification using a center-tapped transformer
99
Vin
+
COMMON
Fig. 9.9: Dual (or bipolar) power supply using a center-tapped transformer
Power supply filtering
The preceding rectified waveforms in Figures 9.5 and 9.7 are not good dc sources. They
are dc only in the sense that they don’t change polarity. We need a dc source which is
steady, instead of varying between zero and a peak value. If we modify the fullwave
rectifier circuit in Figure 9.6 by connecting a capacitor across the load (between terminals
C and D), we get a steadier output voltage. The capacitor is called a filtering or
smoothening capacitor.
The capacitor is charged to the peak voltage of the output in Figure 9.7. As the output
voltage falls to zero, the capacitor discharges with a time constant RLC, where C is the
capacitance of the filter capacitor. When the output voltage starts to rise again to the peak
value, and charge the capacitor to the peak value again, the capacitor has not completely
discharged. In this way the output voltage never goes to zero. The capacitor value is
chosen so that RLC>>1/fr, where fr is the ripple frequency. The ripple frequency is twice
the frequency (f=1/T) of the ac input voltage Vin, as can be seen from Figure 9.7. The
above condition ensures that a small ripple (periodic variations in voltage about the
100
steady value), by making the time constant for discharge much longer than the time
between recharging. Figure 9.10 shows the filtered output voltage.
Vout
Peak-to-peak ripple
Filtered output
Unfiltered output
0
T/2
T
3T/2
2T
t
Fig. 9.10: Filtered voltage
Zener diode
Zener (or breakdown) diodes are much like ordinary diodes except that they are
manufactured to exhibit breakdown in the reverse direction at a specific voltage. These
diodes are almost exclusively used because of their breakdown characteristics. Figure
9.11 show the circuit symbol and the I-V characteristics of a Zener diode. In the forward
direction the Zener diode behaves like an ordinary diode, but in the reverse direction the
diode suddenly starts to conduct at a voltage Vbr (or VZ), called the Zener or breakdown
voltage.
101
I
-VZ
V
Fig. 9.11: Circuit symbol and I-V characteristic of a Zener diode.
The dynamic resistance of the diode after the breakdown voltage is very small (almost
zero), and thus the I-V characteristic is almost vertical. Zener diodes can be used as
voltage regulators; the diode is connected in reverse bias so that the input voltage is
limited to the breakdown voltage of the diode.
So far we have encountered two applications of diodes, namely, rectification and voltage
regulation. Another application of a diode is the use as a switch. Diodes can be used as
switches, especially in logic circuits (see digital circuits).
Questions
7. What is a diode? Why is it called a nonlinear device?
8. Sketch the I-V characteristic of a diode.


9. Make a plot of the diode equation I  I 0 eV / VT  1 for silicon with I0=1nA. Use
0.02V increments in the voltage range –0.1 to 0.7V, and 0.1V increments in the
voltage range –2V to 0.1V. (You may take VT=26mV at room temperature.)
What is the dynamic resistance at a forward voltage of 0.65V?
102
10. Name and give examples of three applications of diodes.
11. How does a Zener diode differ from ordinary diodes? Draw the I-V characteristic
of a Zener diode.
12. A dc power supply consists of a transformer, bridge rectifier, a filter capacitor,
and a Zener diode as a voltage regulator. Draw the circuit diagram.
Further Reading
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
103
LECTURE 10
TUNED CIRCUITS AND FILTERS
Introduction
In this lecture we define a tuned or resonance circuit and discuss the series and the
parallel RLC circuits. We then define a filter and discuss the four types of filters, namely,
the lowpass, highpass, bandpass and bandreject filters, by means of examples of simple
passive RC and RLC filters. We also introduce the transfer function and frequency
response, including Bode plots.
Objectives
By the end of this lecture, you should be able to:

Define a tuned/resonant circuit;

State the applications of a resonant circuit;

Identify the characteristics peculiar to a series resonant circuit;

Identify the characteristics peculiar to a parallel resonant circuit;

Define lowpass, highpass, bandpass and bandreject filters;

Define cutoff frequency of a filter;

Draw Bode plots of a given transfer function.
.
Tuned circuits
A tuned circuit or resonant circuit is an electrical circuit consisting of a resistor (R), an
inductor (L), and a capacitor (C), connected in series or in parallel.
Tuned circuits have many applications particularly for oscillating circuits and in radio
and communication engineering. They can be used to select a certain narrow range of
frequencies from the total spectrum of ambient radio waves. For example, AM/FM radios
with analog tuners typically use an RLC circuit to tune a radio frequency. Most
commonly a variable capacitor is attached to the tuning knob, which allows one to change
the value of C in the circuit and tune to stations on different frequencies.
104
RLC circuit
An RLC circuit is a resonant or tuned circuit. It consists of a power source and a
resonator. There are two types of resonators, series LC and parallel LC. There are two
fundamental parameters that describe the behavior of RLC circuits: the resonant
frequency and the damping factor. In addition, other parameters are derived from these
two.
Resonant frequency
The undamped resonance or natural frequency of an RLC circuit is given by
f0 
0
1

2 2 LC
(10.1)
where  0  1 / LC is the resonance angular frequency. Resonance occurs when the
complex impedance becomes zero:
Z=ZL+ZC=0
where ZL=jL and ZC=1/jC=-j/C.
Damping factor
The damping factor of the circuit is given by
 
 
R
2 0 L
1
2 0 CR
(for a series RLC circuit)
(10.2)
(for a parallel RLC circuit)
(10.3)
105
Note that by substituting for  0  1 / LC we can also write the damping factor as
 
R C
1 L
for the series circuit, and  
for the parallel circuit.
2 L
2R C
For applications in oscillator circuits, it is generally desirable to make the damping factor
as small as possible, or equivalently, to increase the quality factor (Q-factor Q) as much
as possible. In practice, this requires decreasing the resistance R in the circuit to as small
as physically possible for a series circuit, and increasing R to as large a value as possible
for a parallel circuit. In this case, the RLC circuit becomes a good approximation to an
ideal LC circuit.
Derived parameters
The derived parameters include Bandwidth, Q-factor, and damped resonance frequency.
Bandwidth
The RLC circuit may be used as a bandpass or band-stop filter by replacing R with a
receiving device with the same input resistance, and the bandwidth is
R
L
(10.4a)
R
2L
(10.4b)
  2 0 
or
f  2f 0 
The bandwidth is a measure of the width of the frequency response at the two half-power
frequencies. As a result, this measure of bandwidth is sometimes called the full-width at
half-power. Since electrical power is proportional to the square of the circuit voltage (or
current), the frequency response will drop to
1
106
2
at half-power frequencies.
Q-factor
We can define the quality factor as the ratio of the power stored in the circuit at
resonance to the power lost. The power stored at resonance is either P0=Io20L or
P0=Io2/0C, and the power lost is P=I02R, where I0 is the current at resonance. This
definition produces equations (10.29) and (10.30), or
Q
0
f
 0
 f
(10.5)
Resonance damping
The damped resonance frequency derives from the natural frequency and the damping
factor. If the circuit is underdamped, meaning
 1
then we can define the damped resonance as
d  0 1   2
(10.6a)
fd  f0 1  2
(10.6b)
or
In an oscillator circuit
  1 .
As a result
 d   0 or f d  f 0
107
Circuit analysis
Figure 10.1 shows the series and the parallel RLC circuit.
Series RLC circuit
In this circuit, the three components are all in series with the voltage source. We use
Kirchhoff’s loop equation:
VR (t )  VL (t )  VC (t )  V (t )
I
R
V
L
I
C
R
L
C
V
(a)
(b)
Fig. 10.1: (a) Series RLC circuit, (b) Parallel RLC circuit
If we substitute
t
VR (t )  Ri (t ) , VL (t )  L
1
di
i( )d
, VC (t ) 
dt
C  
we get the following integral-differential equation:
t
di 1
Ri (t )  L 
i( )d  V (t )
dt C  
108
To eliminate the integral we differentiate with respect to time t, and if we also divide by
L we get a second-order differential equation (de):
d 2 i R di
1
1 dV


i(t ) 
2
L dt LC
L dt
dt
We make the substitutions
(10.7)
R
1
2
 2 ,
 0 :
L
LC
d 2i
di
1 dV
2
 2
  0 i(t ) 
2
dt
L dt
dt
(10.8)
The solution to the this de can be written as
i=ih+ip
where ih and ip are the homogeneous and particular solutions.
The roots 1 and 2 of the characteristic polynomial 2  2   0  0 are given by:
2
1, 2       2   0 2 /  2 


(10.9)
For the particular solution there three possible cases to consider:

If 1  2 ; 1, 2   , then ih  A1e 1t  A2 e 2t , where A1 and A2 are constants to
be determined.

If 1  2   , then ih   A1t  A2 e 2t .
109

If the roots are complex; 1, 2    j , then ih  et  A1 cos t  A2 sin t  .
Frequency response
To find the amplitude of the current in the series circuit we use complex amplitudes
I=V/Z, where Z is the impedance of the series combination of R, L and C:
Z  R  jL 
1
1 

 R  jL 

jC
C 

(10.10)
Therefore
I ( ) 
V
Z

V
1 

R 2   L 

C 

(10.11)
2
Noting that I (0)  0 , I ( 0 )  V / R , I ()  0 , and that V / R is the maximum
current, we can sketch the graph of the steady-state current as shown in Figure 10.2.
I ( )
0=resonance frequency
Imax
0
0

Fig. 10.2: Frequency response of the current in a series RLC circuit
110
Parallel circuit
In the parallel RLC circuit all the components are connected parallel to the current
source. We use Kirchhoff’s node equation to obtain
iR (t )  iL (t )  iC (t )  i(t )
where iR, iL and iC are currents through R, L and C respectively, and i(t) is the current
from the current source. If we substitute
t
iR (t )  V / R , i L (t ) 
1
dV
V ( )d , iC (t )  C

dt
L   
where V(t) is the voltage across the components, we get the following integraldifferential equation:
t
V (t ) 1
dV

V ( )d  C
 i(t )

R
L  
dt
Dividing through by C and differentiating with respect to t gives the following
differential equation:
d 2V
1 dV
1
1 di


V (t ) 
2
RC dt LC
C dt
dt
If we make the substitutions
(10.12)
1
1
2
 2 ,
  0 , we get:
RC
LC
d 2V
dV
1 di
2
 2
  0 V (t ) 
2
dt
C dt
dt
111
(10.13)
This differential equation is similar to that of the series circuit in equation (8), and can
therefore be solved in a similar manner.
The magnitude of the voltage V can be calculated from
V ( )  I Z  I / Y
where Y is the admittance of the parallel circuit, given by
Y
1
1
1
1 


 jC =  j  C 

R jL
R
L 

(10.14)
so that
2
Y 
1 
1 
1
1
  C 
 2 2
 =
2
2
L 
R
R
 L

 2




1
2


 0

2
(10.15)
Therefore the voltage across the parallel components is given by
V ( ) 
I
1
1
 2 2
2
R
 L





1
 2

 0

2
2
(10.16)
Noting that V (0)  0 , V ( 0 )  R I , V ()  0 , and that R I is the maximum voltage,
we can sketch the graph of the steady-state voltage as shown in Figure 10.3. Note the
similarity with the frequency response for the current in the series circuit shown in Figure
10.2.
112
V ( )
0=resonance frequency
Vmax
Vmax  R I
0
0

Fig. 10.3: Frequency response of the voltage across a parallel RLC circuit.
Filters
A filter is a circuit that allows only signal components lying in a given frequency range to
pass through it, while suppressing the signal components outside the given frequency
range. There are passive filters and active filters. Passive filters contain resistors(R),
capacitors(C) and inductors(L) only, while active filters contain active devices as well. In
this lecture we shall only discuss passive filters, and below we consider the simplest types
of filters.
Lowpass filter
A lowpass filter (LPF) is a circuit that allows only signals below a given frequency,
called the cutoff frequency, to pass through it. Figure 10.4 shows a simple RC lowpass
filter.R
Vin
C
Vout
Fig. 10.4: Simple lowpass filter
113
The output voltage Vout is taken from the capacitor. The voltage transfer function of a
circuit is defined as the ratio of the output phasor to the input phasor,
A=Vout/Vin.
If we use the potential divider rule (see Lecture3) we get
Vout 
ZC
Vin
ZC  R
where ZC=1/jC. Therefore the transfer function comes to:
A
1
1  jCR
(10.17)
This transfer function can also be written in the form
A
1
1  j /  C
(10.18)
or
A
1
1  jf / f C
(10.19)
where C=2fC=1/RC, and fC=1/2RC is the cutoff frequency (C is cutoff angular
frequency). The angle of phasor A gives the phase difference between the output Vout and
the input Vin. Therefore we can write the phase () as
 ( )   arctan( /  C )
(10.20a)
 ( f )   arctan( f / f C )
(10.20b)
or
114
The easiest way to obtain the phase of a transfer function is to find the angles of the
numerator and the denominator, from any of the equations (10.18) to (10.20), and then
subtract the angle of the denominator from the angle of the numerator. In our case the
angle of the numerator is zero, since the numerator is real, and the angle of the
denominator is given by the angle whose tangent is equal to the ratio of the imaginary
part to the real part. The magnitude A of the transfer function may written from equation
(10.18) as
A
1
1   2 / C
2
(10.21)
For a complex quantity A=N/D, the magnitude of A ca be obtained by the relation
A  N / D , and if N=NR+jNI, where NR and NI are real numbers, then
N  N R  N I , etc.
2
2
To show that A , from equation (10.21), represents a LPF, we draw a sketch graph of A .
To do this we consider three cases:

Case1:    C
This means that


 1 , so that A 1.
C
Case 2:    C
This gives
2
1
 1 , so that A 
 0.71
2
C
2

Case 3:    C

This means that


 1 , so that A  C . This the inverse relation with

C
A tending to zero very fast as  becomes large (compared to C).
115
The resulting sketch of A against  is shown in Figure 10.5. To sketch the phase (),
given by equation (10.19a), we note that

(0)=0,

(C)=-450,

()=-900
We further note that g ( ) 

d
d
arctan x   1 2 . We see that
 2 C 2 , since
d    C
dx
1 x
g (0)  0 , but g ()  0 . This simply means that the take-off of the curve for () is not
flat at the origin, but it approaches zero asymptotically for large values of the frequency
. The phase is also shown in Figure 10.5.
A( )
1
1/ 2
0
C

()
0
C

-450
-900
Fig. 10.5: Amplitude-frequency response and phase-frequency response of a
simple RC lowpass filter.
116
In the graphs in Figure 10.5, a logarithmic scale for the frequency is normally used. A
logarithmic scale is nonlinear. Half-logarithmic and full-logarithmic graph papers are
commercially available. Half-logarithmic means that one axis is logarithmic while the
second axis is linear. A full-logarithmic graph paper has both axes logarithmic.
There is another type of plot of the transfer function called a Bode plot. In a Bode plot,
the amplitude on a logarithmic scale is plotted against the frequency also on a logarithmic
scale, and the phase is plotted against frequency on a logarithmic scale. The amplitude is
expressed as:
a( )  20 log 10 A( )
(10.22)
a() is measured in decibels (dB). For the LPF in equation (10.20), we get


a( )  10 log10 1   2 /  C . If we again look at the three cases considered earlier, we
2
get:

For    C
a  10 log 10 1  0

For    C
a  10 log10 2  3.0 dB

For    C

a  10 log10  2 /  C
2
  20 log
10
 /  C  .
Now a change in frequency from  to 10 on the logarithmic scale is called a decade.
Thus log10 10   log10   log10 10 /    log10 10  1decade. Therefore the function
a  20 log 10  /  C  is a linear function with a gradient of –20dB per decade. Figure
10.6 shows the Bode plots.
117
a()
(dB
0
0
C

-3.0dB
()
0
C

-450
-900
Fig. 10.6: Bode plots of amplitude and phase of the RC lowpass filter
We note again that at the cutoff frequency C, the gain reduces by a factor of 1 / 2 ,
which is equivalent to about –3.0dB. For this reason the cutoff frequency is known as the
3dB point. Other names for the cutoff frequency are breakpoint and corner frequency.
118
Both plots are useful because they can be plotted directly from the voltage transfer
function of a linear circuit by making quick sketches of Bode plots using linear
approximations. The second advantage is in the case of a transfer function of the form
A=A1A2. This could be a cascade connection of two amplifiers of transfer functions (or
gains) A1 and A2. They could even be more than two amplifiers. Since
log10 A  log10 A1  log10 A2 , it means that we can we can graphically sketch separate
Bode plots for A1 and A2, and then add the two plots graphically to obtain the Bode plot
for A. Similarly for the phase we have =1+2, where 1 and 2 are the phases of A1 and
A2 respectively.
Highpass filter
A highpass filter (HPF) is a circuit that allows only signal above a given frequency the
cutoff frequency) to pass through it. Figure 10.7 shows a simple RC highpass filter.
C
Vin
R
Vout
Fig. 10.7: Simple highpass filter
The output voltage Vout is given by Vout 
R
Vin , where ZC=1/jC. Hence the
R  ZC
transfer function is given by:
A
1
1  j C / 
119
(10.23)
where C=1/RC is the cutoff frequency, and we have made use of the fact that 1/j=-j.
From equation (10.22) it follows that the magnitude is given by:
1
A
(10.24)
1  C /  2
2
or

a( )  20 log10 A( )  10 log10 1   C /  2
2

(10.25)
The phase shift between Vout and Vin is equal to the angle of A given by equation (10.23):
 ( )  arctan( C /  )
(10.26a)
 ( f )  arctan( f C / f )
(10.26b)
or
To sketch A( ) we note the following:

For    C , A   /  C

For    C , A 

For    C , A  1
1
2
 0.71
To sketch () we note that:

(0)=900,

(C)=450,

()=0.
120
Figure 10.8 shows the sketch graphs for A( ) and ().
A( )
1
1/ 2
0
C

C

()
900
450
0
0
Fig. 10.8: Amplitude and phase responses of an RC highpass filter.
For an ideal HPF we should have A such that A =0 for <C, and A =1 for C.
Similarly for an ideal LPF we should have A such that A =1 for <C, and A =0 for
C.
121
Bandpass filter
A bandpass filter (BPF) is a circuit that allows only signals between two given
frequencies (cutoff frequencies) to pass through it. A simple BPF is the series RLC
circuit in Figure 10.1(a) when the output is taken from across the resistor R. The transfer
function A=Vout/Vin is given by A=R/Z, where Z is the impedance given by equation
(10.9).

1 
1   2


Z  R  j L 

R

j

1

C 
C   0 2 

where  0 
1
LC
is the resonance frequency. If we look at Z we see that
ZR+1/jC, for low frequencies (<<0)
ZR+jL, for high frequencies. (>>0)
This means that for low frequencies the RLC series circuit behaves like a HPF with cutoff
frequency 1=1/RC, and for high frequencies the circuit behaves like a LPF with cutoff
frequency 2=R/L. The LPF consists of an inductor (L) in series with a resistor(R).
Let us look at A( )  R / Z :
A
1
1
1 2 2 2
 C R
 2




1
2


0


2
We note that A(0) =0, A( C ) =1 = max. value, and A() =0. The cutoff frequencies
can be found by letting A( )  1 / 2 or A( )  1 / 2 , and finding the roots of the
2
polynomial.
122
A( ) 
 2C 2 R 2
2


 2C 2 R 2   2 /  0 2  1
2

1
2
This reduces to
2
1 

2
 L 
 R
C 

(10.27)
This equation has two real solutions 1 and 2 for positive frequencies. These are the
cutoff frequencies, called the lower cutoff frequency and the upper cutoff frequency. The
difference between the lower and the upper cutoff frequencies is called the 3dB
bandwidth, defined mathematically by
B=f2-f1
(10.28)
Note that B can also be written as B=(2-1)/2, since =2f. the quality factor Q, which
is a measure of the sharpness of the peak of A( ) versus , is defined by
Q
f0
B
(10.29)
The quality factor can also obtained as the ratio of the power stored in the circuit at
resonance to the power lost. The power stored at resonance is either P0=Io20L or
P0=Io2/0C, and the power lost is P=I02R, where I0 is the current at resonance. If V is the
applied input voltage, ten I0= V / R . Therefore we can also express the Q-factor as:
Q
0 L
R

1
1 L

 0 CR R C
123
(10.30)
From equation (10.29) it is clear that for higher Q-factors the bandwidth becomes
smaller.
In the RLC bandpass filter, see Figure 10.1(a), we chose to take the output from across R.
We can also take the output from across the capacitor or the inductor. In this case the
frequency response will be slightly different; the maximum does not occur at the
resonance frequency 0: in the case of the output being taken from across the capacitor,
all the input voltage appears across the capacitor at =0, and in the case of the output
being taken from across the inductor, all the input voltage appears across the inductor at
infinitely large values of  (=).
Band reject filter
The fourth type of filter is the band-reject filter, also known as the notch filter or trap.
The circuit allows signals below and above given frequencies to pass through it. Figure
10.9 shows a simple notch filter. The circuit is a trap for signals at or near the resonance
frequency, shorting them to ground.
R
Vout
L
Vin
C
Fig. 10.9: Simple notch filter
124
The transfer function of the notch filter circuit is given by
A( ) 
Vout
j L  1 / jC 

Vin
R  j L  1 / jC 
(10.31)
and the magnitude A( ) is given by
 2 / 02 1
A


 C R   / 0 1
2
2
2
2
2
2
(10.32)
where  0  1 / LC is the resonance frequency. We see that A =1 for =0 and =, but
A =0 at resonance =0. Figure 10.10 shows the frequency response.
A( )
1.0
0
0

Fig.10.10: Frequency response of the RLC notch filter.
125
Questions
13. (a) Define a tuned or resonance circuit.
(b) What is a resonator? Name the two types of resonators used in tuned circuits.
(c) Two fundamental parameters used to describe the behavior of RLC circuits are
the resonant frequency and the damping factor. Define these two parameters.
14. A series RLC circuit has the following components: R=100, L=10mH and
C=25nF. Calculate the following parameters: resonance frequency, damping
factor, bandwidth and Q-factor.
[Ans: f010 kHz,   1 / 4 10 0.08, f1.60 kHz, Q6.3]
15. Figure 10.11 shows a series RLC circuit.
I
V
R
VR
L
VL
C
VC
Fig. 10.11
(a) Determine the transfer functions AR()=VR/V, AL()=VL/V, AC()=VC/V.
126
(b) Show that (i) AR (0) = AL (0) =0, AC (0) =1
(ii) AR ( 0 ) =1, AL ( 0 ) = AC ( 0 ) =1/2
(iii) AR () =0, AL () =1, AC () =0
(c) Hence use the results above to sketch graphs for AR ( ) , AL ( ) and
AC ( ) , on the same axes.
16. Figure 1012 shows a resonant circuit.
R
VR
Vin
L
C
VC
Fig. 10.12
Determine and sketch the frequency response for the transfer functions
AR()=VR/Vin and AC()=VC/Vin
17. (a) What is a filter?
(b) Draw the frequency response of each of the following types of filters: LPF,
HPF, BPF, BRF.
(d) What is meant by the following: cutoff frequency, 3dB point, and bandwidth?
18. Given an inductor L and a resistor R, draw simple circuits for a LPF and a n HPF.
What is the cutoff frequency in each case?
19. Two RC lowpass filters having cutoff frequencies 1=1/R1C1 and 2=1/R2C2 are
connected in cascade.
127
(a) Draw the circuit diagram.
(b) Sketch the Bode plots if, (i) 1=2, (ii) 2>1.
Further Reading
3. Seeti, M.L.: Basic Electronics; Makerere 2003.
4. Crecraft D.I., et al: Electronics.
128
LECTURE 11
BIPOLAR TRANSISTORS: STRUCTURE
Introduction
In this lecture we introduce the bipolar junction transistor (BJT) as a three-terminal twojunction device which must be biased in a particular way. The circuit symbols of the two
types of transistor are introduced. A circuit to measure the current–voltage characteristics
of a transistor is presented and discussed, and the characteristics are also presented and
discussed.
Objectives
By the end of this lecture you should be able to:

Describe the bipolar transistor in terms pn-junctions or diodes;

Draw the circuit symbols for npn and pnp transistors;

Describe the biscs of a transistor for normal operation;

Draw the circuit for the determination of the input and output characteristics
of a BJT;

Sketch the input and output characteristics of a BJT.
General features
A bipolar junction transistor (BJT) consists of two pn-junctions. There are two
possibilities of how two pn-junctions can be made, as shown in Figure 12.1(a).
B
C
C
n
p
p
B
n
n
p
E
E
(a)
129
C
C
B
B
E
E
(b)
C
C
B
B
E
E
(c)
Fig. 11.1: npn and pnp transistors; (a)Block diagram, (b)Diode equivalent
circuits, (c)Circuit symbols.
From Lecture 8 we saw that a pn-junction constitutes a diode, hence the diode equivalent
circuits in Figure 11.1(b). Figure 11.1(c) shows the circuit symbols for npn- and pnptransistors. The direction of the arrow serves to differentiate an npn-transistor from a
pnp–transistor, and is drawn on the terminal E. The three terminals are labelled B(base),
C (collector) and E (emitter). One way to remember the direction of the arrow in the
circuit symbols is to note that in both cases the arrow runs from p-region towards nregion.
Currents and Voltages of a BJT
Figure 11.2 shows the currents and voltages of an npn type BJT.
130
IC
C
IB
B
E
VBE
VCE
IE
E
Fig.11.2: Currents and voltages of a BJT
The current IB entering the base is called the base current. The current IC entering the
collector is called the collector current, and IE is the emitter current. The potential
difference VBE between the base and the emitter is called the base-emitter voltage, and
VCE is the collector-emitter voltage. Otherwise the potentials of the individual terminals
B,C and E, w.r.t. some reference point (ground), are known as the base voltage (or
potential) VB, collector voltage VC and emitter voltage VE. It follows that VBE=VB–VE,
VCE = VC – VE and VCB = VC – VB. For an npn-transistor all the currents and voltages
shown in Figure 11.2 are positive. For a pnp–transistor, all the arrows in Figure 11.2
must be reversed.
From Kirchhoff’s current law, applied on the circuit in Figure 11.2, we see that
I B  IC  I E
(11.1)
If we let =IC/IE and =IC/IB, we can find a relationship between  and  using equation
(11.1). First we divide equation (11.1) by IE and substitute for IC/IE=. Secondly we
divide equation (11.1) by IB and substitute for IC/IB=. From the two equations obtained
we eliminate the ratio IE/IB to obtain.


1
(11.2)
In practice IB is very small compared to either IC or IE. In fact IB is usually in the Arange whereas IC (and IE) is in the mA–range. This means that the emitter current is
131
approximately equal to the collector current and 1. The ratio =IC/IB is much larger
than unity.
Normal operation of a BJT
We have seen that an npn-transistor consists of a pn-junction between the base and the
emitter and another pn-junction between the base and the collector. The two junctions
may be likened to two diodes connected back–to–back, as shown in Figure 11.1(b). The
two diodes must biased. In the normal operation of a bipolar junction transistor, the baseemitter junction (or diode) is forward-biased and the base–collector junction is reverse–
biased. This is shown using batteries in Figure 11.3.
IC
VCC
C
IC
VCC
C
IB B
IB B
E
VEE
IE
E
VEE
IE
(a)
(b)
Fig.11.3: Bias for normal operation a BJT: (a) npn , (b) pnp.
Figure 11.3(b) shows the bias for the normal operation of a pnp-transistor. In practice the
batteries VEE and Vcc in Figure 11.3 are replaced by potential dividers in such a way that
the transistor has only one power supply.
132
Characteristics of a BJT
IC
VBB
IB
VCE
VCE
VBE
Fig.11.4: Circuit for determining the d.c. characteristics of a BJT.
Figure 11.4 shows a circuit which can be used to determine the input and output
characteristics of an npn type BJT. For a pnp type BJT the polarities of the two d.c.
power supplies VBB and Vcc are reversed (of course the meters must also be reversed).
VBB is a small d.c. supply of a bout 1.5V (a dry cell can do) and VCC could be a d.c.
power supply of say 12V, depending on the transistor used (manufacturer will give limit
on VCE and IC). We start by fixing the value of VCE by means of the right potentiometer.
We then vary VBE and note the corresponding base current IB. The results may be put in
form of a table as shown in table 11.1.
Table11.1: VCE=const.
Table11.2: IB=const.
VBE
VCE
IB
IC
Before each pair of readings for VBE and IB are read and recorded we must always make
sure that VCE has remained the same. If it changes it must be brought back to its fixed
value by use of the potentiometer before the readings are taken.
In table 11.2 the base current IB is fixed by the left potentiometer and VCE is varied using
the right potentiometer. The maximum collector current allowed by the manufacturer for
a given transistor must not be exceeded.
133
If we plot graphs of IB against VBE for fixed values of VCE, and graphs of IC against VCE
for fixed values of IB, we get the so-called input and output characteristics. The typical
BJT input and output characteristics are shown in Figure 11.5.
IB
IC
VCE
IB
IB=0
VBE
(a)
VCE
(b)
Fig.11.5 I-V characteristics of a BJT: (a)Input characteristics, (b)Output characteristics.
The shape of the input characteristics, Figure 11.5(a) is not surprising. They look like the
I-V characteristics of a diode. Indeed VBE is the forward bias voltage of the base-emitter
junction (or diode). The output characteristics, Figure 11.5(b), show curves which
become almost horizontal for larger values of the collector-emitter voltage. Note that for
IB=0 no collector current IC flows through the transistor even though there is a collector–
emitter voltage. This is the most important feature of the transistor as a three-terminal
device. The base current acts like a control for the flow of the collector current. The
larger IB is the more collector current will flow. The base current and the collector current
are related approximately equation (11.2). The characteristics in Figure 11.5 are
commonly referred to as common–emitter characteristics. This is because in the circuit
in Figure 11.4, the emitter has the lowest potential. Note that in the input characteristics
in Figure 11.5(a) the parameter could have been IC instead of VCE. Similarly in the
output characteristics in Figure 11.5(b) the parameter could have been VBE instead of IB.
134
QUESTIONS
1. (a) Identify the type of doping for each of the regions inside a pnp-transistor and an
npn-transistor.
(b) Draw the circuit symbols for a pnp- and an npn transistor.
2. (a) How are the base-emitter junction (or diode) and the collector-base junction
biased for normal operation of a BJT?
(b) Draw a circuit showing the biasing of the two junctions of a pnp transistor using
batteries for the biasing voltages.
3. (a) What is meant by the common-emitter input and output characteristics of a BJT?
(b) How can the common-emitter input and output characteristics be determined?
(c) Draw sketch graphs for the input and output characteristics.
4 How can you explain the shape of the common-emitter input characteristics of a
bipolar transistor?
5. (a) Draw the circuit symbol of an npn-transistor and label the base B, the collector
C and the emitter E.
(b) Indicate the base current IB, the collector current IC and the emitter current IE in
your diagram.
(c) How are the three currents related?
(d) Given that =IC/IE and =IC/IB. Show that  


and  
.
1
1 
(e) Given that 1, what can you say about  and how does this relate to the
collector and emitter currents?
Further Reading
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
135
LECTURE 12
BIPOLAR TRANSISTORS: SMALL–SIGNAL EQUIVALENT CIRCUITS
Introduction
In this lecture we introduce the hybrid parameters starting form the static current-voltage
characteristics. We learn how to determine the h parameters graphically from the static
characteristics. After deriving the small signal hybrid equation we draw the small-signal
equivalent circuit of a transistor. We define the transconductance of a transistor and
derive a simple expression for it in terms of the collector current.
Objectives
By the end of this lecture you should be able to:

Define the input resistance, the reverse-voltage ratio, the forward current ratio and the
output resistance of a bipolar junction transistor (BJT);

Determine the hybrid parameters from the static input and output characteristics;

Draw the small-signal equivalent circuit of a BJT;

Define the transconductance of a BJT;

Prove that the transconductance is proportional to the collector current.
Hybrid parameters
A look at the common-emitter input and output characteristics in Figure 12.5 suggests
that we can write the base-emitter voltage VBE as a function of the base current IB and the
collector-emitter voltage VCE. In a similar way we can also write the collector current IC,
as a function of IB and VCE. Thus mathematically we can write,
VBE=f1(IB, VCE)
(12.1)
IC=f2(IB, VCE)
(12.2)
136
Now looking at the currents and voltages of a transistor, as depicted in Figure 12.2, we
can think of VBE and IB as input quantities and, IC and VCE as output quantities. Thus in
equation (12.1) an input voltage VBE is expressed as a function of an input current IB and
an output voltage VCE. Similarly an output current IC is expressed as a function of an
input and an output quantity. This formulation leads to hybrid parameters. Other
commonly used two-port parameters are the admittance (or y-) parameters and the
impedance (or Z-) parameters.
From equations (12.1) and (12.2) we can write the total differentials of VBE and IC as
 V
VBE   BE
 I B
 I
I C   C
 I B
 V

 .I B   BE
VCE
 VCE
 I

 .I B   C
VCE
 VCE

 .VCE
 IB

 .VCE
 IB
(12.3)
(12.4)
where we have assumed that dx=x, that is, the differential dx is equal to the change x
in x. This is true for small changes. We have included the subscripts on the partial
derivatives in order to emphasise the variable that is supposed to be kept constant. This is
 z 
a common practice in Thermodynamics. If z=(x,y), then we write   instead of
 x  y
simply
z
 z 
. Symbolically   means the change in z with respect to x, regarding y as
x
 x  y
a constant. We now make definitions for the partial derivatives appearing in equations
(12.3) and (12.4).
 V
hie   BE
 I B


VCE
(12.5)
 V
hre   BE
 VCE


 IB
(12.6)
137
 I
h fe   C
 I B


VCE
 I
h0e   C
 VCE
(12.7)


 IB
(12.7)
hie = input impedance
hre = reverse voltage (feedback) ratio
hfe = forward current amplification factor
hoe = output admittance
These quantities are called the hybrid or h-parameters. The subscript e refers to common
emitter.
If we also write for small signals:
VBE=vbe, IB=Ib, VCE=vce, and IC=ic,
then equations (12.3) and (12.4) can be rewritten as:
vbe=hieib+hrevce
(12..9)
ic=hfeib+h0evce
(12.10)
The hybrid parameters defined by equations (12.5) to (12.8) can be obtained graphically
from the I-V characteristics of the transistor. Figure 12.1 illustrates how to determine the
h-parameters from the input and output characteristics. First of all we have to fix a
working point, as we shall see later in another lecture, for example the point P in Figure
12.1(a). For a single curve, like one of those in Figures 12.1(a) and 12.1 (d), all is needed
is the drawing of a tangent at a given point P and determining its slope. For a pair of
curves (not too far apart to keep the change in the parameter small), like the ones in
Figures 12.1(b) and 12.1(c), the difference between the two values of the parameter gives
the change in that quantity.
138
IB
VCE=const.
IB
tangent at P
VCE1
VCE2
IB=const.
P
VBE
VBE
(a)
VBE
(b)
IC
IC
VCE=const.
IC
tangent
IB2
P
IB=const.
IB1
VCE
(c)
VCE
(d)
Fig.12.1: Graphical determination of h-parameters; (a) hie=1/slope,
(b) hre=VBE/(VCE2-VCE1), (c) hfe=IC/(IB2-IB1), (d) hoe=slope.
Small-signal equivalent circuit
An interpretation of the small–signal equations (12.9) and (12.10) leads to the smallsignal (or a.c.) equivalent circuit of a BJT. Let us first look at equation (12.9), namely
vbe=hieib+hrevce, the left-hand side is the potential difference between the base and emitter
terminals of the transistor. The base current ib flows through an impedance (or resistance)
hie to produce a potential drop Ibhie. We can take hrevce to be a voltage source, it is a
voltage-dependent voltage source, its magnitude is determined by the potential difference
vce between the collector and emitter. We see that vbe=hieib+hrevce is a loop (or mesh)
equation written according to Kirchhoff’s voltage law. On the other hand the equation
ic=hfeib+h0evce is a node equation written according to Kirchhoff’s current law. The
equation is telling us that the collector current ic entering the collector terminal C consists
139
of two currents, a current h0evce flowing through an admittance hoe (or impedance 1/hoe)
connected between the collector C and the emitter E, and a current hfeib which is a
current source. Figure 12.2 shows the resulting small-signal equivalent circuit. It is a lowfrequency (f = 30 to 300 kHz) and midband (300kHz – 3mHz) model.
B
ib
hie
C
ic
hfeib
vbe
hrevce
1/hoe
vce
E
Fig. 12.2: Small signal equivalent circuit of a transistor.
In practice the reverse-voltage ratio hre is very small, typically in the order of 10-4, and
may be considered negligible (hre0). This may become apparent if the curves in Figure
12.1(b) are plotted. The change in VBE used in determining hre is very small. If hre is
neglected the small-signal equivalent circuit in Figure 12.2 reduces to that in Figure
12.3(a). This is the equivalent circuit we shall commonly use.
B
ib
C
ic
hfeib
vbe
hie
1/hoe
vce
E
(a)
hfeib
ib
B
hie
1/hoe
E
ic
C
(b)
Fig. 12.3: Small–signal equivalent circuit of a transistor with negligible
reverse-voltage ratio. Circuit (a) is the same as circuit (b).
140
Instead of the four h-parameters some people prefer to use the following alternate
symbols:
rbe=hie
(12.11)
rce=1/hoe
(12.12)
=hfe
(12.13)
Ar=hre0
(12.14)
The advantage of using these symbols is that we can straight away tell that rbe and rce are
resistances at the base and collector respectively.  is a number (it is the ratio of collector
current to base current). We shall be using these symbols more commonly than the hparameters. The equivalent circuit in Figure 12.3(b) can be repeated with the new
symbols as in Figure 12.4.
ib
ib
rbe
rce
B
E
ic
C
Fig. 12. 4: Signal equivalent circuit of a transistor
Let us define another parameter which is commonly used. Since the collector current
varies linearly with the base current for large currents ( d.c.), a plot of IC against VBE
gives a curve similar to that in Figure 12.1(a). A slope on such a graph gives a quantity
called the transconductance gm defined by
gm 

(12.15)
rbe
Use of equations (12.5) and (12.7) together with equations (12.11) and (12.13) gives the
transconductance as
 I
g m   C
 VBE


VCE
141
(12.16)
It is called transconductance because the current IC is from the output while the voltage
VBE is from the input side of the equivalent circuit. 1/rbe is the input conductance and
1/rce is the output conductance. Practically we can estimate gm by use of the diode
equation for the base-emitter junction. With the base-emitter junction forward-biased,
ICIE so that I C  I O eVBE / VT . Therefore the transconductance
gm 
dI C
I
I
 O eVBE / VT  C .
dVBE VT
VT
Thus
gm 
IC
VT
(12.17)
VT=kT/q26mV at room temperature. Thus gm is proportional to the collector current.
Equations (12.15) and (12.17) also give
VT
IB
rbe 
(12.18)
We have seen one method of determining the four h parameters in the common-emitter
configuration, the method involved a graphical evaluation from the transistor static
characteristics, which are either given by the manufacturers or can be obtained
experimentally, or can be displayed on a curve tracer. Another method involves making
actual measurements in a circuit with the transistor biased and a.c. signals applied.
Biasing means fixing the working point. From the small-signal equations (12.9) and
(12.10) we see that
vbe
ib
rbe 

at VCE=VCEQ
ic
at VCE=VCEQ
ib
Ar 
vbe
vce
at IB=IBQ
142
rce 
vce
ic
at IB=IBQ
The condition vce=0 means that there is no a.c. collector-emitter voltage; that is, the
collector-emitter voltage VCE is kept constant at its working (or quiescent) point value
VCE=VCEQ. Similarly ib=0 means that there is no a.c. base current; that is, the base current
is kept constant at its working point value IB=IBQ.
The small–signal equivalent circuit we have derived above contains a current-dependent
current source ib (or hfeib) between the collector C and the emitter E. If we think of the
output resistance rce (or 1/hoe), which is located between C and E, as the internal
resistance of the current source, we can convert this current source into a voltage source
having a series internal resistance rce. The voltage source (including its series internal
resistance rce) is connected between C and E. The voltage source ibrce is called a
current-dependent voltage source.
143
Questions
1. (a) Write down the small–signal hybrid equations of a common emitter configuration
bipolar junction transistor in a matrix form.
(b) Define the hybrid parameters in terms of the d.c. currents and voltages of the
transistor.
2. (a) What do you understand by “small–signals”?
(b) Describe how you would determine the four hybrid parameters of a bipolar
transistor from the static input and output characteristics of the transistor.
3. (a) Draw the small-signal equivalent circuit of a bipolar transistor containing a
current-dependent current source.
(b) Draw the small-signal equivalent circuit of a bipolar transistor containing a
current-dependent voltage source.
4. (a) Define the transconductance of a bipolar transistor.
(b) Calculate the transconductance of the transistor when
(i) IC=10A, and (ii) IC=20A.
5. A bipolar transistor with a forward current gain =100 passes a collector current of
26mA. Estimate the input resistance of the transistor. (Hint: g m 
Further Reading
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
144

rbe
IC/VT).
LECTURE 13:
COMMON EMITTER AMPLIFIER
Introduction
In this lecture we introduce the common-emitter amplifier. We start with the d.c. biasing
of the transistor and them substitute the transistor with its small-signal equivalent circuit.
The blocking and bypass capacitors are explained. The equivalent circuits of the amplifier
for low-frequency and medium-frequency are given and discussed. The voltage gain and
current gain for medium frequencies (midband) are calculated.
Objective
By the end of this lecture you should be able to:

Draw the circuit of a common-emitter amplifier;

Explain the functions of the blocking and bypass capacitors;

Explain the biasing of the base-emitter diode;

Calculate the midband voltage gain;

Calculate the midland current gain.
Common – Emitter amplifier
Figure 13.1(a) shows the basic common-emitter amplifier. The emitter is connected to
ground and the power supply Vcc is connected to the collector via a collector resistor RC
which limits the amount of collector current through the transistor.
+VCC
IC
R1
RC
B
Vin
IC
VCC
R1
C
B
R2
Vin
E
RC
C
R2
Vout
E
(a)
(b)
Fig. 13.1: Basic common-emitter amplifier.
145
Vout
Instead of drawing the power supply Vcc as in Figure 13.1(a), it suffices just to show the
positive terminal as shown in Figure 13.1(b). This is the common method of showing the
power supply. The negative terminal is assumed to be connected to ground, in our case
the emitter.
If we write the voltage equation for the output loop, that is, the loop containing RC, VCE
and Vcc, we get
ICRC+VCE=VCC
(13.1)
This equation is known as the load-line equation. A plot of IC against VCE gives the
straight line shown in Figure 13.2. It has the intercepts Vcc and Vcc/Rc on the horizontal
and vertical axes respectively.
IC
VCC
RC
ICQ
IB=IBQ
VCEQ
VCC
VCE
Fig. 13.2: The load line and working point Q.
The intersection of the load-line and an output characteristic for a given base current
gives the working point Q, which is also shown in Figure 13.2. How do we choose a
working point? First we note that the slope of the load line can be changed by varying RC.
The working point is normally chosen to lie on the linear part of the output characteristic.
The collector-emitter voltage VCEQ is usually chosen to be
1
VCC. The magnitude of the
2
collector current ICQ is chosen according to the purpose of the circuit. Knowing ICQ and
VCEQ, we can calculate the collector resistor RC using the load line equation (13.1):
146
VCE  VCEQ
RC 
(13.2)
I CQ
Suppose that we know the forward current amplification  of the transistor, then the base
current corresponding to the collector current ICQ is given by
I BQ 
I CQ
(13.3)

This is the base current we must allow through the base of the transistor. This is done by
the resistors R1 an R2 in Figure 13.1. If we make the base current small compared to the
current through R1 and R2 for all likely values of , the resistors R1 and R2 can be taken
to be a potential divider. This is important
because the potential difference across R2
will provide the forward-bias voltage (about 0.65V for silicon) for the base-emitter diode.
This will provide one condition for calculating the resistors of the potential divider:
R2
VCC  VBE
R1  R2
(13.4)
If we choose the current through the potential divider to be about 10IBQ, (i.e. ten-times
IBQ) then the current through R2 should be about 9IBQ, so that R2 is given by
R2 
VBE
9 I BQ
(13.5)
As we shall see later the values for R1 and R2 are chosen to be large so that their parallel
combination is large compared to the input resistance of the transistor.
In the foregoing discussion we designed a common-emitter amplifier for a particular
value of . But the spread of  (i.e. the range of possible values of ) is wide, even for a
given type of transistor. Figure 13.3 shows the usual way of reducing the variation of
147
aperating point, due to differences in the values of , in a discrete common-emitter
amplifier.
+VCC
IC
RS
C1
R1
B
VS
RC
IB
C
R2
Vin
C2
C
E
RL
RE
CE
Vout
Fig. 13.3: Common–emitter amplifier
The input Vin is provided by a signal source VS of internal resistance RS. The capacitors
C1 and C2 act as blocking capacitors, C1 blocks any d.c. component from the signal
source from entering the amplifier and C2 blocks any d.c. component from the power
source from appearing in the output Vout of the amplifier. The base potential is still
determined by the potential divider formed by the resistors R1 and R2. But the emitter
current (and therefore the collector current) is determined by the emitter resistor RE. The
capacitor CE across the emitter resistor is a large capacitor called a bypass capacitor. It
restores the small-signal gain without upsetting the d.c. working point. It is usually
chosen large enough to effectively short-out RE at signal frequencies.
The load line of the common–emitter amplifier in Figure 13.3 is given by the equation.
(RC+RE)IC+VCE=VCC
(13.6)
where we have taken the emitter current to be equal tot he collector current. To fix the
collector current, we choose an emitter potential (the potential drop across RE) that is
much greater than the likely variations in the base-emitter voltage VBE. Since VBE0.65V
148
for a silicon transistor, a choice of VE=1.0V can suffice as we don’t expect VBE to reach
1.0V. This will fix the collector current to
IC=VE/RE=1.0V/RE
This means that the base potential should be held to a voltage of about
VB=VBE+VE+0.65+1.0=1.65V. This is the voltage I2R2 across the potential divider
resistor R2. The voltage drop I1R1 across the potential divider resistor R1 is equal to VCCVB or VCC-1.65V. Therefore the ratio of R2 to R1 will be given by
I 2 R2
VB

I 1 R1 VCC  VB
where I1 and I2 are the currents through the potential divider resistors R1 and R2
respectively. Note that if the potential divider were ideal then we would have I1 = I2. But
we assume as we did before that I1=10IB and I2=9IB, then I1/I2=10/9.
The collector resistor RC is determined from the load line equation (13.6).
As an example suppose Vcc=12V and we need a collector current of 5mA:
If we set VE=IEREICRE=1.0V, then RE=1.0/5x10-3=200.
Since VB=VBE+VE=0.65+1.0=1.65V, the ratio R2/R1 is given by
R2  I 1  V B
10
1.65
16.5
  
 

R1  I 2  VCC  VB
9 12  1.65 93.15
This gives us several choices for R1 and R2. We choose R2=15k and R1=93k. Note
that RP=R1//R2= R1R2/( R1+R2)=12.9k. As we shall see later this resistor Rp appears in
parallel with the rbe, the input resistance of the transistor. If we make RP>>rbe, then Rp
will not have much effect on the amplifier. Choosing VCE=VCC/2=6V, we get Rc using
the load line equation (13.6):
149
RC 
VCC  VCE
12  6
 RE 
 200  1k .
IC
5  10 3
To calculate the voltage gain, AV=Vout/Vin, we need to use the small-signal equivalent
circuit. But before we do that let us estimate the voltage gain when the emitter bypass
capacitor CE in Figure 13.3 is omitted, that is, removed. The d.c. input voltage at the base
is equal to VBE+IERE and the d.c. output voltage at the collector is equal to –ICRC+VCC.
Therefore for a.c. (or small signals) Vin=REIE and Vout=-RCIC. Therefore if we assume
that ICIE, the voltage gain becomes AV=Vout/Vin=-RC/RE.
The small-signal equivalent circuit of he common-emitter amplifier
In Lecture 12 we developed a small-signal equivalent circuit of a BJT for low and
medium frequencies. We now use this model to analyse the common-emitter amplifier in
Figure 13.3. To do this we replace the transistor by its small-signal equivalent circuit (e.g.
Figure 12.4 in lecture 12) and all d.c. supplies by their internal impedances (this is
equivalent to shorting the d.c. supplies if the internal impedance is negligible). Figure
13.4 shows the amplifier equivalent circuit for low frequencies (frequencies below 300
kHz).
ib
C1
Vin
B ib
R1
R2
rbe
E
RE
rce
C C2
CE
RC
Vout
Fig. 13.4: Common–emitter amplifier equivalent circuit for low frequencies.
150
Because of shorting the d.c. power supply (Vcc), both R1 and RC have their common end
connected to ground. The circuit in Figure 13.4 is unloaded (because we have removed
the load RL at the output).
For medium frequencies (300kHz – 3MHz) the blocking and bypass capacitors are
replaced by short circuits. This is because the capacitors are large, in the F-range, so that
at these frequencies, their impedances approach short-circuits. Figure 13.5 shows the
amplifier equivalent circuit for medium frequencies (midband).
i1
B ib
C
io
ib
Vin
R1
R2
rbe
rce
RC
Vout
E
Fig. 13.5 Common–emitter amplifier equivalent circuit for midband.
Voltage gain:
The voltage gain AV of the amplifier is defined by Vout/ Vin. Since the circuit in Figure
13.5 is simpler let us find the voltage gain for the midband, called the midband gain.
Since the circuit contains no reactive elements, it will give a gain which is independent of
frequency. A loop equation containing Vin and rbe gives
ib rbe  Vin  0
Next we consider mode C. since Rc and rce are in parallel and the potential difference
across them is Vout, the currents through the two resistors are Vout/RC and Vout/rce,
flowing in the arrow direction for Vout. Therefore a mode equation for mode C yields
151
Vout Vout

 ib  0
RC
rce
Substitution for ib=Vin/rbe and AV=Vout/Vin gives
AV  

RC rce
rbe RC  rce
(13.7)
or
AV   
RC // rce
rbe
If Rc is small compared to rce, then Rc// rce Rc, and the gain reduces to AV=- Rc/rbe.
We can also find the current gain defined by Ai=i0/i1. If we let RP=R1//R2, then
i1=Vin/RP+Vin/rbe. The output current i0 is given by i0=-Vout/RC. Therefore the current gain
Ai=i0/i1=
 1
R // r 
 Vout
1 
/ Vin 
  =  AV P be .
RC
RC
 RP rbe 
Ai 
RP


RP  rbe 1  RC 
rce 

(13.8)
This expression for Ai reduces to Ai for rbe<<RP and RC<<rce.
Questions
1. (a) Draw the circuit of the basic common-emitter amplifier with no current
feedback (no emitter resistor).
(b) Obtain the load line from the circuit above and draw a sketch graph for it.
What is the significance of the intercepts?
(c) Explain what is meant by the “working point”?
2. (a) What are blocking capacitors and bypass capacitor for?
152
(b) The common-emitter amplifier includes a potential divider at the base of the
transistor. What is the potential divider for and how is it used?
3. (a) What do you understand by low and medium–frequencies? Why is it
important to differentiate the two frequency bands?
(b) Draw the common-emitter amplifier equivalent circuit for the midband.
(i)
Derive expressions for the voltage and current gains.
(ii)
Given that =100, RC=10k, rce=100k, rbe=2k and the potential
divider resistors R1=93k, R2=15k. Calculate the voltage gain and the
current gain.
Further reading
Seet, M.L : Basic Electronics; Makerere 2003.
153
LECTURE 14
THE EMITTER–FOLLOWER
Introduction
In this lecture introduce the emitter-follower (or common-collector amplifier). We derive
the expressions for the voltage gain and the current gain. Before deriving the input and
output resistances of the emitter-follower, we define and discuss the input and output
impedances of an amplifier.
Objectives
By the end of this lecture you should be able to

Draw the basic circuit of an emitter-follower;

Draw the small-signal equivalent circuit of an emitter-follower;

Derive an expression for the voltage gain of an emitter-follower;

Derive an expression for the input resistance of an emitter-follower;

Derive an expression for the output resistance of an emitter- follower;

Discuss possible applications of an emitter-follower.
The Emitter –follower
+VCC
R1
C1
C2
Vin
R1
RE
Fig. 14.1: Emitter – follower
154
Vout
Figure 14.1 shows an a.c coupled circuit of an emitter-follower. The basic circuit may
not have the capacitor C1 and C2. As you can see from the circuit diagram, the collector
will have the lowest potential for a.c signals.
Therefore the emitter- follower is a
common collector circuit. The collector is usually connected directly to the power
supply( in some cases through a resistor), but the output is always from the emitter
terminal. The emitter resistor RE is not shunted with a capacitor. The emitter-follower
also needs to be biased so that a collector current flows during the entire swing. Again,
as it was the case in the common emitter amplifier, a voltage divider consisting of the
resistors R1 and R2 is used. The circuit is called an emitter- follower because the output
at the emitter follows the input (the base), less one diode drop (about 0.65V):
Voltage gain
To analyse the emitter-follower let us draw the small signal equivalent circuit of the
circuit for the midband. Remember that for midband the coupling capacitors are shorted.
Substituting the transistor with its small-signal equivalent circuit, we get the circuit in
Figure 14.2(a).
ib
B
ib
E
rbe
Vin
R1
R2
RE
rce
C
Vout
Fig.14.2(a): Small-signal equivalent circuit of the emitter-follower.
155
i1
B ib
E
rbe
Vin
i2
i3
RP
rce
RE Vout
ibrce
C
Fig.14.2(b): Small-signal equivalent circuit of the emitter-follower.
From Figure 14.2(a) we note that the collector terminal C is the same as ground. We can
also convert the current source ib to a voltage source ibrce having a series internal
resistance rce. The current source is between collector C and emitter E, therefore the
voltage source must be between the same points. Figure 14.2(b) is the resulting
equivalent circuit to that in Figure 14.2(a), where RP=R1//R2. Using this circuit we are
going to calculate the voltage and current gains of the amplifier.
We first find ib by writing the voltage equation for the loop containing Vin, rbe and RE (or
Vout);
ibrbe+Vout-Vin=0
ib=(Vout-Vin)/rbe
Next we note that i2=Vout/RE and then use the current equation for node E to obtain i3;
i3  ib  i 2 
Vin  1
1 
Vout
  
rbe  rbe RE 
We then write the voltage equation for the loop containing Vin, rbe, rce, and the voltage
source ibrce:
ibrbe+i3rce+ibrce-Vin=0
Substitution for ib and i3 gives

  1 rce Vin  1    1 rce
rbe

rbe
156

rce 
Vout
RE 
or
AV 
Vout

Vin
 1
 1
rbe rbe

RE rce
If we assume that >>1, rbe<<RE and rbe<<rce, then
AV 
1
1
rbe
rbe
1

RE rce
The voltage gain AV is slightly less than unity.
(14.1)
For example if =100, RE=500,
rbe=2k and rce=100k, then AV0.96.
Current gain:
If we consider i1, as the input current and i2 as the output current, then the current gain Ai
is given by Ai= i2/ i1. Now i1=ib+Vin/RP=(Vin-Vout)/rbe+Vin/RP=(1/rbe+1/RP)Vin-Vout/rbe,
and i2=Vout/RE. Therefore
Ai 
If we substitute for
Ai 
Vout / RE
1

 1
V
1 
1  RE RE
 
Vin  out


r
R
r
A
RP
P 
be
V  rbe
 be
 RE
 
 rbe
r
r
1
 1  be  be , see equation (14.1), we get
AV
RE rce
1
 RE RE 
r
r  R

1  be  be   E

 rbe RP  RE rce  rbe
If we make RP fulfil the condition RP>>rbe, then RE/RP<<RE/rbe and Ai becomes
Ai 

(14.2)
R
1 E
rce
157
If RE<<rce, the current gain is approximately equal to . This is not surprising. Looking at
Figure 14.2(b), the current i1 is approximately equal to the base current ib, since Rp is of
high resistance and i2 is the emitter current which is approximately equal to the collector
current.
We see that although the emitter-follower is not amplifying voltage (VoutVin), current is
amplified according to equation (14.2). Therefore an emitter-follower is a current
amplifier. But the most important feature of an emitter-follow has something to do with
input and output resistances (or impedances in general).
Input and output impedance
RS
VS
i1
i2
AMP
Vin
Vout
Rin
RL
Rout
(a)
AMP
RS
VS
i1
Vin
Rout
Rin
i2
AVVin
Vout
(b)
Fig. 14.3: General features of an amplifier; (a) amplifier,
(b) equivalent circuit of an amplifier.
158
RL
Figure 14.3 shows the general features of an amplifier. A signal source VS with internal
resistance RS feeds the amp which is loaded with a load resistor R L. The signal source
sees a resistance Rin, between the input terminals of the amplifier, called the input
resistance of the amplifier. The equivalent circuit of the amplifier, shown in Figure
14.3(b), shows that the input resistance Rin is given by
Rin 
Vin
i1
(14.3)
From Figure 15.3(b) we see that not all the signal voltage Vs appears at the amplifier’s
input terminals. Some of the signal voltage appears across the internal resistance R S of
the signal source. The input Vin is given by
Vin 
Rin
VS
Rin  RS
(14.4)
We see that VinVS only if RS<<Rin. Therefore it is important to know the input
resistance of an amplifier so that a matching signal source can be used. At the output not
all the amplifier voltage AVVin appears at the output, across the load. Some of the
amplified voltage falls across a resistance Rout, called the output resistance of the
amplifier. For a loaded amplifier the output voltage Vout is given by
Vout 
RL
AV Vin
RL  Rout
(14.5)
We see that VoutAVVin only if RL>>Rout. Therefore knowledge of the output resistance
Rout helps in choosing the load RL. From Figure 14.3(b) we see that we can find Rout by
shorting the voltage source AVVin and finding the ratio Vout/i2. Since Vout=-i2RL, we can
replace the load RL with a voltage source Vout. Figure 14.4 shows how to find the output
resistance of an amplifier. The signal source VS is replaced by its internal resistance RS,
if any, and the load is replaced by a voltage source Vout.
159
RS
i2
Vin
Vout
AMP
Fig. 14.4: Determination of the output resistance of an amplifier,
Rout=Vout/i2. The voltage source VS in Figure 14.3(a) is shorted
and the load RL is replaced by a hypothetical source Vout.
The output resistance is given by
V 
Rout   out 
 i2 VS 0
(14.6)
We can now determine the input and output resistances of the emitter-follower. To
determine the input resistance we use the circuit in Figure 14.5, obtained from Figure
14.2(a) by combining RE and rce to get RE  RE // rce and then converting the current
source ib (now with internal resistance RE ) into a voltage source ibrce with a series
internal resistance RE .
i1
B
ib
E
rbe
Vin
RE
RP
=R1//R2
ib RE
C
Fig.14.5: Cicuit for the determination of the input resistance of the emitter
follower: Rin=Vin/i1.
160
A voltage equation for the loop containing Vin, rbe, RE and the voltage source ib RE
ib 
gives
Vin
  1RE  rbe
Noting that the current through RP is equal to Vin/RP, we write the current equation for
node B:
i1  ib 
Vin
RP
Substituting for ib and simplifying, with +1, gives the input resistance Rin=Vin/i1 as:
Rin 
RP RE  rbe 
RP  RE  rbe
If we assume that RE<<rce, then RE RE, so that
Rin  RP // RE  rbe 
(14.7)
If we make R1 and R2 high–ohmic, then RP=R1//R2 is still also large, and if RP>>RE, Rin
reduces simply to RE.
To calculate the output resistance Rout we use Figure 14.2(a) by replacing Vin with RS,
the internal resistance of the signal source. This results in RS being parallel to RP. If
RP>>RS, then RS//RPRS. We also combine RE//rceRE, assuming that RE<<rce. The
current source ib is converted into a voltage source ib(RE//rce) ibRE. The resulting
circuit is shown in Figure 14.6.
rbe
B
ib
E
i0
ie
RS
RE
Vout
ibRE
C
Fig. 14.6: Circuit for the determination of the output resistance of
the emitter follower; Rout=Vout/i0
161
The voltage equation for the loop containing RS+rbe and Vout gives
ib(RS+rbe)+Vout=0 or ib=-Vout/(RS+rbe)
The current equation for node E gives
ie=ib+i0=i0-Vout/(RS+rbe)
We use these currents in the voltage equation for the loop containing RE and the voltage
sources ibRE and Vout:
ieRE+ibRE -Vout=0

RE
RE 
Vout  0
i0 RE  1 

R

r
R

r
S
be
S
be 

Rout 
Vout
R (R  r )
RE

 E S be
i0

RE  RE  RS  rbe
1 

 RS  rbe 
This can be rewritten as
R r 
Rout  RE //  S be 
  
(14.8)
Equation (14.7) and (14.8) show that an emitter-follower has a high input resistance
RinRE and a very low output resistance Rout 
RS  rbe

. The circuit can be used as a
buffer to match a high-output resistance circuit to a low-resistance load.
162
Questions
1. (a) What does “emitter-follower” mean? What is the other name for an emitterfollower?
(b) Draw the circuit diagram of a basic emitter-follower.
2. An emitter-follower circuit is given in the Figure below;
+VCC=15V
R1
=130k
Vin
C1
C2
Vout
R2
=150k
RE
=7.5k
Given that =100:
(a) What is the quiescent (working) point? (Calculate IB, IC and VCE).
(b) Sketch the load line.
(c) Calculate the input and output resistances.
(d) C1 forms a high pass filter with the input resistance of the amplifier. What
value of C1 will give a cut off frequency of 20Hz or below?
(e) C2 forms a high-pass filter with the load impedance. Assuming that the load
impedance is not less than RE, what value of C2 will give a cut off frequency
below 20Hz?
(f) Now you have two high-pass filters in cascade. Will this not affect the values
for C1 and C2 if a cutoff frequency below 20Hz is to be achieved? How would
you choose C1 and C2?
163
2. In the emitter–follower below the capacitors have negligible reactance, and
RS=RL=RE=1k, =200, IE=4mA.
+VCC=9V
RB
RS
C1
C2
VS
Vin
RE
RL Vout
IE
(a) Determine the input resistance Rin and the output resistance Rout.
(Hint: First estimate RB and rbe=VT/IB).
(b) Hence use the equivalent circuit of an amplifier in Figure 14.3(b) to calculate
the ratio Vout/VS.
Further reading
1. Seeti, M.L : Basic Electronics; Makerere 2003.
2. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
164
LECTURE 15
TWO-STAGE AMPLIFIER
Introduction
In this lecture we introduce the cascading of two amplifiers and discuss the effects of
cascading amplifiers. In particular we discuss the loading effect in cascaded bipolar
junction transistor (BJT) amplifiers.
Objectives
By the end of this lecture, you should be able to:

Draw a representation of two amplifiers in cascade in terms of input and output
impedances, and open-circuit gain;

Draw a single-amplifier representation of a two-stage amplifier;

Calculate the lower cutoff frequency of a two-stage amplifier;

Show that cascading of amplifiers lowers the bandwidth of the resulting overall
amplifier;

Highlight the problems of cascading tuned BJT amplifiers.
Cascading of amplifiers
The gain provided by a single amplifier may not be sufficient for some applications. To
increase the gain, two or more amplifier stages are cascaded (i.e., the output of one
amplifier is connected as the input of the next amplifier). Although the gain is increased,
cascading also affects the bandwidth of an amplifier.
Two-stage amplifier
If we use the amplifier equivalent circuit from Lecture 14 Figure 14.3(b), we can
represent two voltage amplifiers in cascade as shown in Figure 15.1. Ri1 and R01 are the
input and output resistances of the first amplifier (Amp1) and, Ri2 and R02 are the input
and output resistances of the second amplifier (Amp2). AV1 and AV2 are the open-circuit
voltage gains of Amp1 and Amp2 respectively. We see that V1 is the output voltage of
Amp1, and at the same time it is the input voltage of Amp2.
165
Amp1
RS
VS
Amp2
R01
Vin
Ri1
R02
AV1Vin
V1
Ri2
AV2V1
Vout
RL
Fig. 15.1: Representation of two amplifiers in cascade
We can write down V1 and Vout using the potential divider rule as follows:
V1 
Ri 2
AV 1Vin
Ri 2  R01
Vout 
RL
AV 2V1
RL  R02
(15.1)
(15.2)
If we substitute V1 from equation (15.1) into equation (15.2), we obtain the expression for
the overall gain AV=Vout/Vin:
AV  AV 0
RL
RL  R02
(15.3)
where
AV 0  AV 1 AV 2
Ri 2
Ri 2  R01
166
(15.4)
From equation (15.3) we see that in the limit as RL, AV becomes AV0. Therefore AV0
is the “open-circuit voltage gain.” This can also be seen directly from figure 15.1 by
 Ri 2

AV 1Vin  ,
removing RL (i.e., letting RL=), in which case Vout  AV 2V1  AV 2 
 Ri 2  R01

which gives AV 
Vout
Ri 2
 AV 1 AV 2
 AV 0 .
Vin
Ri 2  R01
From Figure 15.1 we note that the input resistance of the overall amplifier is equal to the
input of the first amplifier (Amp1), and the output resistance of the overall amplifier is
equal to the output of the second amplifier (Amp2). If we combine these facts together
with equation (15.3) we can obtain a single amplifier representation of the two-stage
amplifier as shown in Figure 15.2.
Overall amp
RS
VS
R02
Vin
Rin
AV0Vin
Vout
RL
Fig. 15.2: Single-amplifier representation of the two-stage
amplifier of Figure 15.1
As an example suppose that the two amplifiers are identical. If the amplifiers are
common-emitter amplifiers (see Lecture 13), then AV1=AV2-RC/rbe. The input and
167
output resistances (see Lecture, equations 14.3 and 14.6) of each amplifier are
Ri=rbe//R1//R2rbe and R0=RC//rceRC, respectively. For a transistor with =100, rbe=1k
and RC=2k, the open-circuit gain, given by equation (15.4), becomes
AV 0  AV 1 AV 2
  RC
= 
 rbe
Ri 2
Ri 2  R01
2

rbe

 rbe  RC
  100  2  1
=
13,300

1

 1 2
2
This means that an input of 1mV will produce an open-circuit voltage of about 13V.
When the amplifier is loaded, the output voltage will be given by equation (15.3). The
gain calculated above should remain constant over a range of frequencies, namely, the
lower and upper cutoff frequencies. The cutoff frequencies are determined by the
response of the devices (e.g. BJT) used in the amplifier and the reactive elements used in
conjunction with the amplifier. Figure 15.3 shows two capacitors C1 and C2 connected to
an amplifier of input resistance Ri, output resistance R0 and load resistance RL.
C1
C2
AMP
Vin
Vout
Ri
RL
R0
Fig. 15.3: Capacitors forming high-pass filters
168
We see that C1 and C2 form highpass filters with cutoff frequencies 1=1/C1Ri and
2=1/C2RL. So the question is, what is the effective cutoff frequency when two (or even
more) highpass filters are cascaded?
Two highpass filters in cascade
From Lecture 10, equation (10.23), we can write down the transfer function of the
highpass filter (HPF) as
A( f ) 
1
f
1 j C
f
(15.5)
where fC is the cutoff frequency. Therefore if we have two highpass filters in cascade, the
transfer function of the resulting (or overall) HPF is given by
A  A1 A2 
1

f 
f 
1  j 1 1  j 2 
f 
f 

(15.6)
where f1 and f2 are the cutoff frequencies of the two highpass filters. To determine the
cutoff frequency of the overall HPF, we use the definition of the 3dB cutoff frequency,
namely, that at the cutoff frequency the magnitude of A is reduced to 1 / 2 of the
maximum magnitude. Since the maximum magnitude of A is unity, we set A  1 / 2 .
This yields a quadratic equation in f2:


f 4  f1  f 2 f 2  f1 f 2  0
2
2
2
2
If we solve this equation, e.g. by setting x=f2, we get


x 2  f1  f 2 x  f1 f 2  0
2
2
2
or
169
2
(15.7)
x
1 2
2
2
2
4
4
 f1  f 2  6 f1 f 2  f1  f 2 


2
Finally, we omit the negative value for x, and get
f2
1 2
2
2
2
4
4
 f1  f 2  6 f1 f 2  f1  f 2 


2
(15.8)
For the special case that f1=f2=f0, equation (15.8) gives the overall cutoff frequency fC as:
fC 
2  1 f 0  1.55 f 0
(15.9)
We see that the cutoff frequency has increased. This as a result reduces the bandwidth.
Two lowpass filters in cascade
For two lowpass filters (see Lecture 10) of cutoff frequencies f1 and f2, equation (15.6)
becomes
A  A1 A2 
Again we set
1

f 
f 
1  j 1  j 
f1 
f2 

(15.10)
A  1 / 2 at the cutoff frequency of the overall lowpass filter (LPF), we
get the equivalency of equation (15.7):


f 4  f1  f 2 f 2  f1 f 2  0
2
2
2
2
(15.11)
Solving for f2 and remembering that f is real, we get
f2


1
2
2
2
2
4
4
 f1  f 2  6 f1 f 2  f1  f 2 


2
(15.12)
For the special case that f1=f2=f0, equation (15.12) gives the overall cutoff frequency fC
as:
fC 
2  1 f 0  0.64 f 0
170
(15.13)
We see that the cutoff frequency has decreased. This leads to a reduction of the
bandwidth.
Whereas the lower cutoff frequency of a BJT amplifier is determined by the highpass
filters, the upper cutoff frequency is determined by lowpass filters. In a BJT amplifier
lowpass filters are formed by diffusion capacitors of the base-emitter and base-collector
junctions. The two capacitors (Cbe and Cbc) are part of the high-frequency small-signal
equivalent circuit of a BJT.
Tuned amplifiers
Tuned (or frequency-selective) amplifiers amplify signals of only certain predetermined
frequencies. They are commonly used in communication circuits such as radio and TV. A
single-stage tuned BJT amplifier may be obtained from the common-emitter amplifier
(see Lecture 13) by replacing the collector resistor RC with a tuned (or tank) circuit
containing an inductor L and a capacitor C. Figure 15.4 shows the single-stage tuned BJT
amplifier.
+VCC
C
L
R1
C
C1
B
C2
E
Vin
R2
RE
CE
Vout
Fig. 15.4: Single-stage tuned BJT amplifier
171
Just like we saw in Lecture 13, R1, R2 and RE establish the dc bias conditions. Capacitors
C1 and C2 provide dc isolation between the source and load, respectively; CE is the bypass
capacitor. The three capacitors C1, C2 and CE are large enough to be effective short
circuits at the signal frequencies of interest, so that they do not appear in the small-signal
equivalent circuit.
Figure 15.5 shows the small-signal equivalent circuit of the tuned amplifier in Figure
15.4. We represent the inductor by an ideal inductor in series with a resistance r, which
accounts for the dc resistance of the actual coil. We also take the tank circuit (the parallel
connection of L and C) as the load of the amplifier.
B
C
ib
ib
L
L
Vin
R1
R2
rbe
rce
Vout
C
r
E
Fig. 15.5: Small-signal equivalent circuit of the tuned amplifier in Figure 15.4
We can use Figure 15.5 to find the input resistance Ri, the output resistance Rout and the
open-circuit gain AV0. These are given by:
Ri=R1//R2//rbe
172
(15.14)
R0=rce
AV 0 
(15.15)
 rce
rbe
(15.16)
The load impedance ZL consists of the tank circuit:
Z L  r  jL  //
1
jC
or
ZL 
 0  0  jQ r

02   2  j 0
(15.17)
Q
where  0  1 / LC is the resonance frequency and Q   0 L / r  1 /  0 rC is the Qfactor of the coil. At resonance the load impedance ZL becomes
Z L ( 0 )  Q(Q  j )r
(15.18)
We see that for Q>>1, Z L ( 0 )  rQ 2 . That is, the impedance at resonance is purely
resistive.
When tuned BJT amplifiers are cascaded, the small input impedance (Ri=rbe) of the
second stage is placed in parallel with the output of the first stage. The input impedance
of a BJT amplifier in the tuned circuit is extremely low, and the loading would destroy
any selectivity of the amplifier. To prevent this loading effect in BJT amplifiers, several
methods are available. One method uses a matching transformer, which raises the
effective impedance seen by the tuned circuit. However, the interstage matching
transformer is rather costly. Another method for minimizing the loading effect uses
tapped inductors, and a third method uses tapped capacitors. The three methods are
illustrated in Figures 15.6 to 15.8. Ri2 represents the input impedance of the second stage
of a two-stage amplifier (see Figure 15.1).
173
+VCC
C
L
R1
n1:n2
C1
Ri2
Vin
R2
RE
CE
Fig. 15.6: Impedance matching with an interstate transformer (n1>>n2)
+VCC
C2
C
R1
L1
L2
C1
Ri2
Vin
R2
RE
CE
Fig. 15.7: Impedance matching with tapped inductors.
174
+VCC
Cy
L
R1
Cx
C1
Ri2
Vin
R2
RE
CE
Fig. 15.8: Impedance matching with tapped capacitors
Questions
20. (a) What is meant by “amplifiers connected in cascade?”
(b) Show that the gain A of two amplifiers of gains A1 and A2 connected in
cascade is given by A= A1A2.
(c) What is meant by “open-loop gain?”
21. Two RC highpass filters with time constants R1C1 and R2C2 are connected in
cascade. If R1=1k, C1=8F, R2=500, C2=10F, determine the cutoff frequency
of the overall highpass filter. [Ans: fc2.043f141Hz, f1=1/2R1C120Hz]
175
22. A BJT amplifier shown in the circuit below has R 1=150, R2=100k, RE=1.5k
and RC=4.7k. The transistor parameters at the operating point are found to be:
rbe=1k, rce=50k and =50.
+VCC
RC
R1
C2
C1
Vin
R2
RE
CE
Vout
(a) Determine the input resistance Ri, the output resistance R0 and the open-circuit
voltage gain AV0. [Ans: Ri=1k, R0=4.3k, AV0=-215]
(b) Draw a representation of the amplifier in terms of Ri, R0, AV0, Vin and Vout.
(c) Two identical amplifiers similar to the one above are cascaded.
(i)
Draw a representation of the resulting amplifier in terms of Ri1, Ri2,
R01, R02, AV01, AV02, Vin and Vout.
(ii)
What is the input resistance of the amplifier? What is the output
resistance? [Ans: Ri=1k, R0=4.3k]
(iii)
Calculate the open-circuit loop gain of the amplifier.
[Ans:AV046,000]
23. (a) What is a tuned amplifier?
(b) Draw a circuit of a tuned BJT amplifier using an LC-tank.
176
(d) What problem is encountered if amplifiers of the type as in (b) are coupled
and how can this problem be minimized?
Further Reading
5. Seeti, M.L.: Basic Electronics; Makerere 2003.
6. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
177
LECTURE 16
FIELD EFFECT TRANSISTORS
Introduction
In this lecture we introduce the field effect transistor (FET) by first looking at its structure
and then its current-voltage characteristics. The small-signal equivalent circuit is derived
and FET amplifiers discussed .
Objectives
By the end of this lecture, you should be able to:

Distinguish between a junction bipolar transistor (JBT) and a junction field effect
transistor (JFET);

Explain the operation of a JFET;

Distinguish between n-channel and p-channel JFET;

Draw the current-voltage characteristics of JFETs;

Distinguish between a JFET and a MOSFET (metal oxide semiconductor FET);

Draw the small-signal equivalent circuit of a JFET;

Calculate the voltage gain of a JFET amplifier;

Compare a BJT and a JFET amplifier.
Structure of a junction field effect transistor(JFET)
The junction field effect transistor consists of a single pn-junction formed by a very
narrow region of p-type (or n-type) diffused around a region of n-type (or p-type) called
the channel Figure 16.1 shows the two JFET types and their circuit symbols. The channel
has two terminal attached to its ends, the drain(D) and the source(S). the narrow region
around the channel is called the gate(G).
178
Operation of a JFET
Just like we restricted our discussion to npn-type of transistors while discussing bipolar
transistors, we confine our discussion here to the n-channel JFET noting that the
operation of the p-type JFET is completely analogous to that of the n-channel.
Under normal operation we make a current flow from the drain(D) to the source(S) by
applying a potential between the two terminals as shown in Figure 16.2.
D
G
p
D
n
p
G
G
n
S
p
n
S
D
D
G
G
S
S
(a) n-channel JFET
(b) p-channel JFET
Fig.16.1: Types of JFET; structures and their circuit symbols.
179
G
ID>0
D
G
VGS
VDS>0
>0
S
Fig. 16.2: Current and voltages of a JFET
The drain current ID is controlled by applying a reverse-biasing voltage VGS between the
gate and source. As a result of the reverse bias between the gate and source, a depletion
region extends into the channel. If VDS is positive, the net reverse bias on the pn-junction
near the drain end of the channel is larger than it is near the source end, because the net
voltage between drain and gate is given by VDG=VDS-VGS=VDG+ VGS . Thus, the
depletion region extends deeper into the channel toward the drain end of the channel, as
shown in Figure 16.3.
180
D
n
W
G
p
p
+
VDS
VGS
+
n
S
= Depletion region
Fig.: 16.3: Normal operation of an n-channel JFET
Increasing the reverse bias voltage between gate and source causes the volume of the
channel to decrease, thus increasing the channel resistance which in turn causes the drain
current ID to decrease. If the gate s made increasingly negative, then eventually the
depletion region cuts off the channel, making ID practically zero and the channel
resistance extremely high. This occurs at a gate voltage VP called the pinchoff voltage.
Since the gate-source junction is reverse-biased, no gate current effectively flows (IG0).
The JFET is characterized by a high gate-to-source (or input) impedance (typically 108
or 100M).
181
I-V Characteristics of a JFET
A plot of drain current ID against VDS for different values of gate voltage VGS gives the
output characteristics shown in Figure 16.4(b).
ID
ID
VDS=VGS-VP
VGS=0
IDSS
VGS<0
VGS=VP
VP
0
VGS
0
(a)
VDS
(b)
Fig. 16.4: I-V characteristics of a JFET: (a) Transfer characteristics,
(b) Output characteristics.
The output characteristics have a linear region to the left of the dotted curve where
VDS=VGS-VP and a saturation region to the right of the dotted curve where the current is
constant. If the gate-source voltage is zero, the channel width W reaches its minimum
(we say the channel is pinched off) when VDS=VP. The drain current under these
conditions is called the saturation drain current IDSS.
182
Figure 16.4(a) shows the graphs of ID against VGS, called the transfer characteristics. Note
there are no input characteristics since there is no gate current. For voltages between 0
and VP the drain current can be approximated by the parabola equation
 V
I D  I DSS 1  GS
VP




2
(16.1)
The output characteristics of a p-channel JFET are similar to those in Figure 16.4(b)
except that ID and VDS are negative while VGS is now positive.
Biasing the JFET
JFET circuits are very similar to those for BJT. Since the gate current is zero we can
employ the self-bias circuit as shown in Figure 16.5.
+VDD
RD
ID
D
G
S
RD
ID
RS
Fig. 16.5: Self-bias circuit of a JFET
183
The gate bias is provided by the potential drop across RS, namely
VGS   I D RS
(16.2)
called the bias curve equation. The load line equation is given by
I D RD  RS   VDS  VDD
(16.3)
Equations (16.1) to (16.3) may be used to fix the operating point and determine the circuit
components RS and RD. The value for the saturation drain current IDSS and the pinchoff
current VP are usually specified by the manufacturer in a range. The self-bias circuit in
Figure 16.5 is not flexible enough to accommodate such a spread in the characteristics.
The bias circuit in Figure 16.6 gives a more stable quiescent working point. The potential
divider made up of R1 and R2 provides the gate with a positive voltage VG given by
VG 
R2
VDD
R1  R2
(16.4)
and the bias curve equation, given by the gate loop equation, is
IDRS+VGS=VG
(16.5)
To make the gate-source junction reverse-biased we must have VGS<0. Therefore we
must choose IDRS>VG.
184
+VDD
R1
RD
ID
G
R2
RS
ID
Fig. 16.6: Bias circuit of a JFET
MOSFET
The second kind of FET is the insulated gate FET or commonly called the metal oxide
semiconductor field effect transistor (MOSFET). The metal oxide commonly used is a
film of silicon oxide (SiO2) which separates the gate and the channel as shown in Figure
16.7.
S
G
D
S
G
D
SiO2
n-channel
n+
n+
n+
p
n+
p
(substrate)
(substrate)
(a) Depletion-mode MOSFET
(b) Enhancement-mode MOSFET
Fig. 16.7: Basic structure of a MOSFET; n+= highly doped n-type, n= lightly doped
n-type semiconductor.
185
The silicon oxide makes the input (gate-to-source) impedance much higher than that of a
JFET, typically 1015. The depletion-mode MOSFET, illustrated in Figure 16.7(a) has a
lightly doped n-channel as compared to the highly doped drain and source wells. The
depletion-mode MOSFET may be operated with either a positive or a negative gatesource voltage. A negative gate voltage causes part of the channel to be depleted and
thereby decreasing the drain current.
The enhancement-mode MOSFET, shown in Figure 16.7(b), contains no channel between
the drain and source wells. However, applying a positive gate voltage causes an n-type
channel to be formed and thereby enhancing the number of free electrons in the region
below the gate. No channel is induced using a negative voltage.
I-V Characteristics of MOSFET
D
ID
ID
VDS=VGS-VT
VGS>0
0
G
VDS
VGS<0
S
VT
0
VGS
0
(a)
VDS
(b)
Fig. 16.8: Depletion-mode N-MOSFET: (a) Transfer characteristics, (b) Output
characteristics. Far left is the circuit symbol.
186
ID
ID
VDS=VGS-VT
D
VGS>0
G
S
VT
0
VGS
0
(a)
VDS
(b)
Fig. 16.9: Enhancement-mode N-MOSFET: (a) Transfer characteristics,
(b) Output characteristics. Far left is the circuit symbol.
Figures 16.8 and 16.9 show the transfer and output characteristics of the depletion-mode
and the enhancement-mode of the N-MOSFET (n-channel MOSFET). We note that a
drain current ID only starts to flow if the gate voltage exceeds a threshold voltage VT. The
thrashold voltage is negative for depletion-mode MOSFETs and positive for
enhancement-mode MOSFETs. The dotted curves are the loci of the pinchoff points
given by VDS=VGS-VT. The channel is said to be pinchedoff when VGS-VDS=VT (the drain
current is not cut off). On the far left side of Figures 16.8 and 16.9 are shown the circuit
symbols of the depletion-mode and enhancement-mode N-MOSFETs. As with the JFET,
the arrow indicates that the MOSFETs are n-chanel type. The gate is symbolically
separated separated from the chanel to indicate the idea of insulated gate. The circuit
symbols for P-MOSFETs are obtained by reversing all the arrows in the above symbols
187
in Figures 16.8 and 16.9. The terminal with the arrow in a MOSFET may regarded as a
fourth terminal connected to the substrate of the MOSFET.
Biasing of MOSFETs
The biasing circuits of the JFET shown in Figures 16.5 and 16.6 may also be used for
biasing a MOSFET. We only need to remember that VGS can be either negative or
positive for a depletion-mode N-MOSFET and must be positive for an enhancementmode N-MOSFET. For a positive gate-source voltage we may even leave out RS (i.e.
source grounded). Note also that the depletion-mode MOSFET may be operated with
VGS=0 (see Figure 16.8). The analysis and design of MOSFET biasing circuits is almost
identical to that for the JFET. Therefore we can use the same methods and procedures for
the MOSFET circuits.
Small-signal equivalent circuit of a JFET
We note the absence of the gate current (IG=0), which is one of the most important
advantages of FET over BJT, and consider the drain current ID as a function of VGS and
VDS. We can then write a small change in ID as
 I

 I

I D   D  VGS   D  VDS
 VGS V
 VDS V
DS
GS
or if we let the small changes
I D  id , VGS  Vgs and VDS  Vds
then
Vds
rds
(16.6)


VDS
(16.7)
id  g mV gs 
where
 I
g m   D
 VGS
188
 V
rds   DS
 I D


VGS
(16.8)
gm is called the ttransconductance and rds is the output resistance (impedance in general).
In addition we define the amplification  of the FET by
  g m rds
(16.9)
The tansconductance and the output impedance of a FET may be obtained from the
transfer and output characteristics of the FET in a manner similar to that used for the BJT
in Lecture 12.
Equation (16.6) may be rewritten with use of equation (16.9) as
id rds  Vgs  Vds
(16.10)
Equations (16.6) and (16.10) yield the two FET small-signal equivalent circuits in Figure
16.10.
rds
G
D id
G
D id
gmVGS
VGS
rds
VDS
VGS
S
VGS
VDS
S
(a)
(b)
Fig. 16.10: JFET small-signal equivalent circuit: (a) using a voltage-dependent
current source gmVGS, (b) using a voltage-dependent voltage source VGS.
189
The input impedance rgs of the FET has been assumed to be infinite. The above smallsignal equivalent circuit is only valid for low frequencies. For high frequencies FETs
exhibit capacitive effects that must be accounted for in the small-signal equivalent circuit.
FET amplifiers
Figure 16.11 shows a single-stage common-source amplifier.
+VDD
R1
RD
C2
C1
+
Vin
R2
RS
Vout
CS
Fig. 16.11: Single-stage JFET amplifier.
If we compare this amplifier with the single-stage common-emitter amplifier in Figure
13.3, we see obvious basic similarities between the FET and BJT amplifiers. The
procedure of determining the properties of the FET amplifier is essentially the same as
for BJT amplifier.
Source follower
Figure 16.12 shows the basic circuit of a source follower (or common-drain amplifier).
190
+VDD
C1
Vin
RG
RS
Vout
Fig. 16.12: Source follower
Analysis using the small-signal FET model gives the voltage gain AV=Vout/Vin1,
assuming that
1
 RS  rds . The input resistance Rin=RG, which is very large, e.g.
gm
1M, and the output resistance Rout  RS //
1
1
.

gm gm
FET as a constant-current source
Figure 16.13 shows the basic circuit of a current source.
ID
+
D
S
RS
VGS
G
Fig. 16.13: Constant-current source using a FET.
191
The circuit may be analyzed using the FET small-signal equivalent circuit of Figure
16.10(b). The internal resistance of the current source is given by Ri 
VDG
. It turns out
ID
to be
Ri  1   RS  rds
 RS  rds
 RS
Now if we use equation (16.1), we see that for a given drain current ID, the gate-source
voltage is given by

ID
VGS  1 
I DSS


VP


But from Figure 16.13, VGS=-IDRS. Therefore
RS 
VGS
ID

ID
= 1 
I DSS

 VP

I
 D
This gives an adjustable constant-current source, adjustable through RS. The current,
however, must be less than the drain saturation current IDSS. It is equal to IDSS if RS=0.
192
Questions
1. An n-channel JFET with a saturation current IDSS=6mA and pinchoff voltage VP=6V is used in the self-bias circuit of Figure 16.5. given that VDD=12V, RD=1.5k
and RS=500, determine the operating point (determine ID, VDS and VGS) and the
transconductance of the transistor.
[Ans: ID=3.2mA; VDS=5.6V; VGS=-1.6V; gm=1.5mS]
2.
The biasing circuit in Figure 16.6 has the following circuit values: VDD=18V,
R1=300k, R2=150k, RD=500, and RS=4k. If the n-channel JFET has
IDSS=8mA and VP=-4V, determine the operating point.
[Ans: ID=2mA; VDS=9V; VGS=-2V]
3. Repeat question 2 by a graphical method as follows:
(a) Plot the graphs of ID=IDSS(1-VGS/VP)2 and IDRS+VGS=VG on the same
axes, where VG is the p.d. across R2. Hence deduce IDQ and VGSQ, the
values of ID and VGS at the quiescent (or working) point Q.
(b) Plot the graphs of ID(RD+RS)+VDS=VDD and ID=IDQ on the same axes.
Hence deduce VDSQ.
Further Reading
7. Seeti, M.L.: Basic Electronics; Makerere 2003.
8. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
193
LECTURE 17
FEEDBACK
Introduction
In this lecture feedback is defined and the gain of a feedback amplifier is derived. The
difference between positive and negative feedback is explained and examples are given.
Applications of positive and negative feedback are given by examples.
Objectives
By the end of this lecture, you should be able to:

Define positive and negative feedback;

Derive the formula for the gain of a feedback amplifier;

Calculate the input and output impedance of a feedback amplifier;

Name applications of positive feedback;

Name advantages of use of negative feedback in amplifiers.
Feedback
In a circuit having feedback, part or all of the output signal is diverted and applied at the
input, through a feedback circuit. The diverted signal applied at the input can either be
added to or subtracted from the input signal. Figure 17.1 shows a general block diagram
of the principle of feedback.
194
Amp with feedback
Amp
M
V1
Vin
A
Vout
 kVout
Feedbak
k
kVout
Fig. 17.1: General principle of feedback
The amplifier (Amp) without feedback has a gain A, also known as the open-loop gain.
The feedback circuit has a transfer function k, also called the feedback factor or fraction.
M is a mixer which combines (adds) the input signal Vin and the feedback signal kVout,
from the output of the feedback circuit, to produce the signal V1. The signal kVout can be
positive or negative, and hence the  signs. This means that kVout is either added to or
subtracted from Vin.
V1  Vin  kVout
(17.1)
The  signs are determined primarily by the feedback circuit. The plus sign determines
positive feedback and the negative sign determines negative feedback. Now from the amp
without feedback the gain A is defined by
Vout  AV1
195
(17.2)
The gain A of the amplifier with feedback is defined by A =Vout/Vin. If we substitute
for V1 in equation (17.2) from equation (17.1), we get A to be
A 
A
1  kA
(17.3)
The negative sign refers to positive feedback while the negative sign refers to negative
feedback.
Positive feedback and oscillators
For positive feedback the gain of the amplifier is given by A =A/(1-kA), as seen from
equation (17.3). If the denominator (1-kA) becomes very small (tends to zero), the gain
A becomes very large (infinite). In amplifiers, positive feedback is undesirable because
it usually causes the amplifier to become unstable and oscillate. However, positive
feedback is utilized fully in oscillator circuits.
Oscillators are basic electronic circuits, which have no ac input but provide an ac output
at a specific frequency. In other words, a portion of the output signal is used as the input
signal. The conditions for oscillation of an oscillator circuit may be obtained from the
positive feedback equation, namely
A 
A
1  kA
If the circuit is to oscillate, the gain must be infinite. This means that 1  kA  0 or
kA  1
196
(17.5)
In addition to this condition, we must have that the phase angle of the phasor kA (the
loop gain) is zero or a multiple of 3600 (to ensure that the negative sign does not change).
kA  2n , n=0,1,2,…
(17.6)
Equation (17.5) is called the amplitude condition and equation (17.5) is called the phase
condition for oscillations to occur. Note that kVout=kAV1 (see Figure 17.1) so that
kA=Vout/V1. Therefore the phase condition in equation (17.6) means that the two
signals, one at the output of the feedback circuit and the other at the input of the amplifier
without feedback must be in phase. The two conditions in equations (17.5) and (17.6)
together form the so-called Barkhausen criterion for oscillations to be sustained.
As an example let us look at the phase shift oscillator. Figure 17.2 shows a BJT RC-phase
shift oscillator.
+VCC
R1
RC
C
Vout
C
C
C
B
VB
E
R
R
R
RE
CE
Fig. 17.2: BJT RC-Phase shift oscillator
197
Amp
AV
B
C
Feedback
C
C
C
VB
Vout
R
R
R
Fig. 17 3: Block diagram representation of the phase shift oscillator
Apart from the network of resistors R and capacitors C, the rest of the circuit looks like
the common-emitter amplifier we met in Lecture 13. Its gain is given by
AV=(RC//rce)/rbe. The network of resistors R and capacitors C form the feedback circuit
as indicated in Figure 17.3. the feedback factor k is given by k=VB/Vout. VB is the
potential at the base(B) of the transistor where the feedback takes place. Now from Figure
17.3, VB=kVout and Vout=AVVB. Therefore (1-kAV)Vout=0. If we assume that Vout  0 ,
then we must have that
kAV=1 or k=1/AV
Since AV is real, k must also be real. It remains to find k. It is left as an exercise to show
that
198
1
5
1
6 

 1  2 2 2  j 3 3 3 

k
RC 
 R C
 R C
(17.7)
It follows from equation (17.7) that k is real if the imaginary part on the right hand side is
identically equal to zero. This gives the frequency of oscillation 0 as
 0  2f 0 
1
RC 6
(17.8)
Negative feedback
For negative feedback the gain of the amplifier is given by A 
A
, as can be seen
1  kA
from equation (17.3). We see that if 1+kA is less than 1 we have positive feedback,
therefore we define negative feedback for 1+kA greater than 1. Usually the open-oop
gain absolute value A is much greater than 1, so that A  k , and the feedback gain
can be approximated by
A 
1
k
(17.9)
We can see Figure 17.1 that the apparent input signal to the original amplifier is reduced,
and thus the output is reduced accordingly. Negative feedback amplifiers are typically
characterized as having lower gain than the same amplifier without feedback. There are
several advantages in using negative feedback in amplifiers. It can be used to:

Stabilize the gain (gain is independent of the device parameters);

Raise or lower the input or output impedance;

Broaden the bandwidth;
199

Reduce noise (including thermal effects);

Achieve a more linear operation (less distortion).
Types of feedback can be classified according to the action of the feedback on the gain.
Two types are current feedback and voltage feedback circuits; both are characterized by a
decrease in gain. Two other types of feedback are the series- and shunt-feedback. In a
series-feed back circuit, the output current is sampled and fed back to the input as a
voltage. The connection is also called a voltage-series feedback amplifier. In a shuntfeedback circuit, the output voltage is sampled and fed back to the input in form of a
current.
Example 1: Series feedback
Figure 17.4(a) shows an example of a series feedback amplifier. Figure 17.4(b) shows the
small signal equivalent circuit of the amplifier.
+VCC
ibrce
rbe
R1
RC
B
rce
E
C
ib
Vout
Vin
Vin
R2
RP
RE
RC
Vout
RE
(a)
(b)
Fig. 17.4: Example of a series-feedback amplifier: (a) Cicuit, (b) smallsignal equivalent circuit (RP=R1//R2).
200
For the amplifier without feedback (RE=0), we get (see Lectures 13 and 14):
Ri=RP//rberbe, RP>>rbe
R0=RC//rceRC, rce>>RC
AV 
-  RC // rce   RC


rbe
rbe
With feedback we use the equivalent circuit in Figure 17.4(b) to determine the
corresponding quantities Ri , R0 and AV :
R i  rbe  RE
R 0  RC
A V 
 RC
RE
For a numerical example, suppose that the circuit values are known as follows:
R1=R2=100k, RC=3k, RE=1.2k, =100, rbe=1k and rce=100k. Then it follows that
Ri=1k, Ri =120k
R0=3k, R0 =3k
AV=-300, AV =-2.5
We see that the negative feedback has raised the input resistance(Ri) and lowered the
voltage gain(AV). The output resistance(R0) has remained the same.
201
Example 2: Shunt feedback
Figure 17.5(a) shows an example of a shunt-feedback amplifier. Figure 17.5(b) shows the
small-signal equivalent circuit of the amplifier.
+VCC
RB
RC
B
C
RB
C
Vin
B
Vout
ib
Vin
rbe
rce RC
Vout
ib
E
E
(a)
(b)
Fig. 17.5: Example of a shunt-feedback amplifier: (a) Circuit, (b) smallsignal equivalent circuit.
For the amplifier without feedback (RB=), the results are the same as in example 1,
namely:
202
Rirbe, R0RC, AV 
 RC
.
rbe
With feedback we use the small-signal equivalent circuit in Figure 17.5(b) to determine
Ri , R0 and AV :
To find Ri we first combine RC and rce into RC =RC//rce and then convert the current
source ib into a voltage source ib RC having a series internal resistance RC . The
resulting circuit is shown in Figure 17.6, where RC and RB have been combined into a
series resistance RB+ RC .
RB+ RC
B
i1
RB
i1-ib
B
C
ib
Vin
Vin
rbe
rbe
rce
ib
ibrce
RC Vout
ib RC
E
E
(a)
(b)
Fig. 17.6: Small-signal equivalent circuits for the shunt-feedback amplifier in
Figure 17.5: (a) Determination of the input resistance, (b) determination
of the voltage gain.
203
Since Vin lies across rbe, then ib=Vin/rbe. Taking the outer loop containing the two voltage
sources and the resistor RB+ RC , the loop equation gives the input resistance Ri =Vin/i1,
Ri 
RB  RC rbe
RC
where we have assumed that rce>>RC.
To calculate the voltage gain AV =Vout/Vin, we convert the current source in Figure
17.5(b) into a voltage source ibrce having a series internal resistance rce. The resulting
circuit is shown in Figure 17.6(b). The use of loop equations gives the following result:
AV 
 RC
rbe
The output resistance R0 can be obtained from the circuit in Figure 17.6(b) by shorting
Vin (i.e. letting Vin=0) and proceeding as discussed in Lecture 14(see Figure 14.4 and
equation 14.6). We find that
R0  RB // RC // rce  RB // RC .
Questions
1. (a) What is feedback?
(b) Differentiate between positive feedback and negative feedback
(c) Derive an expression for the gain A of an amplifier with feedback in terms of
the gain A of the amplifier without feedback and the feedback factor k.
2. (a) What is meant by the following: (i) open-loop gain, (ii) closed loop gain.
204
(b) How is positive feedback used in oscillator circuits?
3. (a) What are the advantages of negative feedback in amplifiers?
(b) The feedback amplifier shown in Figure 17.4(a) is constructed with
R1=R2=100k, RC=1k, and RE=500. The transistor parameters are: rbe=1k,
=80, and rce=60k. Determine the input and output resistances as well as the
voltage gain of the amplifier. [Ans: Rin=RE=40k, R0=RC//rce1k, AV=-2]
4. Repeat question 3(b) if the output voltage is taken across the emitter resistor RE.
[Ans: Rin=RE=40k, R0=rbe//RE 330, AV=1]
Further Reading
9. Seeti, M.L.: Basic Electronics; Makerere 2003.
10. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
205
LECTURE 18
OPERATIONAL AMPLIFIERS
Introduction
In this lecture we introduce integrated circuit (IC) operational amplifiers. We discuss the
assumptions of an ideal operational amplifier and use these assumptions to derive the
expression for the output voltage of some basic operational amplifier circuits.
Objectives
By the end of this lecture you should be able to:

Draw the circuit symbol of an operational amplifier (op-amp);

Explain the terms inverting and non-inverting inputs;

Draw the circuit of an inverting, a non-inverting and a summing amp;

Derive the expression for the output of an inverting, a non-inverting and a summing
amp;

Draw the circuit of an integrator and a differentiator;

Derive the expression for the output of an integrator and a differentiator.
Operational amplifier
Figure 18.1 shows the circuit symbol of an operational amplifier (op-amp).
V+
VN
Vout
VP
+
V-
Fig. 18.1: Circuit symbol of an op-amp.
206
The op-amp has two inputs; the inverting input, indicated by a negative sign, and the noninverting input, indicated by a positive sign. It has two power supplies, a positive one V+
and a negative one V-. However, the power supplies are not usually shown on the circuit
symbol. The difference
VD=Vp-VN
(18.1)
is called the differential input of the op-amp, where VP and VN are the voltages at the
non-inverting and inverting inputs respectively. The again (or differential gain AD of the
amplifier is defined by
AD 
Vout
VD
(18.2)
where Vout is the output voltage of the amplifier.
We also define the input impedance Zin and output impedance Zout of the op-amp. These
two quantities are shown in the equivalent circuit of an op-amp in figure 18.2.
Op-amp
+
Zout
VP
VD
Zin
ADVD
Vout
VN
-
Fig. 18.2: Equivalent circuit of an op-amp
207
RL
The input impedance Zin is defined between the two inputs and the output voltage Vout is
referenced to ground (also VP and VN are measured with respect to ground).
Ideal op-amp
An ideal ap-amp has the following characteristics:
1. Infinite gain
The differential gain AD is very large, typically 105, so that it can be considered
infinite (AD=). The consequence of this assumption can be seen from equation
(18.2) by writing VD=Vout/AD. We see that VD=0 or VP=VN, when AD is
infinite. This means that the two inputs have the same potential.
2. Infinite input impedance
The input impedance of an op-amp is very large, typically of the order of 1012, so
that it can be considered infinite (Zin=). The consequence of this can be seen
from figure 18.2. There is no current flowing into either of the two input
terminals.
3. Zero output impedance
The output impedance of a op-amp is very small (compared to the load), so that
we can write Zout=0. We see from figure 18.2 that if Zout=0, then Vout=ADVD, so
that all the amplified differential input is delivered to the load.
The above three are the most important assumptions of an ideal op-amp. We shall be
using these assumptions in most circuits involving op-amps.
208
The inverting amp
Figure 18.3 shows the basic circuit of the inverting amp. The input is applied to the
inverting input (via resistor R1) and the non-inverting input is grounded. The circuit
forms a feedback amplifier through the feedback resistor RF. We need to find the gain
A=Vout/Vin.
iF
i1
R1
RF
VN
-
Vin
VP
+
Vout
Fig. 18.3: The inverting amp
We assume that the op-amp is ideal. This means that no current enters or leaves the inputs
of the op-amp, so that the only currents at node N (the inverting input) are i1 and iF as
shown in the diagram. Therefore a node equation gives
i1+iF=0
or
Vin  VN Vout  VN

0
R1
RF
The second assumption we use is that of infinite gain of the differential gain of the op-
209
amp. This means that VN=Vp. But since Vp=0, then VN=0 also. Substituting for VN=0 in
the node equation yields.
A
Vout  RF

Vin
R1
(18.3)
Because of the negative sign in equation (18.3), the amplifier is known as an inverting
amplifier.
The non-inverting amp
Figure 18.4 shows the basic circuit of the non-inverting amplifier. The input is applied to
the non-inverting input of the op-amp.
Vin
+
Vout
RF
VN
R1
Fig. 18.4: Non-inverting amp
210
We see that R1 and RF form a potential divider, since no current enters or leaves the input
of an ideal op-amp. Therefore by use of the potential divider rule we can write down the
potential VN at he inverting input
VN 
R1
Vout
R1  RF
Also for an ideal op-amp Vp=VN. Therefore since VP=Vin we finally have the gain
A=Vout/Vin
A  1
RF
R1
(18.4)
The input and output voltages are in phase, and hence the name non-inverting amp. We
note from equation (18.4) that for RF=0, the output follows the input (voltage–follower).
The summing amp
If we modify the inverting amp in figure 18.3 by adding more input voltages, we get the
summing amp circuit in figure 18.5.
In analysing the summing amp we proceed as we did for the inverting amp. Since the opamp is ideal we must have that
i1+i2+….+in=0
or
V1 V2
V V

   n  out  0
R1 R2
Rn RF
iF
211
RF
R1
i1
V1
-
R2
i2
V2
Vout
+
.
.
.
.
.
.
.
Rn
in
Vn
Fig. 18. 5: Summing amp
Again we have used the fact that VN=Vp for an ideal op-amp, and since Vp=0, we also
have VN=0. We say that the inverting input is on virtual ground, so that IF= (VoutVN)/RF=Vout/RF. We therefore get for the output Vout:
n
RF
Vk
k 1 Rk
Vout  
(18.5)
Differentiator and Integrator
If we replace the resistor R1 in the inverting amp in figure 18.3 with a capacitor C, we get
a differentiating circuit. Referring to the labels in figure 18.3, the capacitor current i 1
212
becomes i1=CVin, and since iF=Vout/RF, we get CVin  Vout / RF  0 or
Vout   RF C
dVin
dt
(18.6)
If instead of replacing R1, we replace RF with a capacitor C, we get an integrating circuit.
In this case iF becomes iF = C Vout . This together with i1=Vin/R1 gives Vin/R1 + C Vout =0,
or with R1=R
Vout 
1
Vin (t )dt
RC 
(18.7)
Questions
1. (a) Draw the circuit symbol of an op-amp and label the following:
(i)the output voltage Vo,
(ii)the non-inverting input (+) with potential Vp,
(iii)the inverting input (-) with potential VN.
(b)Define the differential input VD in terms of Vp and VN.
(c)Define the closed-loop gain A in terms of VD and the open-loop gain AD.
(d)List the most important assumptions of an ideal op-amp and briefly explain the
consequences of each in simplifying the op-amp equivalent circuit.
2. The op-amp in figure 18.6 is ideal.
(a)Show that Vout 
R3 ( R1  R4 )
R
V2  4 V1
R1 ( R2  R3 )
R1
(b)If R2=R1=1k, R3=R4=10k, V1=-1.0V (d.c.) and V2=0.1sin0t, sketch Vout(t) for
at least one cycle.
213
R4
i1
R1
V1
i2
R2
V2
Vout
+
R3
Fig. 18.6
3. (a) Draw the circuit of a differentiator using an ideal op-amp, a resistor R and a
capacitor C.
(b) Derive the expression for the output Vout in terms of the input Vin, R and C.
4. (a) Draw the circuit of an integrator using an ideal op-amp, a resistor R and a
capacitor C.
(b) Derive the expression for the output Vout in terms of the input Vin, R and C.
Further reading
Seeti, M.L: Basic Electronics
214
LECTURE 19
DC POWER SUPPLIES
Introduction
In this lecture we discuss a few dc power supply practices. We start with a short
discussion on the need for dc power supplies. We then go on to look at half-wave and
full-wave rectifiers and filtering. Equations for determining the value of the filter
capacitor are presented and ripple factor is defined. The pi-section is mentioned briefly.
Objectives
By the end of this lecture you should be able to:

Determine the secondary voltage of a transformer for use in a power supply system;

Determine the filter capacitor for a given load current and ripple voltage;

Design a dual-polarity dc power supply using a center-tapped transformer and a
bridge rectifier;

Discuss the limitations of reducing the ripple voltage by increasing the value of the
filter capacitor;

Discuss the operation of a pi-section filter.
Need for dc power supply
The dc power supply is one of the most basic subsystems in electronics. Whether we are
dealing with communication, instrumentation, computers, or any electronics system,
small or large, it invariably needs a source of dc power, which is furnished by a power
supply. From simple transistor and op-amp circuits up to elaborate digital and
microprocessor systems, require one or more sources of stable dc voltage.
Elements of a power supply
Basically, the function of a power supply is to convert the readily available 50Hz/240Vrms into a specific dc voltage. The power supply, therefore, usually consists of a number
of circuits. These are the transformer, the rectifier, a filter, and a regulator. Figure 19.1
shows a block diagram of the system.
215
Fuse Transformer Rectifier
Plug
Filter
+
~
ac
-
input
Regulator
+
dc
output
-
Fig. 19.1: Elements of a dc power supply
Let us look at each of the circuits of the block diagram in detail.
Transformer
The transformer either steps up or steps down the available line voltage, depending on the
need. Secondly, the transformer isolates the electronic device being powered from actual
connection to the power line, because the windings of a transformer are electrically
insulated from each other. Power transformers (meant for use from the 240V power line)
are available in a variety of secondary voltages and currents. Typical transformers for use
in electronic instruments might have secondary voltages from 10 to 50V, with currents of
0.1 to 3A or so. The larger the voltage-current product (VA) he more expensive the
transformer.
Rectifier
The rectifier circuit converts the alternating current into unidirectional or pulsating direct
current. In Lecture 9 we learnt about half-wave and full-wave rectification. Figure 19.2
shows a full-wave bridge rectifier.
216
D4
D1
VS
V0
+
D2
D3
C
Fig. 19.2: Full-wave bridge rectifier
VS is the secondary voltage of the transformer and V0 is the rectified voltage. Remember
that VS is the rms-value of the secondary voltage (the value measured by an ac
voltmeter). Since two diodes are involved in the conduction for each halfcycle (as
discussed in Lecture 9), V0 is given approximately by
V0  2 VS  2VD
(19.1)
where VD is the diode forward-bias voltage drop, which is about 0.6V for silicon diodes.
Thus a transformer with a secondary voltage output of 10V will give a rectified voltage of
about 13.0V. The full-wave bridge rectifier circuit has become so popular that
encapsulated bridge rectifier units are available in a wide variety of current and voltage
ratings. These packages have four terminals, two for the ac input and, a plus-sign terminal
and minus-sign terminal for the dc output. They have the added advantage that the diode
forward voltages are matched to typically 10mV, permitting ripple filtering to less than
0.1V peak-to-peak on the first filter capacitor.
A disadvantage of the bridge circuit is that neither end of the transformer secondary can
be grounded. Often we wish to operate several rectifiers (e.g. a positive and a negative)
217
from a single secondary winding. This is possible with the half-wave and center-tapped
transformer design, but not with the bridge circuit.
Figure 19.3 shows positive and negative rectifiers operated from a center-tapped
transformer. The dual-polarity voltage supply is needed in many circuits, e.g. those
involving op-amps.
Transformer
D4
D1
AC
Input
VS
+V0
CT
+
D2
D3
C
C
-V0
Fig. 19.3: Dual-polarity supply using a center-tapped transformer and a bridge rectifier.
The output voltages are equal and opposite (V0) and are given by
2V0  2 VS  2VD
(19.2)
where VS is the secondary voltage between the two extreme ends of the secondary coil.
The center-tap terminal(CT) of the transformer is grounded.
218
Filter
The filter circuit removes or minimizes the ripple. Power supplies are more often required
to deliver, not pulses, but pure unfluctuating dc. The simplest filter is a capacitor
connected across the rectifier as shown in Figures 19.2 and 19.3. The capacitor together
with a load resistor across it form the RC-filter. Figure 19.4 shows the output waveforms
of a half-wave and a full-wave rectifier with a filter capacitor.
V(t)
V
Filtered output
Unfiltered output
0
T/2
T
3T/2
t
(a)
V(t)
V
Filtered output
Unfiltered output
0
T/2
T
3T/2
t
(b)
Fig. 19.4: Filtered waveforms: (a) Half-wave rectifier,
(b) Full-wave rectifier
The capacitor is first charged to the peak voltage of the transformer secondary. If we
219
assume that the rate of discharge of the capacitor is constant, then the voltage across the
capacitor changes at a rate of
V
I
 . The time t is the time between charging pulses. If
t
C
T is the period of the line voltage, then t=T for a half-wave rectifier, and t=T/2 for a fullwave rectifier. Therefore in general we can write for the filter capacitor C
C
I
f r V
(19.3)
where fr is the ripple frequency. Note that if f is the line voltage frequency (50Hz), then
fr=f for the half-wave rectifier and fr=2f for the full-wave rectifier.
Example
A power supply delivers 10V dc to a load at 20mA. If the output voltage must not drop
by more than 0.4V between charging pulses, what filter capacitor is required?
Using equation (19.3),
C
I
20  10 3
=
=1000 F
f r V 50  0.4
This is the smallest value of the capacitor for a half-wave rectifier. For a full-wave
rectifier this value is halved, since fr=2f=100Hz for a full-wave rectifier ripple.
From the above example we see that the filter capacitors are large capacitors. High value
capacitors are usually electrolytic types with polarities, which should be correctly
connected. They will short-circuit if reversed. To be able to compare power supplies in
their ability to suppress ripple, a percentage ripple specification, called the ripple factor,
is used. The ripple factor r is defined by
220
r
Vrms
Vdc
(19.4)
where Vrms is the rms-value of the ripple voltage and Vdc is the dc output of the filtered
voltage. In the above example the ripple factor is given by
r
0.4 / 2 2  or 1.4%
10
Note that we divided 0.4V by 2 2 in order to change 0.4V, which is a pea-to-peak
value, to an rms-value.
The output of the power supplies discussed above consists of an ac ripple voltage riding
on a dc voltage level. It is desirable to reduce the ripple content to the lowest possible
level in order to have a pure source of dc power. We know tat a capacitor presents a low
impedance to ac but will not pass dc and that an inductor passes dc quite readily but
presents a high impedance to ac. Using this knowledge, we can block the ac portion of
thepower supply output with a series inductor and shunt any ac that does get by to ground
through a capacitor. Figure 19.5 shows a -section filter, which uses the above principle.
The filter can be used after either a half-wave or a full-wave rectifier.
From
Rectifier
L
To load
C1
C2
Fig. 19.5: Pi-section filter
221
The capacitor C1, is determined as before using equation (19.3). To be successful this
filter must use large capacitors and inductors, so that  r L 

1
, where f r  r is
2
 r C2
the ripple frequency. In that case the output ripple voltage Vout is given by approximately
by
Vout 
Vin
4 f r LC2
2
2
(19.5)
where Vin is the ripple voltage from the rectifier. T maintain the result in equation (19.5)
we must also have that the load resistance RL is much larger than
1
1
, so that
 r C2
 r C2
dominates in the parallel combination of C2 and RL.
Example
If L=1H and C2=100F, then
1
16 and  r L 628.
 r C2
Using equation (19.5),
Vout
1 /  r C2
1
16
 2


 0.03
Vin
r L
628
 r LC2
We see that the ripple voltage reduces to about 0.03 of the original value. The condition
of the load resistance is that RL must be many times larger tan 16, e.g. 160.
222
Regulator
The regulator circuit should maintain the dc level at the output constant with varying
loads. By choosing capacitors that are sufficiently large, we can reduce the ripple voltage
to any desired level. But this method has two disadvantages. The first one is that the
required capacitor may be prohibitively bulky and expensive. The second disadvantage is
that even with the ripple reduced to negligible levels, there are still variations of the
output voltage due to other causes, e.g. input line voltage variation, changes in load
current. Therefore a better approach to power supply design is to use enough capacitance
to reduce ripple to low levels (say 10% of the dc voltage), then use an active feedback
circuit to eliminate the remaining ripple. Voltage regulators will be discussed in Lecture
20.
Load regulation
The output of an elementary power supply drops somewhat from no load to full-load
currents. This is generally undesirable and a load regulation specification is used to
compare power supplies in their ability to deliver a constant output voltage regardless of
load current. Load regulation is defined as
Load Regulation =
VOC  VL
VL
(19.6)
where VOC is the no-load (open circuit) output voltage and VL is the output under load.
The fraction is usually expressed as a percentage. The definition above for load
regulation is made with respect to a specific condition or rated current. To find an
alternative expression for load regulation let us consider Thevenin’s equivalent circuit of
the regulator as shown in Figure 19.6.
223
IL
R0
IL
REGULATOR
CIRCUIT
RL
VL

V0
RL
VL
Fig. 19.6: Thevenin’s equivalent circuit of a regulator circuit with a load RL.
The Thevenin voltage V0 is equal to VOC (the open-circuit output voltage) and the
Thevenin resistance R0 is equal to the output resistance of the regulator. From the
equivalent circuit in Figure 19.6 we can use the potential divider rule to write down VL as
VL 
RL
RL
V0 
VOC
RL  R0
RL  R0
from which we find the ratio R0/RL to be
R0 VOC
V  VL

 1  OC
RL
VL
VL
Comparing this with equation (19.6) we obtain an alternative expression for load
regulation
Load Regulation =
R0
RL
(19.7)
where R0 is the output resistance of the regulator. One of the primary characteristics of a
good regulator is low output resistance. An ideal regulator has zero output resistance.
224
Typical values for elementary power supplies range from 2 to 50%. A fair comparison of
load regulation requires that all supplies being compared be rated for the same full-load
current.
Questions
1. Figure 19.7 shows a circuit of a dc power supply.
Transformer
240V/50Hz
15V
1000F
RL=200
Fig. 19.7
Find:
(a) The peak voltage across RL.
[Ans: 20.6V]
(b) The peak-to-peak ripple voltage across RL.
[Ans: 2.1V]
(c) The percentage ripple in the output voltage.
[Ans: 10%]
(d) The average dc voltage across RL.
[Ans: 19.6V]
(e) What value of the filter capacitor would be required to make the ripple
equal to 1.0%?
[Ans: 10,000F]
2. (a) State two advantages and two disadvantage of the bridge rectifier compared to
the full-wave center-tapped circuit.
(b) Figure 19.8 shows a dc power supply using a bridge full-wave rectifier.
225
240V
12.6V
I L=50mA
50Hz
+
500F
RL
Fig. 19.8:
Find:
(a) The average dc voltage across RL.
[Ans: 16.1V]
(b) The no-load dc output voltage.
[Ans: 16.6V]
(c) The peak-to-peak ripple across RL.
[Ans: 1V]
(d) The ripple factor.
[Ans: 2.2%]
3. For a given power supply, the output voltage with no load is 25V. When a load of
100 is connected, the voltage is 24V. What is the percentage regulation and
what is the output resistance? [Ans: 4.2%, 4.2]
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
226
LECTURE 20
REGULATED POWER SUPPLIES
Introduction
In this lecture we discuss voltage regulation by looking at simple examples of a Zener
regulator, a series regulator, a shunt regulator and IC regulators.
Objectives
By the end of this lecture you should be able to:

Design a Zener regulator;

Discuss the disadvantages of zener regulator;

Draw the circuit of a simple series regulator and explain how it works;

Draw the circuit of a simple shunt regulator and explain how it works;

List the advantages of IC regulators.
Regulator
The simple transformer-bridge-capacitor unregulated power supplies we discussed in
Lecture 19 are not generally adequate because their output voltages change with load
current and line voltage and because they have significant amounts of 100HZ ripple. It is
easy to construct stable power supplies using negative feedback to compare the d.c.
output voltage with a stable voltage reference.
A regulator is any circuit that maintains a rated output voltage under all conditions; either
no load (open circuit) or full load supplying an output current.
Zener regulator
The most basic and inexpensive form of voltage regulator uses a Zener diode as shown in
Figure 20.1.
227
R
Vi
IL
Z
V0
RL
Fig. 20.1: Basic Zener regulator
Vi is the raw or unregulated input voltage, applied to the series current limiting resistor R,
and the regulated output is taken across the Zener diode Z. The unregulated d.c. voltage
at the input reverse biases the Zener diode and must be larger than the Zener voltage of
the diode. The output voltage of this regulator is essentially equal to the Zener voltage.
It does, however, change somewhat when a load is connected because of the non-zero
resistance of the diode. This can easily be seen if we replace the Zener diode by its
equivalent circuit consisting of a voltage Vz and a series equivalent resistance rz. The
Zener resistance rz has typical values of 10 to 30 .
The output resistance of this regulator is the parallel combination of R and rz. Therefore,
the Zener regulator provides good regulation as long as the load resistance is sufficiently
higher than rz.
To find the load regulation of the Zener power regulator we replace the Zener diode by its
equivalent circuit as shown in Figure 20.2 and then determine the output resistance of the
regulator.
228
I
R
IL
IZ
Vi
rZ
V0
RL
VZ
Fig. 20.2: Equivalent circuit of the basic Zener regulator in Figure 20.1.
If we short Vi and Vz, and remove RL, we can then determine the output resistance Ro of
the regulator.
R0  R // rZ 
RrZ
R  rZ
The load regulation (see Lecture 19) is then given by
R0
RrZ

RL ( R  rZ ) RL
As an example let us take R=100, rZ=10 and RL=200:
R0 
RrZ
100  10

 9.1
R  rZ 100  10
 R0 
   100%  4.5%
 RL 
229
Apart from the condition that the load resistance must be sufficiently higher than the
Zener resistance, the power rating of the Zener should not be exceeded. If the output is
shorted, all the current from Vi will flow through the current-limiting resistance R alone.
Therefore R must have a power rating of more thanVi2/R.
Series regulator
Figure 20.3 shows the circuit of a basic series regulator.
IC
I0
R
Vi
IB
V
I
V0
VZ
IZ
Fig. 20.3: Basic series regulator.
The series regulator allows regulation over a wider range of loads. The output voltage Vo
is approximately equal to Vz-0.6, where Vz is the Zener voltage. The common-emitter
voltage VCE is given by VCE=Vi–Vo. This should be at least 1V to avoid saturation of the
transistor. The transistor ceases to provide regulation once it saturates.
The operation of the circuit is based on the fact that the output current Io is essentially the
same as the collector current Ic, which is equal to IB so long as the transistor is operating
in its active region. Therefore, when the load resistance changes, IB, and hence Ic, also
change, thus providing the proper output current in order to maintain the output voltage
230
constant. Since V0=Vz-VBE, the actual amount of change in the output voltage will
be
very small, given approximately by V0=-VBE=-rbeIB. The change VZ=rZIZ in the
Zener voltage can be neglected since rz is usually small.
Example:
Consider a silicon transistor with =100, rbe=500 and VBE=0.6V, and a Zener
diode with a Zener voltage VZ=5.6V and rZ=15 @20mA. Let VI=10V and
R=220. What will be the change in the output voltage Vo when the load
resistance RL is changed from 50 to 100?
With RL=50:
V0=VZ-VBE=5.6-0.6=5.0V
ICI0=V0/RL=5/50=100mA
IB=IC/=100/100=1mA
With RL=100:
IC5/10050mA
IB=IC/=50/100=0.5mA.
Therefore the change in the base current
IB=0.5-1=-0.5mA
his will cause a change in the base-emitter voltage
VBE=rbeIB=-500x0.5 mV=-0.25V
Therefore the change in output voltage
V0=-VBE0.25V
Note that the change in the Zener voltage is
VZ=rZIZ-rZIB=-15x(-0.5)mV7.5mV.
VZ is negligible compared to VBE=-250mV.
231
Shunt regulator
Figure 20.4 shows the circuit of a basic shunt regulator
I
I
R
I0
IC
VZ
VI
V0
IB
Fig. 20.4: Basic shunt regulator
In the shunt regulator the regulated output voltage is the sum of the Zener voltage V z and
the base-emitter voltage VBE, thus Vo=VZ + VBE.
If we assume that the input current I (also I  =I-IBI) is essentially fixed, then a decrease
in the load resistance will be followed by a tendency for the output Vo to decrease. A
decrease in Vo must be reflected as a decrease in VBE because Vz is constant. A decrease
in VBE, therefore, causes both IB and IC to decrease. Since I0+IC= I  I=constant, a
decrease in IC must be followed by an increase in the output current Io, so that Vo=IoRL
remains constant. Similarly an increase of the load resistance causes a decrease in the
output current.
The limit in the regulation of this circuit occurs when the load tries to draw all the current
supplied by the unregulated supply, that is, when Io=I. In such a case the transistor and
Zener diode cut off, so that the load resistance RL and R simply form a potential divider
232
across the unregulated input voltage.
IC regulators
Because of the availability of inexpensive high-performance regulator chips, there is no
advantage in using discrete components in voltage regulators. Low–cost fabricating
techniques have made IC regulators commercially available. These devices range from
fairly simple, fixed–voltage types to high-quality precision regulators.
The IC regulators have a number of features built into them. These include the following:

Current limiting (variable or fixed)

Self-protection against over temperature

Remote control

Remote shutdown

Operation over a wide range of input voltages
One does not need to be completely familiar with the circuit inside the IC regulator in
order to use it. However, it is necessary to understand the terminology used in the
specification sheets.
 Input voltage Range:
Upper and lower limit of input (unregulated)
voltage
 Output voltage range:
Range of possible regulated output voltages
 Line regulation:
The change in regulated output voltage for a
specified change in unregulated input voltage
 Ripple Rejection:
Decrease in the ac component from the input to the
output.
 Temperature stability:
Indication of the change in the output voltage for a
Change in operating temperature.
 Standby current:
Current drawn off by the regulator when no load is
connected.
 Output Noise Voltage:
Ac voltage (rms-value) at output under load with no
Ripple at the input.
233
Examples of IC regulators include the LM309 and the MA723. Their voltage ranges and
current limits are given in Table 20.1.
Table 20.1: IC Power Regulators
Vin
Vout
Iout,max
A723
9.5-40V
2-37V
65mA
LM309
7-25V
5V
1A
Figure 20.5 shows a complete regulated power supply using the IC regulator LM309 to
produce a 5V/1A regulated voltage supply.
Transformer
BR
240V
~
+
50HZ
+
+
C1
~
LM309
C2
-
Fig. 20.5: Regulated power supply; V0=5V@1A.
234
V0
The complete power supply consists of only five components, namely:
1. A transformer, capable of providing 10V–rms at 1A;
2. A full-wave bridge rectifier (BR) assembly with a current rating in excess of 1A;
3. Two capacitors C1 for ripple filtering and C2 for noise suppression; and
4. A hybrid IC voltage regulator (here LM309) with a heat sink.
Questions
1. (a) What is a power regulator?
(b) What distinguishes an unregulated power supply from a regulated one?
(c) What should be the output resistance of a voltage supply for best regulation?
2. The simple Zener regulator shown in Figure 20.1 is connected using a 12V Zener
diode with a current limiting resistance R=100. The unregulated input voltage
Vi=15V. Determine,
(a) the power rating of the Zener diode necessary for operation without a
load;
(b) the highest current that can be supplied with the diode still regulating,
assuming a Zener resistance of 10 and a minimum Zener-current of
5mA.
3. The shunt regulator in Figure 20.4 has the following circuit components: R=50,
Vz=15V, and rz=10; a silicon transistor with = 50 is used. The input voltage Vi is
20V.
(a) Determine the no-load power dissipation in the transistor.
(b) If the regulator is loaded with a resistance RL=25,
(i) What is the output voltage Vo?
(ii) Determine the load regulation of the power supply.
235
Further reading:
1. Cirovic, M.: Basic Electronics; Prentice-Hall, Virginia 1979.
2. Metzger, D.L: Electronic Circuit Behaviour.
236
LECTURE 21
DIGITAL CIRCUITS
Introduction
In this lecture a digital signal is defined and discussed, and some of its advantages over
the analog signal are listed. The transistor as a binary digital system is discussed and the
characteristics of digital signals are given.
Objectives
By the end of this lecture you should be able to:

Define a digital signal;

List the advantages of digital circuits over analog ones;

Describe the transistor switch as a binary device;

Define the rise- and fall-times of a pulse;

Define propagation delay time of a signal path.
Digital circuits
Most naturally occurring physical quantities are analog in their nature in that their value s
vary continuously with time. Examples are pressure, velocity, weight, etc. Analog signals
include sinusoidal, exponential and triangular waveforms.
The amplitude of a digital signal does not vary continuously; instead it may only take up
one of a number of defined values. The amplitude of the digital signal will suddenly
change from one value to another and it will never have an undefined value. In particular
the binary digital system may have either of two values; it may be HIGH or LOW.
Arising largely from the use of just the two voltage levels, digital techniques have a lot of
advantages over analog techniques. Some of the advantages are:

Digital circuits do not need to produce or detect precise values
particular points in a system.
237
at

It is easier and cheaper to mass-produce digital circuits than analog
circuits.

The binary nature of signals makes it much easier to consistently obtain a
required operating performance from a large number of circuits.

Digital circuits are more reliable than analog circuits because faults will
not often occur through variation in performance caused by components.

The effects of noise and interference are much reduced in a digital
system since the digital pulses can always be regenerated and restored. In
analog system noise degrades the signal permanently.
A digital revolution has spread to many aspects of life. The following are examples of
analog systems that have changed to digital:
o Analog computers: Analog computers are no more. They have been
replaced by digital computers since the 1940s, and have been in
widespread commercial use since 1960s.
o Audio recordings: Magnetic tapes have been replaced by digital compact
discs (CDs) and digital audio-tape (DAT).
o Telephone: In most telephone central offices analog signals are converted
into a digital format before they are routed to their destinations.
o Traffic
lights:
Traffic
lights
that
used
to
be
controlled
by
electromechanical timers, and later relays, are today controlled by
microprocessors. Microprocessors can control lights in ways that
maximize traffic flow.
Binary devices
A binary digital system has got two stable states. The simplest binary digital system is a
manual switch which can be either ON or OFF with no intermediate position. However,
the manual switch has the disadvantage of slow speed, large physical size and contact
bounce. Contact bounce is the generation of sporadic and irregular pulses as the switch
contact is made or broken. An ideal binary device should have the following
characteristics:
238

It should be turned ON or OFF by the binary “1” or “0” logic levels.

It should change instantaneously from one state to the other.

It should have infinite impedance when OFF and zero impedance when
ON.
The transistor switch
Bipolar and field-effect transistors can be switched very rapidly by an applied voltage.
Figure 21.1(a) shows a bipolar transistor operated as a switch.
When the input voltage Vin is about 0.6V or greater, for a silicon transistor, the baseemitter junction of the transistor becomes forward-biased causing a base current IB to
flow into the transistor. In turn this base current causes a collector current IC, given
approximately by IC=IB, which gives a small output voltage Vout=VCC-ICRC. The
transistor goes into saturation with VCE,Sat0.2V. On the other hand, when Vin is smaller
than 0.6V the base-emitter junction becomes reverse-biased and no base current flows.
Since this results in no collector current flow, the output voltage VoutVCC. The transistor
is then said to be OFF or not conducting.
+VCC
IC
VCC
RC
RC
ON
IC
Vout
IB
Vin
OFF
IB=0
VCC
(a)
(b)
Fig. 21: Bipolar transistor used as a switch: (a) Circuit diagram,
(b) Current-voltage relationships.
239
VCE
The words OFF and ON are used with respect to the state of the collector current; OFF
means IC0 and ON means ICVCC/RC. Figure 21.1(b) shows these two states. The
transistor is switched along the load line ICRC+VCE=VCC, also shown in Figure 21.1(b).
The circuit in Figure 21.1(a) is also known as an inverter. This is because when Vin0,
VoutVCC, and when Vin0.6V (or greater), Vout0. In other words an output voltage
exists when there is no input voltage and vice-versa.
Digital signals
Binary digital signals may be either unipolar or bipolar. A unipolar signal uses only one
polarity, either positive or negative, and it switches between this value and zero. A
bipolar signal switches between a positive value and a negative value.
Clock
When digital circuits are operated together, they must be timed precisely. This timing is
provided by a periodic train of pulses called a clock. Figure 21.2 shows a general
waveform of a clock.
V(t)
t
t1
t2
T
Fig. 21.2: Clock; T=period=1/frequency, t1/T=duty cycle(%),
t1/t2=make-space ratio.
240
Rise-time and fall-time
The pulses in Figure 21.2 are ideal; they rise and fall in no time (infinite speed!).
Practical pulses cannot have their leading edges (when the voltage rises from zero to a
positive value or from LOW to HIGH) and trailing edges (when the voltage falls from a
positive value to zero or from HIGH to LOW) rise or fall instantaneously. Figure 21.3
shows a practical pulse with rise-time tr, fall-time tf and pulse width tW
V(t)
tW
Vˆ
0.9 Vˆ
VH, min
0.5 Vˆ
VL, max
0.1 Vˆ
0
t
tr
tf
Fig. 21.3: Definitions of: rise-time tr, fall-time tf, and pulse width tW.
The rise time tr of the waveform is the time taken for the signal to increase from 10% (or
0.1) to 90% (or 0.9) of its peak value. The fall-time tf is the time taken for the signal to
decrease from 90% to 10% of its peak value. The pulse width tW is the time for which the
amplitude of the pulse is greater tan 50% of its peak value. If we take LOW to be the
241
voltage level 0.1 Vˆ or less, and take HIGH to be the voltage level 0.9 Vˆ or greater, ten we
see that the rise- and fall-time indicate how long the signal takes to pass through the
“undefined” region between LOW and HIGH.
Propagation delay time
Rise- and fall-time only partially describe the dynamic behavior of a logic element. To
relate the output timing to the input timing we define the propagation delay time of a
signal path as the amount of time that it takes for a change in the input signal to produce a
change in the output signal. Signal path is the electrical path from a particular input signal
to a particular output signal of a logical element. Depending on the direction of the output
change (signal rising or falling), there are two different propagation delays for the inputto-output signal path. Figure 21.4 shows the input and output voltages of an inverter, e.g.
a bipolar transistor.
Input signal
VH
0.5(VH-VL)
VL
Output signal
VH
0.5(VH-VL)
VL
tpHL
tpLH
Fig. 21.4: Propagation delay times: tpHL = propagation delay when the
output switches from HIGH to LOW, and tpLH = propagation
delay when the output switches from LOW to HIGH.
242
Propagation delay is due to the inherent transistor switching delays which make the
change in the output voltage occur sometime after the occurrence of the input transition.
In general tpHL and tpLH are not equal and both depend on the load capacitance CL and the
power supply VCC used. Data sheets usually state the value of CL used when measuring
the values of tpHL and tpLH quoted. Sometimes the average value t pd 
1
t pHL  t pLH  is
2
quoted instead of tpHL and tpLH. The propagation delay of a gate limits the highest
frequency at which the gate can be operated. The lower the value of the ratio tpLH/tpHL the
higher the maximum frequency of operation.
Questions
1. Differentiate between analog and digital signals.
2. List three advantages of using digital circuits over analog circuits.
3. Name three digital systems you know.
4. (a) What is a binary digital system (binary device)?
(b) Why is a manual switch not a good binary device?
(c) Explain how a transistor inverter is used as a binary device.
5. (a) What is a clock as used in digital circuits?
(b) Define the following using diagrams: rise-time, fall-time, pulse-width, and
propagation delay-time.
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
243
LECTURE 22
LOGIC GATES
Introduction
In this lecture a logic gate is defined and circuit symbols for logic gates are introduced.
The truth tables for the logic gates are derived and the notation for writing logic functions
is explained.
Objectives
By the end of this lecture you should be able to:

Draw the circuit symbols for AND, OR and NOT gates;

Draw up the truth tables for the AND, OR and NOT gates having two inputs;

Write down the logic equations for the AND, OR and NOT gates;

Explain how the NAND and NOR gates may be obtained from the AND and OR
gates respectively;

Draw the circuit symbols for the NAND, NOR, EX-OR and EX-NOR gates;

Draw up the truth tables for the NAND, NOR, EX-OR and EX-NOR gates;

Write down the logic equations for the NAND, NOR, EX-OR and EX-NOR gates.
Fundamental logic gates
The gate is the most basic digital device. It has one or more inputs and produces an
output that is a function of only the current input values. This type of logic circuit where
the output depends only on the current inputs and not also on the past sequence of inputs
is called a combinational logic circuit.
The most important kinds of gates are the AND, OR and NOT gates. Figure 22.1 shows
the circuit symbols for the three basic gates.
AND
OR
NOT
Fig. 22.1: Circuit symbols for the AND, OR and NOT gates.
244
The circuit symbols for the AND and OR gates in Figure 22.1 have been drawn with two
inputs. However, the symbols can be drawn with more than two inputs.
Truth tables
The truth table of a gate (or any other combinational circuit) is a table which lists all the
possible combinations of the input variables applied to the gate and the output of the gate.
The output of the gate is called the logic function and the inputs are the logic variables.
The logic variables can only take on the values 0 and 1 (i.e., LOW or HIGH). The logic
function can also be either 0 or 1. Let us consider two input logic variables A and B, and
let Y be the logic function (the gate’s output). We can write Y as a function of A and B as
shown in Figure 22.2.
A
Y
B
A
A
B
AND: Y=AB
OR:
Y
Y
Y=A+B
NOT:
YA
Fig. 22.2: Notations for AND, OR and NOT logic functions.

Y=AB
Is the logic function for the AND gate. It is also called the conjunction or
logic multiplication. Some authors write A B or A  B or A  B , instead
of AB.

Y=A+B
Is the logic function for the OR gate. It is also called the disjunction or
logic addition. Some authors write A  B or A  B , instead of A+B.

YA
Is the logic function for the NOT gate or inverter. It is also called the
negation or complement ( A is the complement of A). Some authors write
A or A* , instead of A . Note that the inverter has only one input.
245
To be able to obtain the truth tables for the tree gates above, we can use a simple analogy
of a switch using the circuits in Figure 22.3.
A
B
A
B
VB
Y
VB
Y
(a) AND gate
(b) OR gate
Fig. 22.3: Realization of two-input AND and OR gates using switches.
From Figure 22.3(a) we see that there will be an output Y only if both switches A and B
are closed. Otherwise there will be no output for any combination of the two switches. In
Figure 22.3(b) the switches are connected in parallel. Therefore there will always be an
output except when both switches are open. Furthermore, if we represent the state “switch
open” by the logic “0” and the state “switch closed” by the logic “1”, we obtain the truth
tables in Table 22.1.
Table 22.1: Truth tables for two-input AND and OR gates, and the NOT gate.
A
B
YAND
YOR
A
YNOT
0
0
0
0
0
1
0
1
0
1
1
0
1
0
0
1
1
1
1
1
YNOT= A
YAND=AB, YOR=A+B
246
The above truth tables are worth memorizing. They are very easy to remember; for the
AND gate, the output is always LOW (or 0) except when both inputs are HIGH (or 1).
For the OR gate, the output is always HIGH except when both inputs are LOW. For the
inverter or NOT gate, the output is HIGH if the input is LOW and vice-versa.
We can use the three basic rules above to extend the truth tables in Table 22.1 to three or
more input variables. For example we can write the truth tables for three variables as
shown in Table 22.2.
Table 22.2: Truth table for three-input AND and OR gates.
A
B
C
AB
ABC A+B
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
247
A+B+C
First we write all the possible combinations of the input variables A, B and C. For three
variables there are 23=8 different combinations, and hence the eight rows in the table. We
start with zero(ABC=000) and count up to seven(ABC=111). We start with 000 and keep
on adding on one (binary arithmetic) until we reach 111.
O evaluate the NAND function, Y=ABC, we first work out the column for AB with help
of Table 22.1. Then we use this column together with the column for C to finally evaluate
ABC. You may try to evaluate Y=A+B+C in a similar way as described above. The
columns for A+B and A+B+C are already drawn in Table 22.2.
Other logic gates
Using the three basic logic gates described above, we can construct many other gates.
Three important such gates are the NOR, NAND and EX-OR gates. The NOR and
NAND gates are simply the negations of the outputs of the OR and AND gates
respectively. In fact NOR is short for NOT-OR and NAND is short for NOT-AND. The
EX-OR or EXclusive-OR (sometimes written XOR) can easily be explained with use of a
truth table. Figure 22.4 shows the circuit symbols for the new gates.
AND
OR
EX-OR
Fig. 22.4: Circuit symbols for the NAND, NOR and EX-OR gates.
Note the similarity between the symbols in Figure 22.4 for the NAND and NOR gates,
and those in Figure 22.1 for the AND and OR gates. The only difference is the dot (or
tiny circle) at the output. The dot at the output is used to symbolize a negation. If the dot
at the output of the inverter in Figure 22.1 is omitted, we get a symbol for the a device
248
called a buffer. Its output is equal to the input. It is used as an impedance transformer for
matching two circuits. Table 22.3 shows the truth tables for the NAND, NOR, EX-OR
and EX-NOR gates. The EX-NOR gate is obtained by negating the output of the EX-OR
gate.
Table 22.3: Truth tables for two-input NAND, NOR, EX-OR and EX-NOR gates.
A
B
YNAND
0
0
1
0
1
1
1
YNOR
YEXOR
YEXNOR
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
1
From Table 22.3 we note that the EX-NOR gate is HIGH when both inputs are the same
(i.e., both either LOW or HIGH), otherwise it is LOW. For this reason the EX-NOR gate
is also known as the equivalence or EQUIV gate and the EX-OR as the antivalence or
ANTIV gate. The EX-OR and EX-NOR gates can have only two inputs. These gates can
be used for comparing two bits.
Since the NAND and NOR gates are negations of the outputs of the AND and OR gates
respectively, we can write the their logic functions as follows:
YNAND  AB
YNOR  A  B
249
Table 22.4 shows how the logic function for the EX-OR may be derived.
Table 22.4: Derivation of the logic function for the EX-OR gate.
A
B
A
B
AB
AB
A B+A B
0
0
1
1
0
0
0
0
1
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
0
0
0
0
From Table 2.4 we can also write the logic functions for the EX-OR and EX-NOR gates
as:
YEXOR  AB  AB  A  B
YEXNOR  AB  AB  A  B
The circuit symbol for the EX-NOR gate is obtained by including a dot at the output of
the EX-OR gate symbol in Figure 22.4.
250
Questions
6. (a)What is a logic gate?
(b) Name the tree basic gates and draw their circuit symbls.
7. (a) Write down the logic equations for the following gates: AND, OR, NOT.
Assume three inputs A, B and C for the AND and OR gates.
(b) Draw the truth tables for the logic functions in (a).
8. (a) How can the AND and OR gates be realized? What can you say about the
NOT gate?
(b) Draw the realization for 3-input AND and OR gates.
9. Construct truth tables for the following logic functions:
(a) F  ABC  AB C  AB C
(b) G  AB  AC
What can you comment about the two functions?
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
251
LECTURE 23
LOGIC ALGEBRA
Introduction
In this lecture we introduce Boolean algebra and point out the differences between
Boolean algebra and ordinary algebra. We learn how to use the laws of Boolean algebra
to simplify logic equations.
Objectives
By the end of this lecture you should be able to:

Differentiate between Boolean and ordinary algebra;

Prove any of the laws of Boolean algebra using truth tables;

Use the laws of Boolean algebra to simplify a logic function;

Use the laws of Boolean algebra to obtain equivalent circuits of a logic function.
Laws of Boolean algebra
To be able to work with binary variables we use a type of algebra called Boolean algebra.
It is used for describing systems which work with binary variables. Remember, a binary
variable represents the two possible states of a binary system. It can only take on two
possible values 0 or 1 (i.e., LOW or HIGH).
Laws of Boolean algebra are used when dealing with Boolean equations. Whereas some
of the laws are similar to those of ordinary algebra you learnt at school, many of the laws
have nothing to do with those of ordinary algebra. We list below some of the laws (or
theorems, as they are sometimes called). Each law has two parts, namely one for logic
multiplication (or AND) and another for logic addition (or OR).
1. Commutative laws:
(a) A+B=B+A
(b) AB=BA
2. Associative laws:
252
(a) A+(B+C)=A+B+C=(A+B)+C
(b) A(BC)=ABC=(AB)C
3. Distributive laws:
(a) A(B+C)=AB+AC
(b) A+BC=(A+B)(A+C)
4. Absorption laws:
(a) A+AB=A
(b) A(A+B)=A
5. Tautolog laws:
(a) A+A=A
(b) AA=A
6. Negation laws:
(a) A+ A =1
(b) A A =0
7. Double negation law:
A =A
8. De Morgan’s laws:
(a) A  B  A B
(b) AB  A  B
9. Operations with logic 0 and 1:
(a) A+0=A,
A.1=A
(b) A+1=1,
A.0=0
(c) 1  0 ,
0 1
To prove the above laws we can use truth tables. To illustrate this let us consider the first
distributive laws, namely A(B+C)=AB+AC. We make truth tables for the left-hand side
(LHS) and the right-hand side (RHS), and then compare the two columns. Forst we note
that we have three logic variables, namely, A, B and C. Therefore we draw up a truth
table for three logic variables as shown in Table 23.1.
To obtain the logic function for the LHS, we first evaluate B+C and then A(B+C). This is
253
shown in the second and third columns of Table 23.1. We then turn to the RHS, namely,
AB+AC. We first evaluate the two terms AB and AC respectively, and then combine
them to obtain the 6th column of Table 23.1. Finally, by inspection of the table we see that
the LHS (column 3) is the same as the RHS (column 6).
Alternatively we may complete the truth table experimentally. Figure 23.1 illustrates this
method. We proceed by connecting up the circuits in Figure 23.1 and completing Table
23.2. The inputs A, B and C to the circuits in Figure 23.1 may be realized using the
ground (GND) for 0 and +5V for 1. The outputs Y1 and Y2 may easily be monitored
using a light-emitting diode (LED) which lights for 1 and extinguishes for 0.
Table 23.1: Truth table for the distributive law A(B+C)=AB+AC
A
B
C
B+C
A(B+C) AB AC
AB+AC
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
254
A
B
Y1=A(B+C)
C
(a)
A
B
Y2=AB+AC
C
(b)
Fig. 23.1: Cicuits for the distributive law A(B+C)=AB+AC
Table23.2: Truth table for the distributive law Y1=A(B+C)= Y2=AB+AC
A
B
C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Y1
Y2
255
1
1
1
De Morgan’s laws
De Morgan’s laws are probably the most commonly used of all the laws of switching
algebra (Boolean algebra). We have already stated the laws (see law number 8) using two
logic variables. But the laws are valid for any number of input logic variables, and may
be written as
X1  X 2   X n  X1  X 2  X n
X1 X 2  X n  X1  X 2    X n
The first law says that an n-input OR gate whose output is complemented (or negated) is
equivalent to an n-input AND gate whose inputs are complemented. The second law says
that an n-input AND gate whose output is complemented is equivalent to an n-input OR
gate whose inputs are complemented. These two theorems together with the doublenegation theorem ( A =A) are useful in designing equivalent circuits. It is common
practice to use only one or two types of gates in a circuit. For example one may be having
only NAND gates or only NOR gates, and probably inverters in addition. This would
necessitate the transformation of all logical expressions (equations) such that they use
either, only NANDs or only NORs (and inverters perhaps).
Let us look at two simple examples:
Y1  AB  AB  A  B
Y2  A  B  A  B  A  B
256
The first example is te AND logic function. The double-negation gives an equivalent
circuit using a NAND and an inverter, and De Morgan’s theorem gives an equivalent
circuit using a NOR and two inverters. These circuits are shown in Figure 23.2(a).
A

or
B
(a)
A

or
B
(b)
Fig. 23.2: Example of equivalent circuits obtained using De Morgan’s theorems:
(a) AND logic function, (b) OR logic function.
The second example is the OR logic function. Again by use of the double-negation
theorem and De Morgan’s theorems, we obtain two equivalent circuits shown in Figure
23.2(b).
Finally we also note that we can build an inverter using either a NAND or an OR gate.
We make use of the tautology theorems, namely, A+A=A and AA=A. If we negate both
sides of these equations we get
A A  A
257
AA  A
The interpretation of these equations is that we can obtain the complement A by use of
either a NAND or a NOR gate as illustrated in Figure 23.3.
A
A
A
(a)
A
(b)
Fig. 23.3: Realizing an inverter using: (a) NAND gate, (b) NOR gate.
We have assumed that the NAND and NOR gates have two inputs. This is not always the
case. In general unused inputs, especially CMOS inputs which have such high
impedance, should never be left unconnected (or floating). As a general rule any unused
inputs should be tied to another input. However, in high-speed circuit design this
increases the capacitive load on the driving signal and may slow things down. A better
solution is then the following:

An unused AND or NAND input should be tied to logic 1 (through
a pull-up resistor).

An unused OR or NOR input should be tied to logic 0 (through a
pull-down resistor).
The pull-up or pull-down resistor has a value in the range of 1 to 10k
258
Questions
10. (a)What is Boolean algebra?
(b) Define the following: logic variable, logic function.
(c) How can a logic variable be realized?
11. How would you go about proving the distributive laws of Boolean algebra using
truth tables?
12. Use the theorems of switching algebra to simplify each of the following logic
functions:
(a) F  ABCD ( ABC D  A BCD  ABCD  AB CD)
(b) G  AB  ABC D  ABDE  ABC E  C DE
13. Write the truth table for each of the following logic functions:
(a) F  A B  A B C
(b) F  AD  B C  A C
(c) F  AD  B  C 





(d) F     A    C    D  , where X   X





14. Given the logic function F=AB+AC, draw a circuit to realize the function:
a. using three 2-input NAND gates only,
b. using three 2-input NOR gates only.
15. In the circuit below write down the logic function F as a function of the three
logic variables A, B and C.
A
B
F
C
259
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
260
LECTURE 24
MINIMIZATION OF LOGIC FUNCTIONS
Introduction
In this lecture we introduce graphical methods for simplification or minimization of logic
functions of 2, 3, 4 or 5 logic variables. Construction and use of a Karnaugh map is
illustrated by examples.
Objectives
By the end of this lecture you should be able to:

Write the canonical sum of a logic function from its truth table;

Draw a Karnaugh map (K-map) from the truth table;

Use a K-map to minimize a logic function;

Use a K-map to obtain the inverse (or complement) of the minimized logic
function;

Draw up a truth table from a given K-map;

Draw up a truth table for a given minimized logic function.
Writing a logic function from the truth table
In Lecture 22 we derived the truth tables for the AND and OR logic functions. There we
simply wrote down the functions YAND=AB and YOR=A+B. It is possible to write down
the logic function from a truth table. We do this by first noting for which combinations of
the input variables is the logic function equal to 1. For example looking at Table 22.1
(Lecture 22), we see that YAND=1 for AB=11, and YOR=1 for AB=01 or 11. When a
variable is 0 we write it in its complementary form, and when a variable is 1 we write it
down in its uncomplimentary form. Thus, we write 00 as A B , 01 as A B, 10 as A B ,
and 11 as AB. Therefore we write
YAND=AB
YOR= A B+A B +AB
261
Although the equation for the AND-function is in its simplest form, the equation for the
OR-function is not. Simplified (reduced or minimized) form means a form which will use
fewest number of gates to implement the circuit design.
We can simplify YOR by the use of the laws of Boolean algebra we learnt in Lecture 23.
First we rewrite YOR using the tautology law:
YOR= A B+AB+A B +AB
The distributive law then gives
YOR=( A +A)B+A( B +B)
But A+ A =1 and B+ B =1, B.1=B and A.1=A.
Therefore
YOR=A+B
This is the simplest form of the OR-function.
Let us look at another example of two logic functions F and G given by way of truth
tables shown in Table 24.1.
Table 24.1: Truth tables for logic functions F and G
of 3 logic variables A,B and C.
A
B
C
F
G
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
1
0
262
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1
1
1
1
1
0
As described above we can write down the logic functions F and G as
F  A B C  A BC  AB C  ABC
= A B  B C  AB  B C
= A  AB  B C
=1.1.C
=C
This result is apparent from the truth table in Table 24.1 by comparing the column for the
logic variable C and the column for the logic function F.
For G we can write
G  A BC  AB C  ABC
= A BC  AB  B C
= A BC  A  1  C
= A B  AC
As these two simple examples may reveal, when Boolean algebra is used to simplify a
logic expression, it is not always clear if the result obtained is the simplest expression
263
possible. The procedure may be lengthy and error-prone, especially with more variables.
Karnaugh maps
A Karnaugh map (or simply K-map) is a graphical representation of a logic function’s
truth table. It provides a convenient method of simplifying Boolean equations. The
function to be simplified is displayed diagrammatically on a set of squares or cells. Each
cell maps one term (also called product term) of the function. For n variables the number
of cells is equal to 2n, which is the number of possible combinations of n binary variables.
Let us look at the three cases n=2, 3 and 4, one at a time.
Two variables:
A
B
0
1
A
0
or
1
B
Fig. 24.1: K-map for 2 logic variables A and B.
The K-map has four squares (or cells) representing all the possible combinations of the 2
logic variables A and B. The first and second columns represent A and A respectively,
while the first and second rows represent B and B respectively. The labeling of the Kmap can be done in any one of the two ways shown in Figure 24.1, depending on your
own personal choice.. The top left cell represents the state 00, the top right cell represents
10, the lower left cell represents 01, and the lower right cell represents 11.
264
Three variables:
AB
C
A
00
01
11
10
0
or
1
C
B
Fig. 24.2: K-map for 3 variables A, B and C
The 1st and 2nd rows represent C and C respectively. The 1st and 2nd columns together
represent A , while the last 2 columns (3rd and 4th columns) together represent A. A and
B are arranged in such a way that there is an intersection (3rd column). Note also from the
first diagram on the left, that AB runs in the order 00, 01, 11, 10. This is to ensure that
two neighboring cells differ in only one bit.
Four variables:
AB
CD
A
00
01
11
10
00
01
or
11
D
C
10
B
Fig. 24.3: K-map for 4 variables A, B, C and D.
265
The 1st and 2nd columns together represent A while the 3rd and 4th columns together
represent A. The two middle columns (2nd and 3rd columns) represent B, and the two
outer columns (1st and 4th columns) represent B . In a similar manner the 1st two rows
represent C , while the 3rd and 4th rows together represent C. the two middle rows (2nd
and 3rd rows) represent D, and the two outer rows (1st and 4th rows) represent D .
The order of the row and column labels is done in such a way that each cell corresponds
to an input combination that differs from each of its immediate adjacent neighbors (i.e.
horizontal and vertical neighbors) in only one variable. This why the labels for either the
rows or the columns are 00, 01, 11, 01 or A B , A B, AB, A B for columns and C D ,
C D, CD, C D for the rows.
Marking the cells
Each input combination for which the logic function is 1 in the truth table corresponds to
a minterm (or product) term in the logic function’s canonical sum. A canonical sum is a
sum of minterms for which the function produces a 1. Since pairs of adjacent 1-cells in
the K-map have minterms that differ in only one variable, the minterm pairs can be
combined into a single product term using the generalization of AB+A B =A. Thus we
can use a K-map to simplify the canonical sum of a logic function.
Example
Let us consider the examples in Table 24.1. F and G are logic functions of 3 variables A,
B and C. Therefore we draw K-maps for 3 variables using Figure 24.2. Let us use the
diagram on the right side. The K-map for F and G are shown in Figure 24.4.
266
A
g2
A
g1
0
0
0
0
0
1
1
1
0
0
0
0
or
C
1
1
1
1
C
B
B
(a) K-map for F
(b) K-map for G
Fig. 24.4: K-maps for logic functions F and G given in Table 24.1
To be able to draw these K-maps we first write down from Table 14.1 the canonical sums
for F and G:
F  A B C  A BC  AB C  ABC
G  A BC  AB C  ABC
In the K-map for F we locate the cells A B C , A BC , AB C and ABC (or 001, 011, 101
and 111) and then write a 1 in each of these cells and a 0 in the rest of the cells. Locating
a particular cell is quite easy. For example the cell A B C is locating by first considering
how A is represented in the K-map. A is represented by the first two columns. Similarly
B is represented by the 1st and 4th columns. Therefore A B is represented by the 1st
column alone. Remember that A B means “ A AND B ” or “ A intersection B ”. Now
since C is represented by the 2nd row, then A B C must be represented by the cell in the
2nd row and 1st column. The other cells are located in a similar way. Locating cells may
be easier if the K-map is labeled as in the left diagram of Figure 24.2.
In general, we simplify a logic function by combining pairs of adjacent 1-cells
267
(minterms) whenever possible, and writing a sum of product terms that cover all of the 1cells. From the K-maps in Figure 24.4, we obtain the minimized forms for F and G as
F C
G  AC  BC
The expression for F is straightforward from the K-map. The expression for G consists of
two terms obtained by taking pairs of adjacent 1-cells as indicated by the groupings g1
and g2 in the K-map for G, so that G=g1+g2.
Example 2
A logic function H is given in form of a truth table below.
Row
A
B
C
D
H
0
0
0
0
0
1
1
0
0
0
1
0
2
0
0
1
0
1
3
0
0
1
1
0
4
0
1
0
0
0
5
0
1
0
1
1
6
0
1
1
0
0
7
0
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
0
10
1
0
1
0
1
11
1
0
1
1
0
12
1
1
0
0
0
13
1
1
0
1
1
14
1
1
1
0
0
15
1
1
1
1
1
In the truth table above we have included the first column, headed row, just as a decimal
268
counter; it helps to check on the number of possibilities. The K-map is shown below.
g2
g1
g2
g1
AB
CD
g2
00
01
11
10
00
1
0
0
1
01
0
1
1
0
or
A
g2
1
0
0
1
0
1
1
0
D
11
0
1
1
0
0
1
1
0
1
0
0
1
C
10
1
0
g2
0
1
g2
g2
B
g2
The 1-cells in the K-map have been put into two groups g1 and g2, g1=BD and g 2  B D .
Therefore the minimized equation for H is given by H=g1+g2 or
H  BD  B D
K-map for 5 variables
The K-map for a logic function of 5 variables A, B, C, D and E can be constructed by
drawing, side by side, two 4-variable K-maps, one for E and one for E (or one for E=1
and one for E=0).
Don’t care states
Don’t care states (or conditions) are combinations of the input variables for which the
logic function is either 1 or 0. The states are indicated by a cross x in a K-map. When the
logic equation is simplified, each cell containing x may be looped (grouped) with either
269
1-cells or with 0-cells. An example of don’t care states is the binary-coded decimal
(BCD) system in which each of the 10 decimal digits 0 through to 9 is represented by a 4bit binary equivalent. Since a 4-bit code allows the use of numbers up to 15 (1111) the
BCD system includes some redundant states, which can be looked at as don’t care states
since they would never occur and can therefore be assigned any convenient values.
The use of K-maps is applicable only to simple Boolean expressions with up to five logic
variables. More complex equations can be handled using tabular methods, which can be
programmed for solution by computer.
Questions
16. What do you understand by the following: minterm, canonical sum, don’t care
state.
17. A 3-variable input logic circuit shows a 1 at the output whenever the input has the
following decimal numbers: 0, 1, 4, or 5.
a. Draw a truth table for the logic circuit.
b. Use the truth table to write down the canonical sum of the logic function.
c. Construct a K-map and use it to minimize the function.
18. Use a K-map to minimize the logic function F given the equation
F  AB C D  A B C D  ABC D  A BCD  ABD  B CD  A BC D
19. Design a logic circuit that inputs a 4-bit number and gives a HIGH output
whenever the input number is prime. Hint: A prime number is a natural number
greater than 1 that has only the factors 1 and itself.
20. A certain beauty contest is decided by a panel of judges who cast their votes by
simply pressing either a green or red light button. To advance to the next stage of
the contest a candidate has to score three or above. Design a logic circuit, which
shows the result of a candidate. Assume that green represents a logic 1 and red
270
represents a logic 0.
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
271
LECTURE 25
LOGIC FAMILIES
Introduction
In this lecture diode logic, bipolar logic and complementary metal-oxide semiconductor
(CMOS) logic circuits are presented and discussed. The advantages of each logic family
over the others are discussed.
Objectives
By the end of this lecture you should be able to:

Define a logic family;

Draw and explain the basic circuits of a diode logic (DL) AND-gate and OR-gate;

Draw and explain the basic circuits of a transistor transistor logic (TTL) NANDgate;

Name the advantages of emitter-couple logic (ECL) family over TTL and CMOS
logic;

Name the advantages of CMOS logic over ECL and TTL.
Logic family
There are very many ways of designing a logic circuit. The various kind of gates can be
obtained in a number of logic technologies called logic families. A logic family is a
collection of different integrated circuit (IC) chips that have similar input, output, and
internal circuit characteristics, but that perform different logic functions. Chips from the
same family can be interconnected to perform any desired logic function. But chips from
different families may not be compatible, in that they may use different power supply
voltages or may use different input and output conditions to represent logic values. These
logic technologies or families provide small-scale integrated (SSI) devices, medium-scale
integrated (MSI) devices, large-scale integrated (LSI) devices, and very-large scale
integrated (VLSI) devices. Table 25.1 shows the general definitions for integrated
circuits. It gives the number of gates or equivalent circuits fabricated on a single chip.
272
Table 25.1: Scale of integration of ICs
Name
Gates on a chip
SSI
<10
MSI
10-100
LSI
100-5,000
VLSI
>5,000
Fan-in and fan-out
The fan-in of a gate is the number of inputs which can be connected to the gate. The fanout is the maximum number of standard loads that can be connected to the gate’s output
terminals without the output voltage falling outside the limits at which the logic levels 0
and 1 are specified.
Diode logic
A semiconductor diode (or junction diode) is able to act as a switch because it can be
turned ON and OFF by an applied voltage. When he diode is OFF its resistance is high,
usually several thousand ohms, and when it is ON the voltage across it is not zero but
approximately 0.6V (for silicon diodes). The time taken by the diode to turn Onis very
small but it takes longer to turn OFF. The turn-OFF time limits the maximum frequency
at which a diode can be switched.
Figure 25.1(a) shows a generalized diode characteristic. The diode conducts only when
the forward bias voltage is greater than a threshold value Vf.
273
I
A
K
A
K
A
K
Slope=1/Rf
A
0
Vf
K
V
Vf
(a)
Rf
Rr
(b)
(c)
Fig. 25.1: Diode: (a) Characteristic, (b) forward-bias equivalent circuit,
(c) reverse-bias equivalent circuit.
When a diode is ON it can be replaced by an equivalent circuit (model) consisting of a
battery of emf Vf and a series resistance Rf as shown in Figure 25.1(b). For silicon diodes
Vf is very often assumed to be 0.6V. Rf is the ac resistance of the diode when it is
forward-biased. It is a small resistance of around 20. When a diode is OFF it can be
represented by a resistance Rr as shown in Figure 25.1(c). Rr is called the reverse
resistance of the diode and its value is very large (several hundreds of mega-ohms).
Diode action can be exploited to perform logic operations. Figure 25.2 shows possible
circuits for realizing the AND and OR gates.
+5V
A
R
B
A
Y=AB
Y=A+B
R
B
(a) Two-input AND gate
(b) Two-input OR gate
Fig. 25.2: Diode Logic
274
For the diode logic we may use the following logic signal levels: 0-2V for LOW (0) and
3-5V for HIGH (1). The level 2-3V represents an undefined level called the noise margin.
So any voltage below 2V is LOW and any voltage above 3V is HIGH. We shall use 0V
or ground (GND) as LOW and +5V as HIGH for the inputs A and B.
AND gate
When both inputs A and B are made low (by grounding them), both diodes are forwardbiased creating a potential drop of 0.6V across each diode. Therefore the output will be
low. When the two inputs are complementary, i.e. A= B , the output appears across the
forward-biased diode (i.e. the diode with a low input) and it is low. When both inputs are
high, both diode are reverse-biased and the output is equal to the supply voltage. The
output id therefore high.
OR gate
When both inputs are low, no current flows in the resistor R and the output is zero or low.
When the two inputs are complementary, the diode on high is forward-biased and the
diode on low is reverse-biased. The output, which is the voltage across R, is less than the
power supply voltage by one diode-drop. Therefore the output is equal to 5-0.6=4.4V or
high.
If we draw the truth tables for these gates, they should agree with those of Table 22.1 in
Lecture 22. The diode logic (DL) is not a complete logic family because we cannot
realize an inverter or NOT gate using diodes. Modification of DL by adding a transistor
as an inverter gives the diode transistor diode (DTL). DTL a good theoretical basis for
understanding of bipolar logic gates, but it is seldom used in practice today because of the
wide availability of high-performance and low-cost logic families with active buffers in
every gate. The DTL has been overtaken by the transistor transistor logic or TTL.
275
Transistor transistor logic
By far the most commonly used bipolar logic is the transistor transistor logic or TTL.
Typical TTL logic levels are 0-0.8V for LOW, and 2.0-5.0V for HIGH. There are also
different TTL families with a range of speed, power consumption, and other
characteristics. The basic circuit for TTL is the NAND gate shown in Figure 25.3.
+5V
R1
A
R2
Y  AB
Q1
B
Q2
Fig. 25.3: Basic TTL NAND gate
The input transistor Q1 has a number of emitters equal to the desired fan-in of the circuit.
When both input terminals are +5V (high), the base-emitter junction of Q1 is reversebiased but its base-collector junction is forward-biased. Current then flows from the
power supply, through R1, into the base of transistor Q2. Q2 turns on and the output
voltage Y falls to the saturation voltage of the transistor. The output of the circuit is then
at logic 0. When either one or both of the input terminals is grounded (logic 0), the
associated base-emitter junction will be forward-biased but the base-collector junction
will be reverse-biased. Q2 turns off and the output voltage of the circuit then rises to +5V
or logic 1. Thus Q1 performs the AND function and Q2 acts as an inverter to give an
overall circuit of a NAND function.
276
The basic TTL NAND gate contains several Schottky diodes (hot carrier diodes) and
resistors in form of an integrated circuit (IC). A Schottky diode is a high-speed diode
with a low forward drop (0.25V), which is usually connected from base to collector
where it takes away current from the base when the collector is nearing saturation. It
prevents saturation, since its forward drop voltage is less than that of the collector-base
junction. TTL was popularized in the 1970s by Texas Instruments company, whose
7400-series part numbers for gates and TTL components have become an industry
standard. A TTL data sheet contains recommended operating conditions, electrical
characteristics, switching characteristics and absolute maximum ratings. A complete data
book also shows test circuits that are used to measure the parameters of the device, and
graphs that show how the typical parameters vary with operating conditions such as
power supply voltage, ambient temperature and load. TTL NAND gates can be designed
with any desired number of inputs (fan-in). Commercially available TTL NAND gates
have as many as 13 inputs. A TTL inverter is designed as a 1-input NAND gate.
Open-collector outputs
Some TTL gates are also available with open-collector outputs in which the collector of
the output stage is left open, so that only passive pull-up to the high-state s provided by
an external resistor. Open-collector outputs can be useful in driving external loads (e.g.
LEDs), performing wired logic and driving external bases. The pull-up resistor has a
value ranging from a few hundred to a few thousand ohms. Open-collector gates usually
indicated in logic circuit diagrams by an asterisk near the output terminal. Figure 25.4
shows examples of a wired-OR and a wire-AND, each two gates. The number of gates
can be extended.
277
A
+5V
+5V
1k
k
*
A
B
*
B
C
*
C
*
F
G
D
D
(a) F   A  B   C  D  A  B  C  D
(b) G  AB  CD  AB  CD
Fig. 25.4: Wired logic: (a) Wired-OR, (b) Wired-AND
The basic TTL-series have a delay time of about 10ns. Compatible series have been
developed using Schottky diodes which prevent saturation in TTL gates.
Some TTL-series:
Name
Part Number

Schottky TTL
74S…

Low Power Schottky
74LS…

Advanced Schottky
74AS…

Advanced Low Power Schottky
74ALS…

Fast TTL
74F…
278
Emitter-Coupled Logic (ECL)
The key to reducing propagation delay in a bipolar logic family is to prevent a gate’s
transistors from saturating. In TTL gates Schottky diodes are used to prevent saturation.
ECL avoids saturated transistors in a different manner by making the difference between
the input high and low levels differ by a small voltage of about 1 volt. ECL is extremely
fast with propagation delays as short as 1ns. It disadvantages over TTL and CMOS are
that it consumes much more power, has poor speed-power product, does not provide a
high level of integration, and is not directly compatible with TTL and CMOS. The basic
circuit of the ECL is a differential amplifier consisting of two transistors with a commonemitter resistor.
CMOS logic
The complementary metal oxide semiconductor or CMOS logic family, which uses MOS
transistors, offers some significant advantages over bipolar logic. These advantages
include:
o Very low power consumption;
o Good noise immunity;
o Ability to operate from a wide range of power supply voltages.
Its main disadvantages are:

A relatively long propagation delay time;

Low output current capability.
The long propagation delay time arises from the inpu time constant of the enhancementmode MOSFETs that are employed because they turn off when their gate-source voltage
is at zero volts.
279
Some typical figures for the CMOS 4000-series:

LOW level
VOL=0.05V max.

HIGH level
VOH=VDD-0.05V min.

Noise margin
1V min.

Propagation delay
30ns

Sink current @VDD=5V
IOL=1mA

Sink current @VDD=15V
IOL=6.8mA

Source current @VDD=5V
1mA

Source current @VDD=15V 6.8mA
Unused CMOS inputs should never be left unconnected (or floating). Since CMOS inputs
have such a high impedance, it takes only a small amount of circuit noise to temporarily
make a floating input look high, creating some very nasty intermittent circuit failures.
Unused inputs should be tied to used inputs.
To prevent electrostatic discharge (ECD) damage when handling loose CMOS devices,
circuit assemblers and technicians usually wear conductive write straps that are connected
by a coil cord earth ground; this prevents a static charge from building up on their bodies
as they move around the factory or lab. Before handling a CMOS device, touch a
grounded metal case of a plugged-in instrument or another source of earth ground.
280
Questions
21. (a) What do you understand by a logic family?
(b) What is a complete logic family?
(c) What bipolar logic?
22. Name at least five logic families.
23. (a) Draw a possible circuit diagram of a DTL 2-input NAND gate.
(b) Explain how the circuit in (a) works.
24. Figure 25.3 show the basic TTL 2-input NAND gate. Suggest how you would
modify the circuit to realize
a. an inverter,
b. a NOR gate.
25. How would you rate the following three logic families, in terms of speed (or
propagation delay time), power consumption and noise immunity: TTL, ECL,
CMOS.
26. Which logic family would you use in a design of a digital wristwatch? Give
reasons why.
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
281
LECTURE 26
MULTIVIBRATORS
Introduction
In this lecture we differentiate between combinational and sequential logic circuits. The
three multivibrators: monostable, bistable and astable are explained with use of bipolar
transistor circuits. The Schmitt-trigger circuit is discussed and its possible uses are
presented.
Objectives
By the end of this lecture you should be able to:

Define a combinational logic circuit;

Define a sequential logic circuit;

Identify the circuits of a monostable multivibrator, an astable multivibrator and a
bistable multivibrator;

Describe how a Schmitt trigger operates;

Name the uses of a Schmitt trigger.
Sequential logic circuits
Logic circuits can be classified into two types, combinational and sequential. A
combinational logic circuit is one whose outputs depend on its current (or present) inputs.
Its operation is fully described by a truth table that lists all combinations of input values
and the output value(s) produced by each one. A logic gate is an example of a
combinational logic circuit. A combinational circuit may contain any number of logic
gates but no feedback loops, which generally create sequential circuit behavior.
A sequential logic circuit is one whose outputs depend not only on its current inputs, but
also on the past sequence of inputs. That is, the circuit has a memory of past events and
the behavior of the circuit may be described by a state table that specifies its output and
next state as functions of its current state and input. The state of a sequential circuit is a
collection of state variables whose values at any one time contain all the information
about the past necessary to account for the circuit’s future behavior. The state changes of
282
most sequential circuits occur at times specified by a free-running clock signal.
Multivibrators
A multivibrator is an oscillator that contains two linear inverters coupled in such a way
that the output of one provides the input for the other. There are several types of
multivibrators, the action of depends on the type of coupling used. The coupling can be
either resistive or resistive-capacitive. Resistive coupling produces a bistable circuit that
has two stable states and can change state on the application of a trigger pulse. Resistivecapacitive coupling produces a monostable multivibrator. Capacitive coupling produces
an astable multivibrator that has two quasi-stable states; once the oscillations are
established the device is free-running, i.e., a continuous waveform is generated without
the application of a trigger signal.
Bistable multivibrator
+VCC
RC
RC
RB
RB
Q
Q
T1
T2
R
R
-VBB
Fig. 26.1: Transistor bistable multivibrator
283
Figure 26.1 shows a transistor bistable multivibrator. The circuit is a simple sequential
circuit consisting of a pair of inverters forming a feedback loop. It has no inputs but has
two complementary outputs Q and Q . The circuit has two possible stable states, namely
when transistor T1 is ON and transistor T2 is OFF, and vice-versa. We summarize the two
states below:
State 1:
T1 is saturated (i.e. ON) and T2 is OFF, as a result
VBE10.6V, VCE10.2V
VBE2-VBB, IC20, VCE1+VCC
Therefore Q=VCE1=LOW and Q =VCE2=HIGH.
State 2:
T1 is OFF and T2 is saturated.
Here the exact opposite of what happened in state 1 occurs. The result is that
Q=HIGH and Q =LOW.
Monostable vibrator
The monostable multivibrator, also known as a time switch, monoflop, univibrator or
oneshot, has only one stable state. The second state stable for only a given time
determined by the time constant RC. After this time interval the circuit switches back, on
its own, to its stable state. Figure 26.2 shows the circuit of a transistor monostable
multivibrator.
284
+VCC
RC
R
RC
C
R1
C1
Vout
T1
B2
T2
R2
Vin
Fig. 26.2: Monostable multivibrator
The circuit is started (or triggered) by a trigger pulse applied at the input terminal labeled
Vin. In the stable state (before Vin is applied) transistor T1 is cut OFF while transistor T2 is
ON (i.e. conducting). The base current making T2 to conduct is supplied from VCC
through the resistor R. Therefore in this case we have the following dc voltages (with
respect to ground):
VB1=0, VB2=0.6V; VC1=+VCC, VC2=0
Suppose now we supply a positive pulse of very short duration at the input Vin. This will
make T1 conducting. As a result T1’s collector potential will jump from +VCC to zero.
Now a small-signal equivalent circuit of T1 shows that R and the capacitor C forma
highpass filter with its input at T1’s collector C1 and output at T2’s base B2. Therefore the
step-voltage at T1’s collector will be transmitted to T2’s base by the highpass filter. The
285
highpass filter makes T2’s base potential jump from 0.6v to –VCC+0.6V, and thereby
making T2 cut OFF. T1 will be kept conducting through the feedback resistor R, even
when the input voltage Vin is already zero again.
To find T2’s base voltage, we make use of the step-function response of a highpass filter.
The base voltage rises approximately according to

VB 2 (t )  VCC 1  2e t / RC

Transistor T2 remains cut OFF until VB2 has risen to about 0.6V. After that, transistor T2
becomes conducting again, that is the circuit jumps back to its stable state. We can
estimate the time it takes for VB2 to reach the value of 0.6V by setting VB2(t)=0. This
gives the output pulse width to approximately
tW  RC ln 2  0.7 RC
Figure 26.3 shows the voltages of the monostable multivibrator. The input trigger pulse
width is less than the output pulse-width tW. In Figure 26.3 the pulse width of the input
pulse used was about 25s and the output pulse-width obtained was tW0.326ms.
Vin
VB1
0.7V
0
+VCC
VC1
0
VCES
286
0.6V
VBES
VB2
-VCC+0.6V
Vout
VCES
tW
Fig. 26.3: Voltages of the transistor monostable multivibrator
Monostable multivibrators exist in form of integrated circuits (IC), for example:
74LS122 = Retriggerable monostable multivibrator;
74LS123 = Dual retriggerable monostable multivibrators;
74LS221 = Dual monostable multivibrators with Schmitt-trigger inputs.
Astable multivibrator
If we replace the second feedback resistor R1 of the monostable multivibrator in Figure
26.2 by a capacitor, then both states become stable for only a limited time. The resulting
circuit, shown in Figure 26.4, starts to oscillate between the two states once it is switched
on.
287
+VCC
RC
R2
R1
C2
RC
C1
T1
T2
Fig. 26.4: Astable Multivibrator
As we saw in the case of the monostable multivibrator the switching times can be
approximated by
t1=R1C1ln2, t2=R2C2ln2
As a clock for digital circuits the period is given by the sum t1+ t2, and hence the
frequency as the reciprocal of this sum. For a symmetrical clock we let R1C1=R2C2 or
R1=R2=R and C1=C2=C. Figure 26.5 shows the voltages of the astable multivibrator.
This multivibrator can produce pulses in the frequency range 100Hz-100kHz. Below
100Hz the capacitors become too large, while above 100kHz the switching times of the
transistors become noticeably disturbing. For these reasons the circuit in Figure 26.4 is
not very practical. Astable multivibrators in form of integrated circuits (IC) are available.
288
VB1
0.7V
t
-VCC
VC1
+VCC
0
VB2
t
0.7V
0
t
-VCC
VC2
+VCC
0
t
t1
t2
Fig. 26.5: Voltages of the multivibrator
Schmitt trigger
A Schmitt trigger is a bistable circuit whose output is binary and is determined by the
magnitude of the input signal, being independent of the input signal form. The output
level changes to the high levelwhen the input signal magnitude drops below a
predetermined value. The circuit inevitably exhibits hysteresis; the amount of hysteresis
is determined by the components in the circuit and can be altered so that the desired
switching levels can be selected.
289
The Schmitt trigger can be used in binary logic circuits in order to maintain the integrity
of the logic 1 and 0 levels. It can also be used with a variety of analog waveforms as a
level detector, i.e., it acts as a trigger for other circuits or devices when the magnitude of
the input waveform exceeds or falls below the predetermined levels. The device may also
be used to generate a rectangular/square pulse train from a variety of input waveforms.
The input-output transfer characteristic of an inverter is shown in Figure 26.6. The
corresponding transfer characteristic for a gate with Schmitt trigger inputs is shown in
Figure 26.7(a).
Vout
VOHmax
H
VOHmin
VOHmax
L
VOHmin
Vin
VIlmin
VIlmax
L
VIhmin
VIHmax
H
Fig. 26.6: Typical input-output transfer characteristic
290
Vout
5.0V
0.0V
0
VT- VT+
5.0V
Vin
(a)
(b)
Fig. 26.7: Schmitt trigger inverter: (a) Input-output
characteristic, (b) circuit symbol
As we said before a Schmitt trigger is a special circuit that uses feedback internally to
shift the switching threshold depending on whether the input is changing from low(L) to
high(H) or from high to low. Figure 26.8 shows an illustration of the usefulness of
hysteresis.
Vin
VT+
VT
VT-
t
291
Vout
H
L
T
Fig. 26.8: Schmitt trigger inverter with a noisy, slow-changing input Vin
The input signal Vin is a noisy, slow-changing signal. VT+ is called the switching
threshold for positive-going input changes and VT- is the switching threshold for
negative-going input changes. The difference between the two threshold levels is called
the hyteresis (VT+-VT-). An ordinary inverter, without hysteresis, has the same switching
threshold for both positive-going and negative-going transitions, VT 
VT   VT 
.
2
Questions
27. (a) Differentiate between combinational and sequential logic circuits.
(b) Give one example of each of the circuits in (a).
28. (a) Why is the monostable multivibrator also known as a time switch?
(b) What can you about the input (trigger) and output pules-widths?
(c) Suggest one possible use of the monostable multivibrator.
29. (a) How does the astable multivibrator differ from the monostable multivibrator?
(b) Sketch the outputs of the astable multivibrator.
(c) Name one use of the astable multivibrator.
30. (a) What is a Schmitt trigger?
(b) Name two uses of a Schmitt trigger.
(c) Use the input signal in Figure 26.8 to sketch the output signal of an ordinary
292
inverter without hysteresis (i.e., VT+=VT-=VT).
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
293
LECTURE 27
FLIP-FLOPS
Introduction
In this lecture a flip-flop as a bistable multivibrator is discussed. The R-S flip-flop, the D
flip-flop, the T flip-flop and the J-K flip-flop are described. The advantage of edgetriggered flip-flop is discussed.
Objectives
By the end of this lecture you should be able to:

Define a define a flip-flop;

Name uses of flip-flops;

Construct the R-S flip-flop using either NOR or NAND gates;

Draw up the state table of the R-S flip-flop;

Define edge-triggering in flip-flops;

Draw up the state table of a J-K flip-flop;

Design a T flip-flop using a J-K flip-flop.
Flip-flops
The basic storage elememnt is a bistable multivibrator (BMV) because it can store a 0 or
a 1. These are the two stable states of the BMV. However, a BMV has no mechanism by
which the states (or contents) can be changed.
A flip-flop (FF) is a device that store either a 0 or a 1. The state of a FF is the value that it
currently stores. The stored value can be changed only at certain times determined by a
‘clock’ input, and the new value may further depend of the FF’s current state and its
‘control’ inputs. A FF is an example of a sequential logic circuit. A digital circuit that
contains FFs is a sequential logic circuit. The name ‘flip-flop’ arises form the fact that
application of a suitable input pulse causes the device to ‘flip’ into the corresponding
state and remain in that state until a pulse on the other input causes it to ‘flop’ into the
other state.
294
FFs are widely used in computers as counting and storage elements and several types
have been developed. FFs as described above are unclocked and are triggered directly by
the input pulses. Clocked FFs have a third input to which a clock pulse is applied. We
describe below the basic types of FFs.
R-S Flip-flops
If we modify the bistable multivibrator circuit in Figure 26.1 (Lecture 26), we get the
circuit in Figure 27.1 called the R-S flip-flop.
+VCC
RC
RC
R1
R1
Q
Q
T1
T2
R2
R2
R
S
Fig. 27.1: Transistor R-S flip-flop
The R-S FF has two inputs called the Set(S) and the Reset(R) inputs, and two
complementary outputs Q and Q . S sets (or presets) Q to 1 and R resets (or clears) Q to
0. The R-S FF in Figure 27.1 can be made using a discrete design typically designed as a
feedback sequential circuit using individual logic gates and feedback loops. Figure
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27.2(a) shows a R-S FF using NOR gates. Figures 27.2(b) and 27.2(c) show the circuit
symbol and state table respectively.
In the state table we use Qn+1 to mean “next value of Q” and Qn to mean “previous value
of Q.” Therefore Qn+1 is the present state and Qn is the previous state of the FF. Some
authors use Q* instead of Qn+1. From the state table we see that when R and S are both 0,
the FF does not change its previous state. But when R and S are complementary (i.e.,
S  R ) the FF takes on the state at the S-input (i.e., Qn+1=S). The state when both R and
S are 1 (i.e. HIGH) is undefined; making both R and S HIGH would make both
transistors in Figure 27.1 conducting, a condition which would make the output
unpredictable. Therefore this state (i.e., R=S=1) is avoided.
R
Q
Q
S
(a)
R
S
Qn+1
0
0
Qn
0
1
1
1
0
0
1
1
*
* = unallowed state
(c)
R
Q
S
Q
(b)
Fig. 27.2: The R-S flip-flop: (a) Circuit using NOR gates,
(b) circuit symbol, (c) state table.
296
(=S)
The R-S FF in Figure 27.2(a) uses NOR gates. We can also construct one using NAND
gates. We start by writing the Boolean equations for the outputs Q and Q from Figure
27.2(a):
Q  R  Q and Q  S  Q
In order to use NAND gates, we complement the two equations above:
Q  R Q and Q  S Q
These two equations can be realized using NAND gates as shown in Figure 27.3. Note
however, that in this version we use the complementary inputs R and S instead of R
and S, respectively.
Q
S
Q
R
Fig. 27.3: R-S flip-flop using NAND gates
R-S flip-flop with Enable
The R-S FF considered above is sensitive to its R and S inputs at all times (a latch).
However, we may modify it to create a device that is sensitive to these inputs only when
an enabling input C is asserted (i.e., made HIGH). Such a FF with an enabling input is
shown in Figure 27.4.
297
S
S
Q
C
Q
R
R
(a)
S R C
Qn+1
0 0 1
Qn
0 1 1
0
1 0 1
1
1 1 1
*
x x 0
Qn
R
Q
C
Q
S
(b)
*=unallowed state, x=0 or 1
(c)
Fig. 27.4: R-S flip-flop with enable: (a) Circuit, (b) circuit symbol, state table.
We see that S   SC  S , if C=1. Similarly R  RC  R , if C=1. Thus when C=1, the
R-S FF with an enable input behaves like the R-S FF in Figure 27.3. But when C=0,
S   1 and R  1, which is equivalent to the state when R=S=0, as in the state table in
Figure 27.2(c). The R-S FF retains its previous state when R=S=0. The state table in
Figure 27.4(c) summarizes the results.
298
D Flip-flop
To eliminate the troublesome situation when both S and R are asserted simultaneously,
we can make sure that we always have R  S by adding an inverter before the R-input.
The resulting circuit is shown in Figure 27.5(a).
D
Q
C
Q
(a)
D
Q
C
Q
(b)
D C
Qn+1
x 0
Qn
0 1
0
1 1
1
(c)
Fig. 27.5: D Flip-flop: (a) Circuit, (b) circuit symbol, (c) state table.
This FF, called a D flip-flop (or data latch), has two inputs D and C. From the state table
in Figure 27.5(c) we see that when C=0, the output is unaffected by the change at the Dinput. But when C=1 the output follows the D-input. The control C is sometimes named
EN or ENABLE, CLK or clock, or G, and is active low in some D-latch designs.
299
Edge-triggered flip-flops
There are times when it is necessary to have a FF that changes its output only at either the
rising edge (low to high or 0 to 1) or falling edge (1 to 0) of a controlling clock (CLK)
signal. If the output changes at the rising edge, the FF is called a positive-edge triggered
FF, and if the output changes at the falling edge, the FF is called a negative-edge
triggered FF. The rising and falling edges of the clock are also known as the leading edge
and the trailing edge, respectively. Edge-triggered FFs can be made by designing a circuit
with two FFs, a master FF and a slave FF. For this reason edge-triggered FFs are also
known as master-slave FFs. In the positive-edge triggered FFs the master FF (the first FF)
is open and follows the input when the clock is LOW. When the clock goes HIGH, the
master FF is closed and its output is transferred to the slave FF. The slave FF is open all
the while that the clock is HIGH, but changes only at the beginning of the interval,
because the master is closed and unchanging during the rest of the interval.
J-K flip-flops
The problem of what to do when S and R are asserted simultaneously is solved in a
master-slave J-K FF. The J and K inputs are analogous to S and R of the R-S FF. Figure
27.6 shows an edge-triggered J-K FF using an edge-triggered D FF internally. The arrow
direction in the state or function table indicates a rising edge.
Q
J
D
K
CLK
CLK
(a)
300
Q
Q
Q
Q
J
K
C
Qn+1
x x
0
Qn
Q
x x
1
Qn
Q
0
0
Qn
0
1
0
1
0
1
1
1
Qn
J
C
K
(b)
(c)
Fig. 27.6: Edge-triggered flip-flop: (a) circuit, (b) circuit symbol, (c) function table.
T flip-flop
A T (or toggle) FF changes state on every tick of the clock. The FF can be positive-edge
or negative-edge triggered. Figure 27.7(b) shows the functional behavior (timing
diagrams) of a positive-edge triggered T-FF. Notice that the signal on the FF’s output Q
has precisely half the frequency of the T-input.
Q
T
Q
(a)
301
T
Q
Q
(b)
Fig. 27.7: Edge-triggered T flip-flop: (a) circuit symbol, (b) timing diagrams.
It is possible to construct T FFs from D or J-K FFs as shown in Figure 22.8. The T FF in
Figure 27.8(b) has an enable input EN. The FF changes state at the triggering edge of the
clock only if EN=1.
EN
D
Q
J
Q
Q
T
T
C
Q
C
Q
Q
K
(a)
(b)
Fig. 27.8: Possible circuits of a T flip-flop made from,
(a) a D flip-flop, (b) a J-K flip-flop.
302
Questions
31. (a) What is a flip-flop? Why is a flip-flop a sequential circuit?
(b) Name two possible uses of flip-flops.
32. (a) Draw the circuit diagram of an R-S flip-flop using NOR gates.
(b) Draw and complete the state table for the R-S flip-flop. Comment on the state
of the flip-flop when both R and S are asserted simultaneously (R=S=1).
33. Given four 2-input NAND gates, how would you realize the R-S flip-flop?
34. (a) What is an edge-triggered flip-flop? What is the advantage of using such a
flip-flop?
(b) Draw the logic( or circuit) symbol of a J-K flip-flop.
(c) Draw and complete a state table for the J-K flip-flop.
35. (a) By use of the J-K flip-flop state table in question 4(c) above, draw a circuit
diagram for a T flip-flop using a J-K flip-flop.
(b) Draw a timing diagram for the T-input and Q-output. Comment on the
frequency of the input and output signals.
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Crecraft, D.I., et al.: Electrinics; Chapman and Hall 1994.
3. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
303
LECTURE 28
BINARY COUNTERS
Introduction
In this lecture we shall introduce the ripple counter and the synchronous counter, and
point out the advantage of the latter over the former. Cascading of counters and reduction
of the modulus of count will be discussed using examples.
Objectives
By the end of this lecture you should be able to:

Define a ripple counter;

Differentiate between synchronous and asynchronous counters;

Point out the advantage of synchronous counters;

Sketch the clock and output waveforms of a counter to illustrate ‘frequency
division’;

Cascade two or more counters to extend the length of count;

Modify the basic counter circuit in order to reduce the length of count;

List applications of counters.
Counters in general
A very important aspect of sequential circuitry is the ability to count. A counter is an
electronic circuit that is able to count the number of pulses applied to its input terminals.
The count may be outputted using the straight forward binary code, or may be in binarycoded decimal (BCD). Alternatively, the outputs of a counter may be decoded to produce
a unique output signal to represent each possible count. A counter that counts from zero
to 2n-1, which is m=2n state, is known as a modulo m-1 counter. For example a counter
that counts from 0 to 7 is known as a modulo-7 counter. It has m=23=8 states, namely
0,1,2,3,4,5,6 and 7. A counter may also be used as a frequency divider to produce a pulse
waveform of lower frequency than the original clock.
304
Applications of counters
The possible applications of counters are many. They are often used for the direct
counting of objects in industrial processes and of voltage pulses in digital circuits such as
digital voltmeters. Counters can be used as frequency dividers and for the measurement
of frequency and time. They are also used in analog-to-digital conversion.
Ripple counter
As mentioned above, counters are clocked sequential circuits. A modulo-(m-1),
sometimes called a divide-by (m-1) counter, has m states which are visited in the
sequence 0,1,2,…,2n-1,0,1,2,… Each of these states is encoded as the corresponding n-bit
binary integer.
We can construct an n-bit binary counter using n flip-flops. Figure 28.1 shows a 4-bit
binary ripple counter.
(LSB)
(MSB)
Q0
Q1
Q
C
T
Q2
Q
Q
T
Q
Q3
T
Q
Q
T
Q
Q
Fig. 28.1: A 4-bit binary ripple counter using T flip-flops.
The carry information ripples from the less significant bits to the more significant bits
one bit at a time. Remember that a T flip-flop toggles (changes state) on every
rising/falling edge of its clock input. Figure 28.2 shows the clock and output waveforms.
The arrows indicate the rising edges of the ‘clocks.’
305
C
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Fig. 28.1: Clock(C) and output waveforms of the 4-bit binary ripple counter.
Synchronous counters
Although the ripple counter is easier to realize than any other type of binary counter, it is
too slow. When the most significant bit (MSB) of an n-bit ripple counter changes, the
output is not valid until a time ntpd after the rising edge of the clock Qn 2 (the clock for
the nth flip-flop), where tpd is the propagation delay time from input to output of a T flipflop. A synchronous counter has the clock applied to all the flip-flops at the same time. In
this way all the flip-flops outputs change at the same time, after a delay of only t pd. This
requires the use of T flip-flops with enable-inputs. Figure 28.3 shows two synchronous 4bit counters.
306
EN
CLK
EN
T
EN
Q
EN
T
Q
T
Q0
EN
Q
Q1
T
Q
Q2
Q3
(a)
EN
CLK
EN
T
EN
Q
T
EN
Q
T
Q0
Q1
EN
Q
T Q
Q2
(b)
Fig. 28.3: Synchronous 4-bit binary ripple counter, (a) with serial enable logic,
(b) with parallel enable logic.
307
Q3
The output of a T flip-flop with enable input toggles on the rising edge of the clock input
T if and only if the enable input EN is high. Combinational logic on the enable inputs EN
determines which, if any, flip-flops toggle on each rising edge of the clock CLK. In
Figure 28.3(a) the combinational enable signals propagate serially from the least
significant bits to the most significant bits. If the clock period is too short, there may not
be enough time for a change in the counter’s least significant bit to propagate to the most
significant bit. This problem is eliminated in Figure 28.3(b) by driving each enable input
EN with a dedicated AND gate. This counter, called a synchronous parallel counter, is the
fastest binary counter structure.
IC counters
Counters are available in both TTL and CMOS logic families. Medium scale integration
(MSI) counters have extra inputs and outputs. We look at one particular example, the
TTL 74163. The 74163 is a synchronous 4-bit binary counter. Figure 28.4 shows its pin
configuration (top view).
CLR
1
16
VCC
CLK
2
15
RC0
A
3
14
QA
B
4
13
QB
C
5
12
QC
D
6
11
QD
ENP
7
10
ENT
GND
8
9
LOAD
Fig. 28.4: Pin configuration of the 74163
QD QC QB QA is the output code word with QA=LSM and QD=MSB. DCBA is the input
code word with A=LSB and D=MSB. The data inputs are used to preset the count. This is
308
done by letting the LOAD -input got to low for a very short duration ( LOAD is normally
set to high). The counter has two enable inputs ENP and ENT. Both enable inputs are put
on high. The counting is inhibited if ENP is made to go from high to low (negative edge).
The CLR -input is normally high. It is momentarily made to go to low to clear the outputs
to zero. RCO is the carryout bit output, it indicates a carry from the MSB position and is
1 when all of the count bits are equal to 1 and ENT is high. VCC is the power supply (+5V
for TTL) and GND is ground (earth). The 74163 is fully synchronous, that is, its outputs
change only on the rising edge of the clock CLK.
Cascading of counters
In many applications more than 16 states are required for counting. Counters like the
74163 are designed to be able to be connected together to extend the length of count.
Figure 28.5 shows the general connections for an 8-bit counter (28=256 states).
CLK
CLK
QA
Q0
RESET
CLR
QB
Q1
LOAD
LOAD
QC
Q2
ENP
QD
Q3
EN
ENT
CRO
8-bit output
code word
CLK
QA
Q4
CLR
QB
Q5
LOAD
QC
Q6
ENP
QD
Q7
ENT
CRO
RCO8
Fig. 28.5: General cascading of two 74163 counters to form an 8-bit counter
309
The CLK, CLR , and LOAD inputs of all the 74163s are connected in parallel, so that all
of them count or are cleared, or loaded at the same time. The enable signal EN is
connected to the low-order (first) counter. The RCO output is asserted if and only if the
first counter(lower-order 74163) is in state decimal 15 (binary 1111) and EN=1; RCO is
connected to the enable inputs of the second counter (high-order counter). Thus, both the
carry information and the master enable EN ripple from the output of one 4-bit counter
stage to the next. This scheme can be extended to build a counter with any desired
number of bits, although the maximum counting speed is limited by the propagation
delay time of the ripple carry signal through all the stages.
Up/down counter
The 74169 is a synchronous 4-bit up/down counter. One difference in 74168 is that its
carry output and enable inputs are active low. More importantly, the 74169 is an up/down
counter; it counts is ascending or descending binary order depending on the value of an
input signal U / D . The counting is up if U / D =1 and down if U / D =0. Note that U / D
is the name of the input (pin number 1).
Reducing the count
There are occasions when a counter is required to have a count of less than 2n-1, where n
is the number of flip-flops it contains. The reduced count is obtained by modifying the
basic counter circuit so that one or more of the possible states are omitted.
Although the 74163 is a modulo-16 counter, it can be made to count in a modulus less
than 16 by using the CLR and LOAD inputs to shorten the normal counting sequence.
Figure 28.6 shows an example of a modulo-11 counter with the counting sequence
5,6,…,15,5,6…
310
+5V
R
CLK
CLK
CLR
LOAD
QA
Q0
ENP
QB
Q1
ENT
QC
Q2
A
QD
Q3
B
C
RCO
D
Fig. 28.6: Modulo-11 counter with counting sequence 5,6,…,15,5,6…
During the counting the carry output is low, CRO=0, so that the load input LOAD is high
(through the 7404 inverter). But when the count reaches 15 (or 1111) CRO goes to 1 and
thereby making the load input low. The counter ten loads with the binary number
DCBA=0101 (= decimal 5). There many other ways to make a modulo-11 counter using
a 74163. The choice of approach depends on the application.
The 74160 and 74162 are synchronous decade counters. They are 4-bit counters with a
modified counting sequence to go to state 0 after state 9. In other words, these are
modulo-10 counters, sometimes called decade counters.
Frequency division
A look at the waveforms(outputs) of a 4-bit counter in Figure 28.2 shows that a binary
counter offers the possibility of frequency division by multiples of 2, depending on which
311
bit position is used. A familiar example of this idea is found in the digital watch. Te
problem here is to provide a compact, precision oscillator of high stability to produce a
sequence of pulses at one second intervals. Low-frequency oscillators are not compact
(they involve use of large capacitors) nor do they operate with the required precision (e.g.
accuracy of 1 second in a month may be required in a watch). The solution is to use a
high-frequency oscillator regulated by a quartz crystal and divide the frequency to the
required 1 Hz. Crystal-controlled oscillators can be designed to give good long-term
stability coupled with high accuracy. In the process of dividing down, this accuracy is
maintained all the way through to the final 1Hz output. A crystal frequency commonly
used in watches is 32.768 kHz. You will notice that the number 32768=2 15, so that a 15bit counter could provide a 1Hz output.
Frequency division using modulo-n counters is used as the basis for frequency
determination in ‘digitally synthesized’ tuners for radio reception. In this case a
waveform corresponding to the required signal frequency is divided by a large value of n,
and this divided value is synchronized to a fixed frequency from a stable oscillator. By
altering the value of n, the ‘synthesized’ signal frequency can be stepped through a range
of values.
Questions
1. (a) How can a 3-bit ripple counter be constructed? Draw the circuit diagram.
(b) Draw the clock and output waveforms of the counter in (a).
(c) What is the major disadvantage of a ripple counter?
2. (a) What is a synchronous counter and how does it differ from a ripple counter?
(b) Draw a diagram of a 3-bit synchronous binary counter using J-K flip-flops.
3. (a) Why is the cascading of counters useful?
(b) Draw a diagram of a 12-bit binary counter made out of three 4-bit counters.
(c) What limits the building of a counter of any number of bits using 4-bit
counters?
4. By using the 74163 (4-bit synchronous binary counter) design,
312
(a) a decade (or modulo-10) counter,
(b) a
modulo-13
counter
with
the
following
counting
sequence:
3,4,….,15,3,4…..
5. (a) Given a quartz crystal oscillator of frequency 128 Hz, how would you go
about to provide a 1Hz-clock?
(b) Suggest, by use of block diagrams, how you would design a digital watch
using the clock in (a).
Further reading:
4. Seeti, M.L.: Basic Electronics; Makerere 2003.
5. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
313
LECTURE 29
BINARY ADDERS
Introduction
In this lecture we shall introduce the half-adder and the full-adder by means of truth
tables. The ripple adder and its disadvantage will be discussed. Subtractions by a twos
compliment will be described and examples presented.
Objectives
By the end of this lecture you should be able to:

Define a half-adder;

Define a full-adder;

Draw up the truth table of a full-adder;

Draw the circuit diagram of a 1-bit full-adder;

Draw a block diagram of a n-bit ripple adder;

Cascade two adders;

Construct a n-bit subtracter from a n-bit adder.
Adders
Addition is the most commonly performed operation in digital systems. A binary adder is
a circuit which is able to add together two binary numbers. An adder is a combinational
logic circuit.
Half-Adder
The simplest adder, called a half-adder (HA), adds two 1-bit numbers (operands) X and
Y, producing a 2-bit sum S. The sum can range from zero to two, which requires two bits
to express. The high-order bit is a carry-out bit Cout. Table 29.1 shows the truth table of a
half-adder.
314
The sum S is obtained by carrying out the four additions: 0+0=00, 0+1=01, 1+0=01,
1+1=10. The carry-out bit Cout is zero everywhere except for the last sum 1+1=10, where
the sum S=0 and Cout=1.
Table 29.1: Truth table of a half-adder
X
Y
S
Cout
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
From the truth table we can write down the Boolean equations for S and Cout as follows:
S  XY  XY  X  Y
Cout  XY
We can recognize the expression for S as the EX-OR gate (see Lecture 22). Therefore we
can realize the half-adder using the EX-OR gate for the sum and an AND gate for the
carry-out bit Cout. Figure 29.1 shows a circuit for the half-adder(HA).
HA
X
S
Y
Cout
315
Fig. 29.1: Circuit diagram of a half-adder(HA) with
inputs X and X, and outputs S and Cout.
If we wanted to add two 2-bit numbers, e.g. 11+01, using two half-adders would not give
the correct result (e.g. 11+01=10, which is incorrect). This is because the HA is unable to
take into account of any carry from a previous stage (or the less significant sum).
Full-adder
To add two numbers with more than one bit, we must be able to ‘carry’ between bit
positions. A full-adder(FA) has a third input for the ‘carry-in’ bit Cin. Table 29.2 shows
the truth table of a full-adder.
Table 29.2: Truth table of a full-adder
X
Y
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
From the above truth table the Boolean equations for the sum and carry-out bits can be
written as:
S  XYCin  XYCin  XYCin  XYC in
316

Cout  XYC in  XYCin  XYCin  XYC in
If we construct the K-maps for S and Cout, we can easily minimize Cout but not S. Figures
29.2(a) and 29.2(b) show the K-maps for S and Cout respectively.
X
Cin
X
0
1
0
1
1
0
1
0
Cin
0
0
1
0
0
1
1
1
Y
Y
(a)
(b)
Fig. 29.2: K-maps of a full-adder: (a) Sum S, (b) Carryout Cout
From Figure 29.2(b) we can minimize Cout to:
C out  XY  XCin  YC in
The sum S cannot be minimized (it is already in its minimized form) but it can be
rewritten as follows:
S  XYCin  XYC in  XYCin  XYCin
= XY  XY Cin  XY  XY Cin
= X  Y X  Y Cin  XY  XY Cin , since XX  0 and 0  X  X ,
S = X  XY  Cin  XY  XY Cin
= X  Y  Cin   X  Y Cin
317
= X  Y  Cin
Therefore we have managed to express S in terms of gates we already know, namely EXOR gates. Figure 29.3(a) shows a possible gate-level circuit diagram of a full-adder(FA)
using the above equations. Figure 29.3(b) shows the logic symbol for the full-adder.
FA
X
Y
S
Cin
Cout
(a)
X
S
Y
Cout
Cin
(b)
318
Fig. 29.3: Full-adder (FA): (a) Circuit diagram, (b) logic symbol
Ripple adder
A ripple adder is a cascade of full-adder stages, each of which handles one bit. Figure
29.4 shows a 4-bit ripple adder.
X0 Y0
X1 Y1
X2 Y2
X3 Y3
X
X
X
X Y
Y
Y
C1
C0
Cin
Cout
Y
C2
Cin
Cout
C3
Cin
Cout
C4
Cin
Cout
S
1
2
S0
3
S1
4
S2
S3
Fig. 29.4: A 4-bit ripple adder
In this 4-bit ripple adder, two 4-bit numbers X  X 3 X 2 X 1 X 0 and Y  Y3Y2Y1Y0 are added
together to get a sum S  S 3 S 2 S1 S 0 , where C4 is the carryout bit. The carry-in C0 to the
least significant adder (adder number 1) is normally set to 0.
A ripple adder is slow, since in the worst case a carry must propagate from the least
significant full-adder to the most significant one. Faster adders are made using a
technique called “carry look ahead” which speeds up the process. As an example of
medium scale integration (MSI) adders, the 74283 is a 4-bit binary adder that forms its
sum and carry outputs with just a few levels of logic, using the carry look-ahead
319
technique. Figure 29.5 shows the pin configuration of the 74283 4-bit binary full-adder
with fast carry.
S2
1
16
VCC
B2
2
15
B3
A2
3
14
A3
S1
4
13
S3
A1
5
12
A4
B1
6
11
B4
C0
7
10
S4
GND
8
9
C4
Fig. 29.5: Pinout configuration (top view) of the 74283 4-bit full-adder
with fast carry. Note that S=A+B, where A=A4A3A2A1,
B=B4B3B2B1, S=S4S3S2S1.
We can obtain an 8-bit adder by cascading two 74283 4-bit binary full-adders. The two
adders are connected in such a way that the carryout (C4) of the first adder becomes the
carry-in (C0) of the second adder. The second adder carries the high-order 4 bits. Figure
29.6 shows the 8-bit adder.
74283
74283
A0
5
A4
5
A1
3
A5
3
A2
14
4
S0
A6
14
4
S4
A3
12
1
S1
A7
12
1
S5
B0
6
13
S2
B4
6
13
S6
B1
2
10
S3
B5
2
10
S7
B2
15
B6
15
B3
11
B7
11
C0
7
9
C4
9
7
C4
320
C0
Fig. 29.6: Two 74283 4-bit binary adders connected to from an 8-bit adder
Twos complement subtraction
The twos (or 2s) complement of a number can be considered as the negative number. The
2s complement of a number is obtained by complementing each bit (result is also known
as the ones comlement) and then adding 1. As an example let us find the 2s complement
of 6:
6 = 0110
Complement of 6 = 1001
Twos compl. of 6 = 1001
+
1
= 1010
Thus –6 is equivalent to 1010. Therefore we can work out, say 9-6, by carrying out an
addition:
1001 = 9
+ 1010 = -6
= 10011 = ?
If we consider the MSB (bit 4) as a carryout (or overflow) bit, then the result is 0011 or 3.
To complement a number we can use inverters. But for flexibility it is more convenient to
use an EX-OR gate. Remember that for an EX-OR gate (see Lecture 22) with inputs x
and y, the output is given by F  xy  xy . We see that if y=0, then F=x, and if y=1,
F  x . Therefore we can use the second input of the gate as a control signal, to
complement or not to complement. Figure 29.7 shows the circuit for complementing a 4bit number.
321
B0
B1
B2
B3
C
Fig. 29.7: Circuit for complementing a 4-bit number B3B2B1B0,
when the control signal C=1.
To add a 1 we can use the carry-in bit (Cin) of the full-adder. Figure 29.8 shows a
subtractor.
B0
A0
A1
B1
B1
A1
A2
B2
A2
B2
322
A3
S1
S0
S2
S1
S3
S2
S4
S3
B3
B3
A3
A4
B4
C
Cin
Cout
Cout
Fig. 29.8: A 4-bit subtractor.
The control signal C is set to 1 to subtract B  B3 B2 B1 B0 from A  A3 A2 A1 A0 , and is set
to 0 to add A and B. For the full-adder we can use the 7486 which is a quadruple 2-input
EX-OR gates chip.
In the example above we assumed that B (the subtrahend) was less than the A so that A-B
is positive. To deal with the case when A is less than B we must formulate a rule (or
convention) to deal with negative numbers. One method would be to reserve one bit
position, the MSB, for the sign information. The MSB=0 for a positive number and
MSB=1 for a negative number, with the value of the number given by the remaining n-1
bits (for n-bit numbers). This method reduces the size of the number that can be
represented by 2n-1, where n is the number of bits. A better method is to use the carryout
bit. After the arithmetic operations we must check to see if the result is valid. By addition
one can get “overflow” and by subtraction one can get “underflow.” This means that the
answer (or result) is not correctly represented as it is, but in both cases simple operations
can provide the correct result. The carryout bit, Cout, gives information about
overflow/underflow. The answer is valid if:

Addition
Cout=1: The answer shows 2n too little. Therefore we must add 2n
to get correct numerical answer. The sign is positive.
Cout=0: The answer is valid.
323

Subtraction:
Cout=1: The answer is valid and the result is positive.
Cout=0: A borrow from the carry-in has occurred. The result must
be negative, and the result shows 2n too much. The correct
numerical value is found by taking the 2s complement of
the answer.
Examples:
1. Addition
(a) 9+6=1001+0110=1111=15.
Since Cout=0 (i.e. bit 4 or 5th bit is 0), the answer is valid.
(b) 9+7=1001+0111=11001=25.
Since Cout=1, the answer is invalid. (solution: use a 5-bit adder)
2. Subtraction:
(a) 9-6=1001-0110=1001+1010=10011.
Since Cout=1, the result is positive.
(b) 6-9=0110-1001=0110+0111=1101.
Since Cout=0, the result is given by the 2s complement.
Thus, 0010+1=0011=3 or 6-9=-3.
Questions
6. (a) Differentiate between a half-adder and a full-adder.
(b) Draw the logic symbol of a full-adder and give its truth table.
7. (a) What is the major disadvantage of a ripple adder and how has this
disadvantage been dealt with?
324
(c) Given two n-bit adders, how would you construct a 2n-bit adder? Sketch the
block diagram for the 2n-adder.
8. (a) Draw up a truth table of a full-subtractor. Use the inputs X, Y and Bin, and
outputs D and Bout, where D=X-Y is the difference, Bin is the borrw-in bit and
Bout is the borrow-out bit.
(b) Compare your table with Table 29.2.
Show that (i) D  X  Y  Bin , (ii) Bout  XY  X  Y Bin .
(c) Use the results in (b) and logic symbol of a full-adder to draw the circuit of a
full-subtractor.
9. The adder/subtractor circuit in Figure 29.8 is to be used to subtract 6 from
11(eleven).
(c) Which value should the control signal C be set to?
(d) What is the carry-in bit (Cin)?
(e) What are the inputs applied to A4A3A2A1 and B4B3B2B1?
(f) What is the output of the circuit: (i) in binary, (ii) in decimal?
(g) Is there a carryout and what happens to it?
Further reading:
6. Seeti, M.L.: Basic Electronics; Makerere 2003.
7. Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
8. Green, D.C.: Digital Electronics; Addison Wesley Longman Limited, Essex 1999.
325
LECTURE 30
MULTIPLEXERS & DEMULTIPLEXERS
Introduction
In this lecture the multiplexer is introduced and discussed by means of truth tables.
Applications of multiplexers are discussed. Demultiplexers are introduced and described
by use of truth tables. Lastly the encoder is defined and its application discussed.
Objectives
By the end of this lecture you should be able to:

Define a multiplexer;

Draw a truth table of multiplexer;

Name applications of multiplexers;

Use a multiplexer to realize a logic function;

Define a demultiplexer or decoder;

Draw a truth table of a priority encoder;

Name applications of priority encoders.
Multiplexers
A multiplexer (MUX), or data selector, is a digital switch which connects data from one
of several sources to a single output. The circuit’s basic function is to select any one of n
input lines and transmit that data present on that line to a single output line. Figure 30.1
illustrates the basic concept of a multiplexer.
S0
D0
S1
D1
S2
n data
D2
inputs
.
.
Single output
Sn-1
Dn-1
326
Fig. 30.1: Concept of a multiplexer; n data inputs D0, D1, …, Dn-1,
connected one at a time to a single output.
At any instant in time only one of the switches S0 to Sn-1 is closed, connecting the
associated data input to the output.
A multiplexer has 2n data inputs, n control or select inputs, and an output terminal, where
n=1,2,3, or 4. The selection of one of 2n data inputs is made by the signals applied to the
select lines. Figure 30.2 shows a block diagram of a multiplexer with 8 data inputs.
Enable
EN
D0
D1
D2
D3
D4
Output
D5
D6
D7
C B A
Fig. 30.2: Block diagram of an 8-to-1 multiplexer
The address on the select inputs C B A determines which data input is switched to the
output. Each data input has it own unique address, e.g. data input D1 has the highest
address 001 for a 3-input multiplexer and 0001 for a 4-bit multiplexer.
327
The sizes of commercially available medium scale integration (MSI) multiplexers are
limited by the number of pins available in an inexpensive IC package. The most
commonly used multiplexers come in 16-pin packages. For example the 74151 is an 8-to1 data selector/multiplexer with 16 pins. Figure 30.3 shows the pinout configuration of
the 74151.
1 D3
VCC 16
low-order
2 D2
D4 15
inputs
3 D1
D5 14
4 D0
D6 13
5 Y
D7 12
6 W
A 11
7 G
B 10
8 GND
C
Outputs
Enable
high-order inputs
Select inputs
9
Fig. 30.3: Pin-out configuration of the 74151 multiplexer
The select inputs are named C, B and A. C is the MSB and A is the LSB. The enable
input G is active low, and both active-high (Y) and active-low (W= Y ) versions of the
output are provided. D0 is the LSB and D7 is the MSB of the data bits. Table 30.1 shows
the truth table of the 74151 multiplexer.
328
Table 30.1: Truth table of the 74151 multiplexer
C
B
A
G
Y
x
x
x
1
0
‘CBA’=select input code(x=0 or 1),
0
0
0
0
D0
D7D6D5D4D3D2D1D0=input data code,
0
0
1
0
D1
G =enable input; Y=output
0
1
0
0
D2
0
1
1
0
D3
1
0
0
0
D4
1
0
1
0
D5
1
1
0
0
D6
1
1
1
0
D7
Instead of denoting the output with either 0 or 1 for each input combination, we have
written the switched inputs as D0, D1, D2,…, D7. This makes the table compact. We may
think of Y as a sum-of-products(SOP) given by Y  D0Y0  D1Y1  D2Y2  D3Y3  D4Y4 ,
where Y0  C B A G , Y1  C B AG , Y2  C BA G , etc. These are the Boolean equations
used to realize the 74151 multiplexer.
Several different multiplexers are included in the TTL and CMOS logic families, e.g.:

74157:
Quad 2-to-1 multiplexer;

74153:
Dual 4-to-1 multiplexer;

74151:
Single 8-to-1 multiplexer.
329
Some multiplexers have three-state outputs and others have open-collector outputs. The
output of some multiplexers is active-high and for some it is active-low, while the 74151
has both true and inverted outputs. The three-state outputs include a third electrical state,
in addition to the normal states of LOW and HIGH, called the high-impedance (Hi-Z) or
floating state. In this state the output behaves as if it is not connected to the circuit
(except for a small leakage current which may flow in or out of the output pin).
Applications of multiplexers
Multiplexers are obviously useful in any application in which data must be switched from
multiple sources to a destination. A common application in computers is the multiplexer
between the processor’s registers and its arithmetic logic unit (ALU). We consider two
more applications in detail below.
Parallel-to-serial converter
If a counter is connected to the select inputs of a multiplexer, the parallel input data D0,
D1, D2,…, D7 can be selected in a given order and cyclically. Figure 30.4 shows a
parallel-to-serial converter using the 74151 multiplexer. Data in parallel form is applied
to the data inputs of the 74151 and is fed out of the circuit in serial from at a speed that is
determined by the frequency of the clock applied to the counter.
Enable
Clock
C
7 G
QA
11 A
QB
10 B
QC
9 C
Counter
4 D0
Y 5
3 D1
2 D2
Data
1 D3
inputs
15 D4
330
Y 6
14 D5
13 D6
12 D7
Fig. 30.4: Parallel-to-Serial converter
Logic function generator
A 2n-input multiplexer can perform any logic function of n variables. For example, Table
30.2 show the truth table of a general logic function of three variables. The function’s
value, denoted by F0, F1, …, F7. regardless of the values chosen in the truth table, the
logic function can always be performed by connecting logic zeros and ones to the
corresponding inputs of an 8-bit input multiplexer as shown in Figure 30.5.
Table 30.2: General truth table of a 3-variable logic function F(A,B,C).
Row
A
B
C
F
0
0
0
0
F0
1
0
0
1
F1
2
0
1
0
F2
3
0
1
1
F3
4
1
0
0
F4
5
1
0
1
F5
6
1
1
0
F6
7
1
1
1
F7
331
74151
A
11 A
B
10 B
C
9 C
F0
4 D0
F1
3 D1
F2
2 D2
F3
1 D3
F4
15 D4
F5
14 D5
F6
13 D6
F7
12 D7
Y 5
F
Y 6
F
G
7
Fig. 30.5: General scheme of realizing a logic function with multiplexers.
As a specific example, suppose that F is 1 if and only if the number of inputs with a 1 are
greater than one. Looking at Table 30.2, F fulfills the above condition if we let
F3=F5=F7=1 and F0=F1=F2=F4=F6=0. Figure 30.6 shows the circuit diagram of this
particular function F.
332
+5V
R
74151
A
11 A
B
10 B
C
9 C
4 D0
5
3 D1
Y
F
Y 6
F
2 D2
1 D3
15 D4
14 D5
13 D6
12 D7
G
7
Fig. 30.5: Realization of the logic function F  A, B ,C 3,5,7
Demultiplexer
A demultiplexer (DEMUX) performs the inverse function to a multiplexer in that it has a
single input terminal and effectively switches it to any one of a number of possible
333
outputs. The required output is selected by an input address. Non-selected outputs are
either non-active or are open-circuit. Figure 30.7 shows the basic idea of a demultiplexer.
D0
D1
.
Input
.
Outputs
.
Dn-1
Fig. 30.7: Concept of a demultiplexer
The truth table of a demultiplexer has one data input, n select address inputs, and 2n data
outputs, Table 30.3 gives the truth table of a 1-to4 demultiplexer.
Table 30.3: Truth table of a 1-to4 demultiplexer.
Inputs
Outputs
Select
Data Enable
A
B
D
G
Y3
Y2
Y1
Y0
x
x
x
1
1
1
1
1
0
0
D
0
0
1
1
1
0
1
D
0
1
0
1
1
1
0
D
0
1
1
0
1
334
1
1
D
0
1
1
1
0
For the enable input G=0 (or G =1) the outputs will be high for whatever select address
and for whatever data input D. the Boolean expressions describing the logic function for
the circuit are given by:
Y0  ABD , Y1  AB D , Y2  A BD , Y3  A B D
Some examples of demultiplexers in the TTL and CMOS logic families:

74139:
Dual 2-to-4 demultiplexer;

74138:
Single 3-to-8 demultiplexer.
Decoders
A decoder can detect a code at its input and deliver a single output that indicates the
presence of that code. The code is the address of the output to be made active. The
applications of decoders include alerting a system that a specified input has arrived,
selecting memory chips in a microprocessor system, or a number comparator. The
operation of a decoder is similar to that of a demultiplexer in that there is only one active
output at a time. However, no data is routed to the output and the address is decoded
when the selected output is made active. A demultiplexer can be used as a decoder when
the demultiplexer data input becomes the decoder enable input.
A binary decoder with an enable input can be used as a demultiplexer. The decoder’s
enable input is connected to the data line, and its select inputs determine which of its
output lines is driven with the data bit. The remaining output lines are negated. Thus, the
74139 can be used as a 2-bit 4-output demultiplexer with active low data inputs and
outputs, and the 74138 can be used as a 1-bit 8-output demultiplexer. In fact, the
manufacturer’s catalog typically lists the ICs as ”decoders/demultiplexer.”
335
Encoder
An encoder performs the opposite function to a decoder. Only one of its inputs is active at
a time and this input produces a specified output data word. A code converter that
converts from either decimal or hexadecimal into some other code is usually known as an
encoder.
The main application of encoders is in conjunction with keyboards, where a single key
operation must produce a unique binary code. If two, or more, keys are pressed
simultaneously two inputs become active together and will give an incorrect output. To
avoid this happening, a priority encoder is often employed. If more than one input is
applied to a priority encoder it encodes the input with the highest magnitude (highestorder data) and ignores all other lower magnitude inputs. The 74148 is an 8-to-3 (8-line
to 3-line) priority encoder. Figure 30.8 shows its pinout configuration and Table 30.4
shows its truth table.
74148
I4
1
16
VCC
I5
2
15
E0
I6
3
14
GS
I7
4
13
I3
E1
5
12
I2
A2
6
11
I1
A1
7
10
I0
GND
8
9
A0
Fig. 30.8: Pinout configuration of the 74148 8-to-3 priority encoder.
336
Table 30.1: Truth table for the 74148 8-to-3 priority encoder.
Inputs
Outputs
GS E 0
E1
I 0 I1 I 2 I 3 I 4 I 5 I 6 I 7
A2 A1 A0
1
x x x x x x x x
1 1 1
1
1
0
1 1 1 1 1 1 1 1
1 1 1
1
0
0
x x x x x x x 0
0 0 0
0
1
0
x x x x x x 0 1
0 0 1
0
1
0
x x x x x 0 1 1
0 1 0
0
1
0
x x x x 0 1 1 1
0 1 1
0
1
0
x x x 0 1 1 1 1
1 0 0
0
1
0
x x 0 1 1 1 1 1
1 0 1
0
1
0
x 0 1 1 1 1 1 1
1 1 0
0
1
0
0 1 1 1 1 1 1 1
1 1 1
0
1
x = irrelevant
The 74148 encodes 8 data lines I 0 , I 1 , …, I 7 to a 3-line binary A2 A1 A0 . Cascading
circuitry (enable input E1 and enable output E 0 ) has been provided to allow octal
expansion without the need for external circuitry. The encoder has 8 active-low inputs
337
and 3 active-low outputs, and it performs octal-to-binary conversions. The outputs A2,
A1, A0 contain the number of the highest-priority asserted input, if any. For example, the
output 001, which is the binary encoding of decimal 6, is the number of the priority
inputs asserted when the device is enabled and one or more of the request inputs is
asserted. The E 0 signal is an enable output designed to be connected to the E1 input of
another 74148 that handles lower-priority requests. E 0 is asserted if E1 is asserted but no
request input is asserted; thus, a lower-priority 74148 may be enabled.
Questions
1. (a) Define a multiplexer.
(b) Why is a multiplexer also called a ‘data selector?’
(c) Name two applications of multiplexers.
2. (a) Draw up the truth table of a 4-input multiplexer (MUX).
(b) Write down the Boolean equation for the MUX in (a).
(c) Draw a circuit diagram for the logic function in (b).
3. A multiplexer may be used to realize a logic function (see Figure 30.5). Use an 8to-1 multiplexer (e.g. the 74151) to realize the logic function F  A, B,C 0,1,3,6 .
4. (a) Point out the difference between a demultiplexer (DEMUX) and a decoder.
(b) Draw the truth table for a1-to-4 DEMUX.
5. (a) What is a priority encoder?
(b) Complete the truth table below of a 4-to-2 line priority encoder.
Inputs
Outputs
338
I0 I1 I2 I3
A1 A0
(c) Draw a circuit diagram to realize the above encoder.
Further reading:
Wakerly, J.F.: Digital Design; Prentice Hall, NJ 1994.
339
LECTURE 31
DIGITAL-TO-ANALOG CONVERTER
Introduction
In this lecture the weighted-resistor method and the R/2R-ladder method for digital-toanalog converters (DAC) are discussed with examples of 4-bit DACs. The equations for
the output voltage are derived and resolution defined.
Objectives
By the end of this lecture you should be able to:

Describe how a weighted-resistor DAC works;

Describe how a R/2R-ladder resistor DAC works;

Explain why the ladder method is preferred over the weighted-resistor method;

Define the resolution of a DAC.
Basic features of converters
The function of many electronic systems is to receive some input information, process it
in some way, and then pass the processed information to its destination. If analog signals
are to be processed to or from a digital computer, some kid of signal converter is
required, as illustrated in Figure 31.1.
Analog input
ADC
Computer
DAC
Analog output
340
Fig. 31.1: Analog signal input/output: ADC=Analog-to-digital converter,
DAC=Digital-to-analog converter.
Digital processing of analog signals by computer offers several advantages including the
following:

Accuracy;

Speed;

Flexibility;

Repeatability;

Ability to perform complex operations.
One consequence of using a computer is that data can only be input at discrete points in
time. Hence only sampled values of an analog signal can be taken and not the true signal
itself. An obvious requirement is that the signal should not change significantly between
samples, otherwise information is lost, and a high enough sample rate must be used.
Likewise, the computer can only output data at discrete points in time. Horizontal
portions of the waveform occur while the next update of the output amplitude is awaited.
In many cases the staircase effect is not noticeable because the analog signal is slowly
varying, or because the steps are smoothed out by a smoothing filter at the output of the
converter.
A second consequence of using a computer follows because data are presented by words
having a finite number of bits. An n-bit data word can assume any of 2n different codes
(n-bit combinations of 0’s and 1’s). Each code is made to correspond to a fixed level of
analog signal amplitude, and the levels are usually chosen to be equal-spaced. This means
that a sampled value of analog signal is given a code which has the nearest corresponding
fixed level. This process of assigning the nearest fixed level to a sample is called
quantization and gives rise to a quantization error because the exact value of the original
signal can not be recovered. Quantization errors can have magnitudes up to half the
spacing between quantization levels. It is important therefore to choose a sufficient
number of data word bits so that that uncertainty due to quantization is kept to an
acceptable amount.
341
Binary codes
Binary codes (or natural binary codes) are usually for unipolar signals (i.e., signals that
are either always positive or always negative). Positive polarities are often adopted. The
output voltage from an n-bit digital-to-analog converter (DAC) is given by
n
bnk VFSR
 n
k
2
k 1 2
Vout  VFSR 
n 1
2
k 0
k
bk
(31.1)
where the bits bn-1 to b0 that make up the n-bit word can each take on the value 0 or 1, and
VFSR is the full-scale range of the output voltage. b0 is the least significant bit (LSB) and
bn-1 is the most significant bit (MSB). In general the largest value of Vout is given by
1 1/ 2 V
n
FSR


, which is 1 LSB less than VFSR , so that Vout ranges from 0 to 1 1 / 2 n VFSR


. If n is large enough such that 1 / 2 n  1 , then 1  1 / 2 n VFSR  VFSR .
The smallest increment of voltage that can be obtained is called the resolution and
corresponds to the weight assigned to the LSB.
Resolution = VFSR / 2 n
(31.2)
Resolution is usually expressed relative to the full-scale range voltage VFSR , and therefore
has a value of 1/2n. The data word lengths encountered in practice in all converters use
with computers fall in the range of 8 bits to 16 bits. For higher number of bits the costs
and difficulty of handling signals so as to preserve accuracy increase rapidly.
For analog-to-digital conversion (ADC) using binary coding, the task of the converter is
to find that binary code which corresponds most closely to the analog input signal
amplitude. Bits bn-1 to b0 are generated so as to satisfy the equation
342
n
bn k
 Vin  VQE
k
k 1 2
VFSR 
(31.3)
The quantization error variable VQE is included because the left-hand side f the equation
assumes discrete values, whereas the input voltage Vin may assume any value in the
continuous range of the converter. Typical values for VFSR voltages for ADCs and DACs
are 5V and 10V. A value of 10.24V is sometimes used because it equals 210  10 mV and
the binary weights are then convenient multiples of 10mV.
Equations (31.1) and (31.3) are called the converter transfer functions. These transfer
functions can be plotted graphically. For the DAC, Vout is plotted against the binary
codes. The resulting graph is a series of dots because there s a unique voltage level for
each discrete binary code. For the ADC, the output codes are plotted against the input
levels. The resulting graph is a “staircase.” In practice, component imperfections within
the converter cause deviations from the ideal function.
Digital-to-analog converter (DAC)
There are basically two methods which are commonly used for digital-to-analog
conversion. The two methods are the weighted-resistor method and the R-2R ladder
method.
Weighted-Resistor method
Figure 31.2 shows a 4-bit binary-weighted resistor DAC.
If we assume that all the switches S0 to S3 are closed, then for an ideal op-amp the
inverting-input node equation can be written as
I 0  I1  I 2  I 3  I F  0
343
VRef
I3
I2
R
I1
I0
2R 4R 8R
RF
0
1
S3
S2
IF
S1
S0
(MSB)
Vout
+
Fig. 31.2: A 4-bit Weighted-Resistor DAC
Since the non-inverting input is zero, then the inverting input is also zero (ideal op-amp).
Therefore it follows that
I0= VRef/8R, I1= VRef/4R, I2= VRef/2R, I3= VRef/R, IF= Vout/RF.
Therefore the node equation becomes
VRef (1/8R + 1/4R + 1/2R + 1/R) + Vout/RF=0
or
1
1
1 
1
Vout   RF VRe f  



 R 2 R 4 R 8R 
344
(31.4)
Equation (31.4) applies to the case when all the switches S0 to S3 are closed. To be able to
write down a general equation for any combination of switches, we represent the switches
S0 to S3 by bits b0 to b3, respectively. Each of these bits can be either 0 for an open
switch, or 1 for a closed switch. Then equation (31.4) becomes:
b 
b
b
b
Vout   RF VRe f  3  2  1  0 
 R 2 R 4 R 8R 
(31.5)
We also write the resistors 8R, 4R, 2R and R in general as
Ri  2 3i R ; i = 0,1,2,3
With this expression for the resistors, we can write equation (31.5) in a more compact
form as
Vout 
3
 RF
i
V
Re f  2 bi
23 R
i 1
(31.6)
We note that
3
2 b
i
i 1
i
 2 3 b3  2 2 b2  21 b1  2 0 b0
= 8b3  4b2  2b1  b0
is equal to the decimal-value of the binary code input word b3b2b1b0.
In general, for an n-bit DAC equation (31.6) becomes
Vout 
n 1
n 1
 RF
 2 RF / R
i
i
V
2
b

V
Re f 
i
Re f  2 bi
n
2 n 1 R
2
i 1
i 1
345
(31.7)
The maximum output voltage is obtained when the decimal-value of the binary code
input is maximum. This is the case when all the n bits are equal to logic 1:
n
2 b
i
i
i 1
 1  2  2 2  2 3    2 n 1
This is a geometrical progression and its sum is equal to 2n-1. Therefore using equation
(31.7) the maximum output voltage is given by
Vout,max 
 RF
 2 RF
VRe f 2 n  1 
VRe f 1  1 / 2 n
n 1
R
2 R




If we let
VFSR 
 2 RF
VRe f
R
(31.8)
then
Vout  VFSR 
1
2n
n 1
2 b
i
i 0
i
(31.9)
and


Vout,max  1  1 / 2 n VFSR
(31.10)
To obtain a positive value for VFSR (see equation (31.9)) a negative reference voltage VRef
is used.
The smallest change of the analog voltage that can be represented by a digital word is
called the resolution of the converter. It corresponds to the weighting of the LSB. Thus
the resolution V can be written as
V  Vout bn1  0, bn2  0,, b1  0, b0  1
=
V FSR
2n
This is usually expressed relative to the full-scale range voltage VFSR as
346
V
1
 n
VFSR 2
(31.11)
The weighted-resistor method has a setback. The high range of resistor values, R to 2n-1R
for an n-bit converter, is difficult to manufacture with adequately matched temperature
coefficients and aging properties. For this reason the method is limited to DACs with up
to 4 or 5 bits. The R-2R ladder method eliminates the above problem.
R-2R Ladder method
Figure 31.3 shows a 4-bit R-2R ladder DAC.
R
R
R
VRef
I3
I2
2R
I1
2R
I0
2R
2R
2R
RF
IF
S3
0
S2
1
0
S1
1
0
S0
1
0
1
Vout
+
Fig. 31.3: A 4-bit R-2R Ladder DAC
347
R
R
R
IRef
+
IRef
I3
I2
I1
I0
VRef
+
2R
2R
2R
2R
2R
 VRef
R
Fig. 31.4: Distribution of the currents of the 4-bit Weighted-Resistor DAC
when all the switches are in position 0
Because the resistor values are now confined to a two-to-one range, difficulty in
obtaining a wide range of resistors, as required for the weighted-resistor method, is
overcome. Figure 31.4 shows the distribution of the currents when all the four switches
S0 to S3 are in position 0 (i.e., all the 2R resistors are connected to ground). If we
combine the resistors starting from the left; 2R//2R=R in series with R, giving again 2R.
If this is repeated we end up with the simple series equivalent circuit shown on the righthand side in Figure 31.4, in which the reference voltage VRef is in series with the resistor
R. Hence IRef=VRef/R.
If we proceed as above but without eliminating the branch containing the current I3, we
get that I 3 
1
1
1
1
I Re f . Similarly I 2  I 3 , I 1  I 2 , and I 0  I 1 . If we express all the
2
2
2
2
currents in terms of IRef we get
I3 
1
1
1
1
I Re f , I 2  I Re f , I 1  I Re f , I 0  I Re f
2
4
8
16
348
For any combination of the switches S0 to S3, the currents I0 to I3 may be written as
I3 
1
1
1
1
I Re f b3 , I 2  I Re f b2 , I 1  I Re f b1 , I 0  I Re f b0
2
4
8
16
where b3b2b1b0 is the input binary code. The bits b0 to b3 can each assume the values 0 or
1, corresponding to the bit positions of the switches in Figure 31.3. Now for an ideal opamp we have that I 0  I1  I 2  I 3  I F  0 , and since the inverting input is on virtual
ground we also have that IF=Vout/RF. Therefore the output voltage comes to
Vout  VFSR 
1
8b3  4b2  2b1  b0 
25
where
VFSR 
 2 RF
VRe f .
R
This scheme can easily be extended to higher resolutions, provided suitably accurate
resistors are available. Therefore in general, for an n-bit R-2R ladder DAC the output
voltage can be written as
Vout  VFSR 
1
2
n 1
n 1
2 b
i
i 0
i
(31.12)
A comparison of this equation with equation (31.9) shows a factor of ½ in the latter.
The switches in Figure 31.3 are usually FET switches in form of an IC chip. Most
practical DAC circuits are based on the R-2R ladder method. Typically the FET switches,
and associated drive circuitry, are made as an integrated circuit chip, and the passive R2R ladder is made in thin film form on a separate substrate. Both chips are mounted in the
same encapsulation.
349
Questions
1. (a) List four advantages of the digital processing of analog signals by a computer.
(b) Why are converters (ADC or DAC) essential?
2. (a) What is meant by the resolution of a DAC?
(b) Draw the circuit diagram of a 3-bit weighted-resistor DAC.
(c) What is the maximum output voltage of the DAC in (b) if VRef=-6V, R=1k,
RF=1k. [Ans: 10.5V]
3. (a) What is the disadvantage of the weighted-resistor method of constructing a
DAC? How can this disadvantage be overcome?
(b) Draw the circuit diagram of a 3-bit R/2R-ladder DAC.
(c) Assuming that R=RF=10k and VRef=-5V, calculate for the DAC in (b):
(i)
the full-scale range voltage; [Ans: 10V]
(ii)
the maximum output voltage; [Ans: 7/1.6 V = 4.375V]
(iii)
the output voltage for the input word 101.
[Ans: 5/1.6 V = 3.125V]
Further reading:
1. Seeti, M.L.: Basic Electronics; Makerere 2003.
2. Crecraft, D.I., et al.: Electronics; Chapman and Hall 1994.
350
LECTURE 32
ANALOG-TO-DIGITAL CONVERTER
Introduction
In this lecture three methods of analog-to-digital conversion will be discussed. The there
methods give rise to: the flash converters, the successive approximation converters and
the dual-slope integration converters. The advantages of one over the others will e
discussed.
Objectives
By the end of this lecture you should be able to:

Describe how a flash converter works;

Describe how a successive approximation converter works;

Describe how a dual-slope integration converter works;

List the three converters above in order of their speed of conversion.
Brief introduction to ADC
The output of an analog-to-digital converter (ADC) is a binary code representing the
analog input. The following methods, in order of decreasing speed of conversion, are
commonly used:
1. Flash conversion;
2. Successive approximation method;
3. Dual-slope method.
We shall look at the above methods of conversion one by one.
Flash converters
Flash converters (or parallel converters) are used for maximum speed. In principle the
input signal is compared with all possible subdivisions of the reference voltage at the
same time. Figure 32.1 shows a 3-bit flash converter.
351
Vin
VRef
R/2
V8
8
R
V7
7
R
Priority Encoder
(Code Converter)
6
V6
R
V5
5
b2
b1
R
V4
b0
4
R
3
V3
R
2
V2
R
V1
1
R/2
Fig. 32.1: A 3-bit flash converter
352
The chain of resistors divides the reference voltage VRef to give 1-LSB steps except at the
two ends where a ½-LSB interval is generated. In the example in Figure 32.1 the chain of
resistors add up to 8R, so that the voltages at the comparators inputs can easily be
calculated using the potential divider rule. For example the voltage at the first comparator
(comparator labeled 1) is equal to
R/2
1
1
VRe f  VRe f = LSB , since 1 LSB = VRef/23 (resolution).
8R
16
2
The voltage at the second comparator is equal to
3R / 2
3
3
VRe f  VRe f = LSB , etc.
8R
16
2
A comparator compares two input voltages Vin and Vi, and outputs a logic 1 if Vin is
greater than Vi, and outputs a logic 0 otherwise. (i.e., for VinVi). For example in Fgure
32.1 the first comparator compares Vin with
with
1
LSB, the second comparator compares Vin
2
3
LSB, etc. The outputs of the comparators are fed to a priority encoder (see
2
Lecture 30) which produces the digital code b2b1b0.
In general, an n-bit flash converter uses 2n comparators which limits the method to 8 or 9
bits. The chain of resistors consists of 2 resistors each of R/2 at either end and (2 n-1)
resistors
RS  2 
of
R

in
the
middle,
giving
a
combined

(series)
resistance
R
 2 n  1 R  2 n R . If the comparators are numbered 1 through to 2n, starting
2
at the bottom, the voltage Vi on the i-th comparator is given by
Vi 
i  1R  R / 2 V
RS
Re f
or
353
Vi 
2i  1 V
2
n 1
Re f
, i=1,2,…,2n
(32.1)
The resolution V is given by V  Vi 1  Vi , which gives
V 
VRe f
2n
(32.2)
By definition this should correspond to the weight assigned to the LSB. Thus, we can also
write Vi in equation (32.1) as
 1
Vi   i   LSB , i=1,2,…,2n
 2
(32.3)
Example:
Suppose the 3-bit ADC in Figure 32.1 uses VRef=12V, and let the input voltage Vin be
4.65V.
The resolution of the ADC is given by equation (32.2) as
V 
VRe f
2
n

12
 1.5 V
8
The reference voltages Vi at the comparator i is given by equation (32.1) as
Vi=(2i-1)0.75V, i=1,2,…,8
or
(V1, V2, V3, V4, V5, V6, V7, V8)=(0.75, 2.25, 3.75, 5.25, 6.75, 8.25, 9.75, 11.25V).
Thus comparator 1 compares Vin=4.65V with V1=0.75V and outputs a 1; comparator 2
compares Vin=4.65V with V2=2.25V and outputs a 1; comparator 3 compares Vin=4.65V
with V3=3.75V and outputs a 1, etc. Comparator 8 compares Vin=4.65V with V8=11.25V
and outputs a 0. The eight comparators together output an 8-bit code 00000111, which
the priority encoder converts into a number between zero and seven (3-bit code).
354
Flash converters are the fastest ADC. They vary from 4-bit to 10-bit, cost and size being
the limiters. Their speeds range from 15 to 300 msps (mega-samples per second), e.g., the
TRN TDC 1084 is a bipolar, 8-bit 20msps converter costing about US$100.
Successive approximation converters
The successive approximation method is the technique used in most ICs. The method
operates by repeatedly comparing the analog signal voltage with a number of
approximate voltages which are generated at a DAC-output. Figure 32.2 shows a block
diagram of a successive approximation register (SAR) and a DAC.
Clock
Comparator
Successive
Vin
V1
START
Approximation Register
(SAR)
STATUS
V2
bn-1
.
.
b1
.
.
.
.
.
.
DAC
V2
Fig. 32.2: Successive approximation ADC
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b0
The SAR is a shift register which includes necessary logic to use the comparator voltage
V1 so as to find the binary code bn-1….b1b0 such that the DAC output is closest to the
input voltage Vin. Initially the shift register is cleared and then the DAC output is zero.
Conversion is initiated by a start signal at the input terminal START. The first clock
pulse then applies the MSB (i.e. bit bn-1) of the register to the DAC which produces a
voltage V2. If Vin>V2, the MSB is retained (stored by a latch).If VinV2, the MSB is made
logic 0. The next clock pulse applies the next-lower significant bit (bn-2) to the DAC
which produces another voltage V2. Again comparison between Vin and V2 is made and
the bit either retained or discarded.
A succession of similar trials are carried out and after each trial the shift register output
bit is either retained or discarded. Once n+1 clock pulses have been supplied to the
register, the conversion has been completed and the register output gives the digital word
that represents the analog voltage. The status output terminal STATUS is used to indicate
whether the conversion is complete and the data is ready for use or the DAC is still busy.
Example
Consider a 4-bit ADC with VFSR=16V. Suppose that Vin=5.7V. Figure 32.3 shows the
timing diagrams.
The SAR first tries b3=1 (all the lower bits are 0), which gives V2=8V. Since Vin=5.7V is
less than 8V, b3=1 is discarded and made low, b3=0. Then b2=1 is tried: V2=4V and since
Vin>4V, b2=1 is retained. So now we have b3b2b1b0=0100.. Next b1=1 is tried: now we
have b3b2b1b0=0110 or V2=6V. Since Vin<6V, b1=1 is discarded, so that b3b2b1b0=0100 or
V2=4V. Lastly b0=1 is tried giving b3b2b1b0=0101 or V2=5V: Since Vin>5V, b0=1 is
retained, giving a final result b3b2b1b0=0101. this is what will appear at the output of the
DAC at the beginning of the sixth clock pulse T5. Note that immediately after the first
pulse T0, a “start” command resets all bits to zero and sets the STATUS signal to “busy”
to indicate that conversion is in progress. Subsequent events are synchronized with the
clock.
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For our example the output code corresponds to 0101=5V, whereas the nearest code to
Vin=5.7V in fact corresponds to 0110=6V. A close examination of the method shows that
the result will always be the code producing a DAC output just less than Vin. This is due
to the ADC not being ideal, resulting in the presence of an offset error of ½LSB. The
offset occurs in all types of ADCs which use a DAC in a feedback loop and is corrected
by subtracting a ½LSB offset from the DAC output V2.
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V2
8
7
6
5.7V
5
4
t
T0
T1
T2
Clock
START
b3 (MSB)
b2
b1
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T3
T4
T5
b0
STATUS
Conversion time
Fig. 32.3: Timing diagrams for a 4-bit Successive Approximation ADC
Dual-Slope Integration Converters
An integrating ADC measures the time taken for a capacitor to charge to determine the
input analog voltage and then converts this time into a digital word. The dual-slope (or
dual-ramp) method, illustrated in Figure 32.4, is widely used in digital voltmeters and
panel meters, but is also used for analog input to computers.
Vin
S1
Clock
V(t)
R
S2
C
V0(t)
-VRef
Control
START
Logic
+
STATUS
Integrator
Comparator
Counter
bn-1
.
.
.
b0
Fig. 32.4: Dual-slope ADC block circuit diagram
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START
STATUS
BUSY
READY
T
T
t
g1=-Vin/RC
g2=VRef/RC
V0(t)
Fig. 32.5: Timing diagrams for the dual-slope ADC
The block diagram consists of four major parts: the integrator, the comparator, a control
logic unit, and a binary counter. The integrator’s output voltage V0(t) is given by
t
V0 (t )  
1
V ( )d
RC 0
The operation sequence of the converter begins with the arrival of the “start” command as
shown in the timing diagram in Figure 32.5. Switch S1 is momentarily closed to discharge
the capacitor C and reset the integrator output V0(t) to zero. At the same time the counter
is set running, switch S2 is switched to the input voltage Vin and the status signal is set to
“busy” to indicate that conversion is in progress.
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Assuming that Vin is positive, the integrator produces a negative-going ramp whose slope
g1=-Vin/RC is proportional to Vin. After a fixed time T, as determined by the counter
reaching a predetermined value, the switch S1 is turned to the reference voltage –VRef. At
this time the counter is reset and again set running in order to determine how long it takes
to return the integrator output to zero. The integrator now produces a positive-going
ramp, with constant slope g2=VRef/RC. After a period of time T, the integrator output
reaches zero. This condition is detected by the comparator, which signals the counter to
stop. The counter then holds a count which is a measure of the time T. The status signal
is reset to “ready” to indicate that conversion is complete. We summarize the operation
sequence as follows:
1. Momentarily close switch S1 (in order to reset V0);
2. Simultaneously: set counter running and set switch S2 to V=Vin;
3. After a fixed time T switch S2 to V=-VRef, and rest counter (or note
counter contents);
4. Stop the counter when V0=0.
We see that after time T, the integrator output voltage is given by
T
V0 (T )  
=
1
V (t )dt
RC 0
T
RC
1 T

  V (t )dt 
T 0

or
V0 (T )  VRe f  
T
Vin
RC
(32.4)
T
1
where Vin   V (t )dt , the average value of Vin over the interval time T. The gradient g2
T 0
of the positive-going ramp is given by g2=VRef/RC. We also see that from the graph in
Figure 32.5 that g2=V0(T)/T=-VRef/T. Hence
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RC=T
(32.5)
Combining equations (32.4) and (32.5), we obtain
Vin 
T
VRe f
T
(32.6)
If the count representing T is chosen to be the full-scale of the converter, then the final
counter output conveniently equals the average Vin as a proportion of VRef.
This type of converter has two useful properties. Firstly, the accuracy of the conversion,
as can be seen from equation (32.6), does not depend on the accuracy of the passive
components R and C, or the clock frequency. Secondly, the average value of V in is
converted. This means that the fluctuations in the signal over the time interval T are
averaged out. A common type of unwanted fluctuations is that due to the 50Hz mains
supply. By choosing T to be equal to an integral number of periods of the mains supply
the average value of any interference voltage in the circuit is zero and its effect is
therefore eliminated.
Questions
1. (a) Name three methods you know employed in ADC.
(b) How do the above methods compare in speed (or time of conversion)?
2. (a) A 4-bit ADC has a resolution of one count per 200mV. If an analog voltage of
peak value 2.1V is applied to the circuit, what will be the output digital word?
[Ans: 1010]
(b) An ADC has a resolution of 100mV per count. Determine the analog signal
voltage that is represented by the third significant bit at the output.
[Ans: 0.4V]
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3. (a) Draw the diagram of a 2-bit flash ADC.
(b) If the reference voltage used is 15V, what is the largest analog voltage that can


be converted? [Ans:11.25V] [ Vout  VRe f / 2 n  Dec.No.  Re solution  Dec.No.
]
(c) Determine the digital word at the input of the priority encoder if the analog
voltage were 10.45V. [Ans: 7]
4. (a) The maximum input voltage to a successive approximation ADC is 5V.
Calculate the voltage corresponding to the LSB if,
(i) 8 bits, (ii) 16 bits, are used.
[Ans: (i)1/51 V  9.61mV, (ii)1/13107 V  0.076mV ]
Hence compare the circuits on the basis of both speed and noise.
(b) An analog signal of peak voltage 5V is applied to a successive approximation
4-bit ADC. Sketch the output voltage of the DAC.
Further reading:
3. Seeti, M.L.: Basic Electronics; Makerere 2003.
4. Crecraft, D.I., et al.: Electronics; Chapman and Hall 1994.
5. Green, D.C.: Digital Electronics; Addison Wesley Longman Limited, Essex 1999.
6. Cook, B.M. and White, N.H.: Computer Peripherals; Edward Arnold, UK 1995.
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