Differential Phase Frequency Detector with
Zero Systematic Timing Misalignment
George von Büren 1), Student Member, IEEE, Christian Kromer 2), Member IEEE,
Silvan Wehrli 1), Student Member, IEEE, Alex Huber 3), Member IEEE,
Thomas Morf 4), Member IEEE, and Heinz Jäckel 1), Member, IEEE
1)
Swiss Federal Institute of Technology (ETH) Zurich, Electronics Laboratory, Switzerland
Email: george.vonbueren@ife.ee.ethz.ch; Tel: +41 44 632 43 54; Fax: +41 44 632 12 10
2)
Aprius Inc., Sunnyvale, CA 94085, USA
3)
Institute of Microelectronics, University of Applied Sciences Northwestern Switzerland
4)
IBM Research, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland
Abstract- This paper presents a differential currentmode logic (CML) phase frequency detector (PFD)
targeted for charge pump phase-locked loops (PLL). This
PFD operating with a reference frequency up to 1.6 GHz is
optimized for minimal timing misalignment between
UPn (inverted) and DN (non-inverted) pulses and short
(130 ps) concurrent UPn/DN pulses. Consequently, this
PFD is not a dominant source for the static phase error
and resulting reference spurs of the PLL. In addition, the
small turn-on-time of the concurrent UPn/DN pulses
reduces the in-band noise contribution of the PLL.
Index Terms- Phase-locked loop, phase frequency
detector, CML, CMOS.
I. INTRODUCTION
Phase-locked loop (PLL) architectures (Fig. 1)
often incorporate a tri-state phase frequency detector
(PFD) to detect the phase difference between the
divided output signal DIV and the reference signal REF
and to control the NMOS and PMOS switches of the
charge pump (CP) with the DN and UPn signals.
CP
UPn
REF
PFD
DN
DIV
iCP
vLF
VCO
OUT
ZLF
DIVIDER
Fig. 1. Charge pump PLL architecture.
Fig. 2(a) depicts a commonly used tri-state PFD
consisting of two edge-triggered resettable D-type
master-slave flip-flops (D-FF) and one AND gate. The
timing diagram of the PFD signals and charge pump
current iCP is illustrated in Fig. 2(b). The delay in the
reset path, illustrated by the block DELAY, has to be
long enough to eliminate a dead zone and so to maintain
the linearity of the PFD/CP transfer function. The PFD
offers also frequency-error detection and thus a
theoretically unlimited capture range.
In reality, the PFD has an operation speed
limitation due to the feedback loop that is present to
reset the PFD [1]. The maximum PLL comparison
frequency can be determined by considering the
situation when the clock signals REF and DIV are 180°
out of phase. For correct operation of the PFD, the
comparison frequency must not be higher than
1/(2THP,MIN), where the minimum half period THP,MIN
includes the delay of the AND gate, the propagation
time inside the flip-flops and the time needed to reset
the flip-flops.
REF
REF
”1”
CLK Q
D
R
UP
DELAY
”1”
DIV
R
D
CLK Q
DIV
UP
AND
DN
DN
icp
(a)
(b)
vLF
Fig. 2. Conventional tri-state phase frequency detector
(PFD): (a) Schematics, (b) timing diagram.
In order to handle higher reference frequencies a
combined phase and frequency detector (PD2) has been
proposed in [2] and the schematic and timing diagram
of its phase detector are drawn in Fig. 3(a) and (b),
respectively. Hence, when comparing high frequency
clocks, this phase detector offers an alternative to a
Gilbert cell (XOR) phase detector, especially when the
loop has to lock to a phase difference of zero degree.
But with lower PLL reference frequencies, the duration
of concurrent UP/DN pulses of the conventional PFD
(Tswitch1 = tAND + tDELAY + tFF,R01) is shorter than the one
of PD2 (Tswitch2 = 1/(4fref)) as illustrated in Fig. 2(b) and
Fig. 3(b). Shorter UP/DN pulses are preferred when a
charge pump based PLL topology, as depicted in Fig. 1,
is applied, because the PLL phase noise is affected by
noise sources of the charge pump during the time when
the switches are closed. As a consequence, it is
desirable to employ PFDs with short concurrent UP/DN
pulses whenever possible. In Section II, the design of a
fully differential PFD is presented. Important issues are:
1) the minimum UP/DN pulse width and 2) the
maximum operating frequency. Measurement results of
two PLLs with this PFD serving as verification
examples are presented in Section III, followed by the
conclusion in Section IV.
timing mismatch between UPn (UPN - UPP) and DN
(DNP - DNN) pulses is zero. Furthermore, a PFD
consisting of CML generates less switching noise on the
supply voltage and has a better immunity to supply
variations compared to CMOS PFDs.
resetable D-FF I
D-latch I
AMP 1
qrp
DP dp
qp
qrn
DN dn
qn
CM
CP cp
CP
CN cn
rp rn
RP RN
“1“
“0“
REFP
REFN
D-latch III
q1p
dp
qp QP q1n
dn
qn QN
cp
cn
rp rn
RP RN
IP
IN
ON
OP
AMP 3
q3n
q3p
UPP
IP
IN
UPN
sep
REF
REF
AND
AMP 5
UP
rep
ren
DIV
DIV 90°
AND
DIV 0°
DN
icp
vLF
(b)
II. CIRCUIT DESIGN
Single-ended sequential PFDs suffer from an
inherent delay difference between the UPn and DN
pulses due to the inverting stage needed to control the
PMOS transistor [Fig. 4(a)]. As shown in Fig. 4(b), the
net current injected by the charge pump into the loop
filter jumps to +iCP and -iCP, disturbing the VCO control
voltage vLF periodically even if the loop is locked. This
increases jitter and reference spurs. The skew between
UPn and DN can be reduced by delaying the UP signal
with a complementary pass gate or by adjusting the
delays with scaled inverter chains.
CP
REF
DIV
PFD
DN
iCP
REF
DIV
UPn
DN
(a)
IP
IN
mup
mun
ZP
ZN
icp
(b) vLF
Fig. 4. (a) Single-ended PFD, inverting stage and charge
pump. (b) Effect of skew between UPn and DN.
Our goal is to achieve a minimum systematic timing
misalignment. Thus, we propose a fully differential
PFD. The schematic of the PFD is illustrated in Fig. 5.
The PFD is fully symmetric and consists of differential
current-mode logic (CML). Therefore, its systematic
“1“
anp
ann
AP
AN
BP
BN
ZP
ZN
“0“
sep
sen
RP RN
rp rn
CP
cn
CN
CN
CP cp
qdn
qn
DM dn
qp qdp
DP dp
DIVN
DIVP
“0“
“1“
D-latch II
resetable D-FF II
reset
AND
BP
AP
AN
BN
SM
Fig. 3. Phase detector of the combined phase and
frequency detector (PD2) [2] with the divided I/Q signals
DIV 0° and DIV 90°: (a) Schematics, (b) timing diagram.
UPn
ON
OP
UP
DN
(a)
MUX
SP
ON
OP
RP RN
rp rn
cn
cp
q2n
qn QN
dn
q2p
qp QP
dp
IN
IP
OP
OM
q4p
q4n
sen
DNN
IN
IP
OP
ON
DNP
D-latch IV
AMP 2
AMP 4
Fig. 5. Proposed CML PFD architecture.
vb
vb
dp
vb vb
qp
qn
dn
cn
ZP ZN
AN
BN AP
BP
BN
AN BP
AP
cp
rn
rp
(a)
(b)
Fig. 6. (a) Schematics of resetable CML D-latch,
(b) Schematics of CML AND gate.
The schematics of the resettable CML D-latch and
CML AND gate are shown in Fig. 6(a) and Fig. 6(b),
respectively. The CML multiplexer (MUX) is a Gilbertcell and is needed in the reset path as part of the startup/power-on circuit in order to guarantee a correct
initial differential reset signal (rep - ren) at the inputs of
the D-FFs. The five differential amplifiers (AMP1 …
AMP5) are inserted to reduce the load of the preceding
stages and to sharpen the rising and falling edges. Short
rise and fall times reduce the jitter generation of the
PFD. All CML circuits in this PFD employ PMOS
loads to obtain an area-efficient compact layout.
In order to investigate if the proposed PFD has no
dead zone and to determine the maximum operating
frequency a timing analysis has been performed (Fig. 7).
Typical propagation delays and setup/hold times of the
gates and flip-flops are extracted from device level
simulations of the complete PFD circuit. The delay for
one buffer (AMP) is tAMP = 25 ps. The delays for the
differential output signal QP - QN of a D-FF are
tFFC = 30 ps (rising edge of CP - CN) and tFFR01 = 35 ps
(rising edge of RP - RN), respectively. After reset
(falling edge of RP - RN), the D-FF needs a setup time
of tFFR10 = 57 ps before the next rising edge of the clock
signal can be processed. The total delay for the AND,
MUX and AMP5 amounts to tRP = 70 ps. The duration
of the minimum UP/DN pulse is determined by the
propagation delays of the AND, MUX, AMP5, the reset
to output delay of the D-FF and one AMP delay. The
rise and fall times of the differential signals inside the
PFD are 50 ps. This implies that the minimum UP/DN
pulse must be longer than 100 ps so that the switches
inside the charge pump are fully turned on and off. A
high slew-rate of the UPn/DN signals would be
favourable for high-speed PFDs. However, a high edge
steepness increases the injected charge on the output
node of the charge pump. The reset pulse width is
tRP + tFFR01 + tAMP = 130 ps (shaded pulse in Fig. 7) and
therefore long enough to avoid a dead zone.
1
REFP
charge pump currents iCP_mean versus the PFD phase
error with clock frequencies of 375 MHz, 625 MHz and
1.6 GHz respectively. Fig. 9 reveals that the linear range
of the transfer function decreases to -π…π for the
highest operating frequency possible, which has been
shown by the work of Soyuer and Meyer (Fig. 7 in [1]).
The PFD/CP gain is KP = 195μA/2π and the transfer
characteristic has no dead zone or systematic offset.
1V
REFP-REFN
DIVP-DIVN
0V
-1 V
1V
UPP-UPN
DNP-DNN
0V
-1 V
1V
qrp-qdn
qdp-qdn
rep-ren
0V
0
-1 V
1.5 ns
qrp
2.5 ns
time [s]
3 ns
Fig. 8. Simulated timing diagram at fREF = fDIV = 1.6 GHz,
REFP and DIVP are 180° out of phase.
tFFC + tAMP
q3p(UPP)
DIVP
150
qdp
tFFC + tAMP
2 ns
tFFR01 + tAMP
100
i
CP_mean
[A]
q4p(DNP)
tRP
tRP tFFR10
50
rep
Fig. 7. Timing diagram to determine the reset pulse width
and the maximum operating frequency when REFP and
DIVP are 180° out of phase.
III. RESULTS
The limiting case for the maximum operating
frequency of this edge-triggered PFD occurs when
REFP and DIVP are 180° out of phase. The timing
diagram for this situation is depicted in Fig. 7. The
minimum half period THP,MIN of REFP and DIVP is
determined by taking all delays and setup times into
account and results in tFFC + tAMP + tRP + tFFR01
+ tAMP + tRP + tFFR10 = 312 ps. Hence, 1.6 GHz is the
upper limit and has been verified by simulations of the
whole circuit. The simulated timing diagram in Fig. 8
indicates that the PFD operates correctly at 1.5 GHz.
The linear range of the PFD/CP transfer characteristic,
which is at low frequencies -2π…2π, is reduced due to
the reset delay (130 ps) of the PFD. The simulated
transfer characteristic of this PFD together with the
implemented charge pump is depicted in Fig. 9. The
dashes, solid and dashed-dotted lines are the mean
0
50
-100
-150
-400°
Phase error [°]
-200°
0°
f=375MHz
f=625MHz
f=1.6GHz
200°
400°
Fig. 9. Simulated PFD/CP transfer function.
The operating range of the PFD has been verified
by measurements of two multiply-by-16 PLLs operating
in the ranges of 6 to 11 GHz and 8 to 12.1 GHz,
respectively. Fig. 10 depicts the measured spectrum at
6 GHz with a reference frequency fref = 375 MHz. The
reference spurs at an offset frequency ±375 MHz are
approximately -40 dB below the carrier and are
dominated by the charge pump non-idealities such as
finite output impedance and non-equal up and down
currents. The 12.1 GHz output clock and the 757 MHz
reference clock are shown in Fig. 11.
consumption of the PFD are 30 x 30 μm2 and 1.62 mW
(VDD = 1V), respectively.
TABLE I
COMPARISION WITH STATE-OF-THE-ART CML PFDS
fref
200 MHz
>40 MHz
>20 MHz
1.6 GHz
VDD
3.3 V
1.2 V
1.0 V
1.0 V
Power
6.5 mW
0.5 mW
3.7 mW
1.6 mW
CMOS Tech.
0.35 μm
0.13 μm
0.13 μm
90 nm
Year
[3], 2004
[4], 2006
[5], 2008
This
TABLE I shows a comparison with previously
published CML PFDs. All of them are tailored for lowpower and low-noise PLLs. Among them, the presented
PFD covers the largest operating range.
Fig. 10. Output signal of the PLL with the PFD: Measured
spectrum at 6 GHz with reference spurs at 6±0.375 GHz.
Output clock
IV. CONCLUSION
A fully differential CML PFD with a power-on
circuit to guarantee a correct start-up for charge-pump
PLL has been presented. The proposed PFD has zero
systematic timing misalignment between UPn
(UPN - UPP) and DN (DNP - DNN) and therefore no
deterministic contribution to the reference spurs and to
the static phase error. Moreover, the in-band phase
noise due to PFD/CP noise is reduced owing to the
short concurrent UP/DN pulses.
ACKNOWLEDGEMENTS
Reference clock
1.32ns
Fig. 11. Output signal of the PLL with the PFD: Reference
clock (757 MHz) and multiplied-by-16 output clock
(12.1 GHz).
The authors thank D. Barras, F. Ellinger,
C. Menolfi, M. Kossel, L. Rodoni, M. Schmatz,
T. Toifl, and J. Weiss for fruitful discussions, U. Egger
and M. Lanz for designing and manufacturing the test
substrate and the IBM foundry team for manufacturing
the CMOS chips. This work was supported by the Swiss
Federal Office for Professional Education and
Technology, contract/grant number KTI 7995.1.
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Fig. 12. Jitter histogram of the synthesized 10-GHz clock.
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jitter component proofing that the PFD is dead zone
free. Implemented in 90-nm CMOS, the area and power
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