TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
D
12-Bit Voltage Output DAC
D
Single Supply 2.7-V to 5.5-V Operation
D
Separate Analog and Digital Supplies
D ±
0.4 LSB Differential Nonlinearity (DNL),
±
1.5 LSB Integral Nonlinearity (INL)
D
Programmable Settling Time vs Power
Consumption:
1
µ s/4.2 mW in Fast Mode,
3.5
µ s/1.2 mW in Slow Mode
D
8-Bit
µ
Controller Compatible Interface (8+4
Bit)
D
Power-Down Mode (50 nW)
D
Rail-to-Rail Output Buffer
D
Synchronous or Asynchronous Update
D
Monotonic Over Temperature
The TLV5613 is a 12-bit voltage output digital-to-analog converter (DAC) with a 8-bit microcontroller compatible parallel interface. The
8 LSBs, the 4 MSBs and 3 control bits are written using three different addresses. Developed for a wide range of supply voltages, the TLV5613 can be operated from 2.7 V to 5.5 V.
D
Digital Servo Control Loops
D
Battery Powered Test Instruments
D
Digital Offset and Gain Adjustment
D
Industrial Process Control
D
Speech Synthesis
D
Machine and Motion Control Devices
D
Mass Storage Devices
A1
A0
SPD
DV
DD
D2
D3
D4
D5
D6
D7
DW OR PW PACKAGE
(TOP VIEW)
7
8
9
10
4
5
6
1
2
3
14
13
12
11
17
16
15
20
19
18
D1
D0
CS
WE
LDAC
PWD
GND
OUT
REF
AV
DD
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class A
(slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by the control bits within the 16-bit data word.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20 pin SOIC in standard commercial and industrial temperature ranges.
TA
0
°
C to 70
°
C
– 40
°
C to 85
°
C
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(DW)
TLV5613CDW
TLV5613IDW
TSSOP
(PW)
TLV5613CPW
TLV5613IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright

2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
REF
SPD
PWD
A(0–1)
CS
WE
2
Power-On
Reset
Interface
Control
3
3-Bit
Control
Latch
4
4-Bit
DAC MSW
Holding
Latch
4
8
8-Bit
DAC LSW
Holding
Latch
8
Powerdown and Speed
Control
2
12
12-Bit
DAC
Latch
12 x2
8
D(0–7)
LDAC
PWD
REF
SPD
GND
WE
NAME
TERMINAL
AVDD
A0
A1
CS
DVDD
D0 (LSB) – D7 (MSB)
LDAC
OUT
NO.
11
8
7
18
10
1–6, 19, 20
16
13
15
12
9
14
17 I
I
I
I
I
I
I
Analog positive power supply
Address input
Address input
Chip select. Digital input active low, used to enable/disable inputs
I
I
Digital positive power supply
Data input
Load DAC. Digital input active low, used to load DAC output
O DAC analog voltage output
Power down. Digital input active low
Analog reference voltage input
Speed select. Digital input
Ground
Write enable. Digital input active low, used to latch data
OUT
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
†
Supply voltage (DV
DD
, AV
DD
to GND)
Reference input voltage range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage difference, AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
– 2.8 V to 2.8 V
– 0.3 V to AV
DD
7 V
+ 0.3 V
Digital input voltage range to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
TLV5613I
– 0.3 V to DV
DD
+ 0.3 V
: TLV5613C 0
°
C to 70
°
C
– 40
°
C to 85
°
C
Storage temperature range, T stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65
°
C to 150
°
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Load resistance, RL
Load capacitance, CL
5-V Supply
3-V Supply
Supply voltage difference,
∆ VDD = AVDD – DVDD
Power on reset, POR
DVDD = 2.7 V to 5.5 V
DVDD = 2.7 V to 5.5 V
5-V Supply (see Note 1)
3-V Supply (see Note 1)
4.5
2.7
–2.8
5
3
0
5.5
3.3
2.8
0.55
2
0
2
0.8
GND 2.048
AVDD – 1.5
GND 1.024
AVDD – 1.5
2
100
70 TLV5613C
TLV5613I – 40
NOTE 1: Due to the x2 output buffer, a reference input voltage
≥
(VDD – 0.4)/2 causes clipping of the transfer function.
85
UNIT k
Ω pF
°
C
°
C
V
V
V
V
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
power supply
PARAMETER TEST CONDITIONS
Fast
MIN TYP MAX UNIT
1.6
3 mA
No load,
Slow
Fast
0.5
1.4
1.3
2.7
mA mA
DAC latch = 0x800
Power down supply current See Figure 14
Slow 0.4
0.01
1.1
10 mA
µ
A
Zero scale, See Note 2
PSRR Power supply rejection ratio
Full scale, See Note 3
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax]
3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax] static DAC specifications
–65
–65
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution
Integral nonlinearity (INL), end point adjusted
Differential nonlinearity (DNL)
EZS Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
Vref(REFIN) = 2.048 V, 1.024 V
Vref(REFIN) = 2.048 V, 1.024 V,
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 4
See Note 5
12
±
1.5
±
0.4
±
3
±
4
±
1
±
20 bits
LSB
LSB
Vref(REFIN) = 2.048 V, 1.024 V, See Note 6
Vref(REFIN) = 2.048 V, 1.024 V, See Note 7 3 mV ppm/
°
C
EG Gain error Vref(REFIN) = 2.048 V, 1.024 V, See Note 8
±
0.25
±
0.5
% of FS voltage ppm/
°
C Gain error temperature coefficient Vref(REFIN) = 2.048 V, 1.024 V, See Note 9 1
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref
×
8. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 k
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref
×
106/(Tmax – Tmin).
Ω excluding the effects of the zero-error.
106/(Tmax – Tmin).
output specifications
VO
PARAMETER
Output voltage
Output load regulation accuracy
RL = 10 k
Ω
TEST CONDITIONS
VO(OUT) = 4.096 V, RL = 2 k Ω
,
MIN TYP
0
0.1
MAX UNIT
AVDD–0.4
V
0.29
% of FS voltage
IOSC(source) Output short circuit source current VO(OUT) = 0 V input all 1s
Ω input all 1s
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
–100
–25
–10
–10
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
reference input (REFIN)
PARAMETER
Vref Input voltage reference
Ri Input resistance
Ci Input capacitance
See Note 10
TEST CONDITIONS
Fast mode
Slow mode
Reference feed through
REF = 1 Vpp at 1 kHz + 1.024 V dc,
See Note 10
NOTES: 10. Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
IIH
IIL
Ci
PARAMETER
High-level digital input current
Low-level digital input current
Input capacitance
VI = DVDD
VI = 0 V
TEST CONDITIONS
MIN TYP
0
10
5
1.6
1
MAX
AVDD– 1.5
–60
UNIT
V
M
Ω pF
MHz
MHz dB
MIN TYP MAX UNIT
–1
1
µ
A
µ
A
8 pF
analog output dynamic performance
S/N
PARAMETER
Glitch energy
Signal-to-noise
TEST CONDITIONS
L
Ω
, ,
CL = 100 pF,
See Note 11
RL = 10 k Ω
,
CL = 100 pF,
RL = 10 k Ω
,
CL = 100 pF,
See Note 12
See Note 13
Code-to-code transition
Fast
Slow
Fast
Slow
Fast
Slow
MIN TYP MAX UNIT
1 3
µ s
65
3.5
0.5
1
8
1.5
1
78
7
1.5
2
µ
V/ s
µ s nV–s
S/(N+D) Signal-to-noise + distortion
THD Total harmonic distortion
RL = 10 k, CL = 100 pF
58 69
–68 –60
Spurious free dynamic range 60 72
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change of 0x020 to 0x3FF or 0x3FF to 0x020.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full scale.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
digital inputs tsu(D) tsu(CS-WE) tsu(A) th(D) tsu(WE-LD) tw(WE) tw(LD)
Setup time, data ready before positive WE edge
Setup time, CS low before positive WE edge
Setup time, address bits A0, A1
Hold time, data held after positive WE edge
Setup time, positive WE edge before LDAC low
Pulse duration, WE high
Pulse duration, LDAC low
MIN NOM MAX UNIT
9 ns
13 ns
17
0 ns ns
0
25
25 ns ns
µ s
D(0–7) X
Data X
A(0–1)
CS
X tsu(CS-WE)
Address tsu(D) tsu(A) th(D) tw(WE)
X
WE tsu(WE-LD) tw(LD)
LDAC
Figure 1. Timing Diagram
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

D(0–7) X
A(0–1) X
CS
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
MSW X LSW X
0 X 1 X
WE
LDAC
D(0–7) X
Figure 2. Example of a Complete Write Cycle Using LDAC to Update the DAC
MSW X LSW X Control
A(0–1) X 0 X 1 X 3
CS
WE
LDAC
Figure 3. Example of a Complete Write Cycle Using the Control Word to Update the DAC
X
X
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
7

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
MAXIMUM OUTPUT VOLTAGE vs
LOAD
4.5
AVDD = 5 V, Vref = 2 V,
Input Code = 4095
4
MAXIMUM OUTPUT VOLTAGE vs
LOAD
3
AVDD = 3 V, Vref = 1.2 V,
Input Code = 4095
2.5
3.5
2
3
1.5
2.5
1
2
1.5
100 K 10 K 1 K
RL – Output Load –
Ω
100
Figure 4
TOTAL HARMONIC DISTORTION vs
LOAD
0
AVDD = 5 V, Vref = 2 V,
Tone @ 1 kHz
–20
10
0.5
100 K 10 K 1 K
RL – Output Load –
Ω
100
Figure 5
TOTAL HARMONIC DISTORTION vs
LOAD
0
AVDD = 3 V, Vref = 1.2 V,
Tone @ 1 kHz
–20
10
–40 –40
–60
–80
–100
100 K 10 K 1 K
RL – Output Load – Ω
100
Figure 6
10
–60
–80
–100
100 K 10 K 1 K
RL – Output Load –
Ω
100
Figure 7
10
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
–20
–30
–40
–50
TOTAL HARMONIC DISTORTION vs
FREQUENCY
0
AVDD = 5 V
–10
–60
–70
–80
0 5 30 35 10 15 20 f – Frequency – kHz
25
Figure 8
30
20
10
0
0
80
70
60
50
40
SIGNAL-TO-NOISE + DISTORTION vs
FREQUENCY
AVDD = 5 V
5 30 35 10 15 20 f – Frequency – kHz
25
Figure 10
TOTAL HARMONIC DISTORTION vs
FREQUENCY
0
AVDD = 3 V
–10
–20
–30
–40
–50
–60
–70
0
70
60
50
40
30
20
10
0
0
5 10 15 20 f – Frequency – kHz
25
Figure 9
30 35
SIGNAL-TO-NOISE + DISTORTION vs
FREQUENCY
AVDD = 3 V
5 10 15 20 f – Frequency – kHz
25
Figure 11
30 35
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
9

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
0
–0.2
–0.4
–0.6
–0.8
–1
0
1
0.8
0.6
0.4
0.2
500 1000 1500 2000
Code
2500
Figure 12. Differential Nonlinearity
3000
4
2
1.5
1
0.5
0
–0.5
–1
–1.5
–2
–4
0 500
3500
1000 1500 2000
Code
2500
Figure 13. Integral Nonlinearity
3000 3500
4000
4000
10
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
POWER DOWN SUPPLY CURRENT vs
TIME
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0 100 200 300 t – Time – ms
400
Figure 14
500 600
The TLV5613 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, speed and power down control logic, a resistor string and a rail-to-rail output buffer. The output voltage
(full scale determined by reference) is given by:
2 REF
CODE
0x1000
[V]
Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero).
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0.
LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. Two more asynchronous inputs, SPD and PWD control the settling times and the power down mode:
SPD:
PWD:
Speed control
Power control
1
→
fast mode 0
→
slow mode
1
→
normal operation 0
→
power down
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
11

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the control register. The following tables list the possible combination of the control signals and control bits.
PIN
SPD
0
0
1
1
BIT
SPD
0
1
0
1
Slow
Fast
Fast
Fast
PIN
PWD
0
0
1
1
BIT
PWD
0
1
0
1
Down
Down
Normal
Down
PIN
LDAC
0
0
1
1
BIT
RLDAC
0
1
0
1
Transparent
Transparent
Hold
Transparent
The TLV5613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0.
A1
0
0
1
1
A0
0
1
0
1
ADDRESS BITS
REGISTER
DAC LSW holding
DAC MSW holding
Reserved
Control
D7 D6
X
X: Don’t care
SPD: Speed control bit
PWD: Power control bit
RLDAC: Load DAC latch
X
D5
X
1
→
fast mode
1
→
power down
1
→
latch transparent
D4
X
D3
X
0
→
slow mode
0
→
normal operation
0
→
DAC latch controlled by LDAC pin
D2
RLDAC
D1
PWD
D0
SPD
12
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
To achieve the best performance, it is recommended to have separate power planes for GND, AV
DD
, and DV
DD
.
Figure 15 shows how to lay out the power planes for the TLV5613. As a general rule, digital and analog signals should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in parallel. The two positive power planes ( AV
DD
and DV
DD
) should be connected together at one point with a ferrite bead.
A 100-nF ceramic low series inductance capacitor between DV
DD
and GND and a 1-
µ
F tantalum capacitor between AV
DD
and GND as close as possible to the supply pins are recommended for optimal performance.
DVDD AVDD
Figure 15. TLV5613 Board Layout linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 16.
Output
Voltage
Negative
Offset
0 V
DAC Code
Figure 16. Effect of Negative Offset (Single Supply)
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
13

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage.

The circuit in Figure 17 shows how to interface the TLV5613 to an Intel MCS

251 microcontroller. The address bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which is connected to a latch at port 0.
An address decoder is required to generate the chip select signal for the TLV5613. In this example, a simple
3-to-8 decoder (74AC138) is used for the interface as shown in Figure 17. The DAC is memory mapped at addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations
(0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to generate the chip select signals for the entire system.
The data pins and the WE pin of the TLV5613 can be connected directly to the multiplexed address and data bus and the WR signal of the controller.
LDAC is held high so that the output voltage is updated using the RLDAC bit in the control register. Hardware power down mode is deactivated permanently by pulling PWD to DV
DD
.
8xC251
8 16
P2 A(15–8)
8 8
A(15–0)
AD(7–0)
P0 AD(7–0)
ALE
8
74AC373
D(7–0) Q(7–0)
LE OE
A2
A3
A4
DVDD
A
B
C
74AC138
Y(7–0)
A15
G1
G2A
G2B
8
CS(7–0)
2
TLV5613
D(7–0)
SPD
PWD
DVDD
CS OUT
WR WE
REF191
REF
Figure 17. TLV5613 Interfaced to an Intel MCS

251 Controller
LDAC
DVDD
RL
MCS is a registered trademark of Intel Corporation.
14
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
In the following example, the code generates a waveform at 500 KSPS with 500 samples stored in a table within the program memory space of the microcontroller. The period of the waveform is 1 ms.
The waveform data is located in the program memory space from address 01000h to address 013E8h
(2
×
500 = 1000 = 03E8h) beginning with the MSW of the first 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (the table is not shown in the code example).
The program consists of two parts:
D
A main routine, which is executed after reset and which initializes the timer and the interrupt system of the microcontroller.
D
An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC.
This example uses timer 0 in mode 3 (8-bit timer with auto reload). The clock of the timer is derived from the system clock and has a frequency of f osc
/12. The timer overrun frequency f tim
is given by the following equation: f tim
+ f
OSC
12(256–Reload) and the reload value is given by Reload
+
256– f
OSC
12 f tim
To get a timer overrun frequency of 500 kHz at a system clock of 24 MHz, the reload value is:
Reload + 256 –
24
12 0.5
+ 256–4 + 252 + 0FCh
With this value, the timer generates an interrupt every 2
µ s. The corresponding service routine T0_isr reads a sample from program memory and writes it to the DAC. First, it disables the update of the DAC output by clearing the RLDAC bit in the control register. Then it reads the MSW and the LSW from the waveform table and stores it in the MSW and LSW register of the TLV5613. The write cycle is completed by setting the RLDAC bit, which updates the DAC output. At the end of the interrupt service routine, the pointer to the waveform samples is increased and is checked to determine if it has reached the end of the table. If the pointer has reached the end of the table, the pointer is set to the start address of the table.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
15

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
;************************************************************************
;* Title : Waveform generation with TLV5613 *
;* Version: 1.0 *
;* MCU : Intel MCS

251, MCS

51 *
;*

1998 Texas Instruments Inc. *
;************************************************************************
TABLE_START EQU 01000h
TABLE_END_H EQU 013h
TABLE_END_L EQU 0E8h
RELOAD EQU 0FCh
ORG 00000h
JMP main
ORG 0000bh
JMP T0_isr
;start address of waveform data
;high byte – end address of waveform data
;low byte – end address of waveform data
;timer reload value
;entry point
;jump to main program
;timer0 (T0) interrupt vector
;jump to T0 interrupt service routine
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;main: setup timer and interrupt, loop forever
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– main: CLR A
MOV A, IE0
CLR TCON.4
MOV A, #002h
;disable all interrupts
;stop T0
MOV TMOD, A
MOV A, #RELOAD
MOV TH0, A
MOV TL0, A
MOV P2, #080h
;set T0 to auto reload mode
;set T0 reload value
;set T0 start value
;set A15 of address bus to select DAC
MOV DPTR, #TABLE_START ;set data pointer to start of wave form data
SETB IE0.1
SETB IE0.7
SETB TCON.4
idle_loop: SJMP idle_loop
;enable T0 interrupt
;enable interrupts
;start T0
;loop forever
16
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;T0_isr: will be called on every timer interrupt.
;fetches a new 16–bit value from program memory space and writes it
;to the DAC. If end of table is reached, sets DPTR to table start addr.
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
T0_isr: MOV R0, #003h
MOV A, #001h
;select DAC control register
;RLDAC=0, PWD=0, SPD=1
MOVX @R0, A
;no DAC update, normal operation, fast mode
;write Accu to DAC control register
MOV R0, #001h
CLR A
MOVC A, @A+DPTR
MOVX @R0, A
;select DAC MSW register
;get MSW from code memory
;write Accu to DAC MSW register
INC DPTR
MOV R0, #000h
CLR A
MOVC A, @A+DPTR
MOVX @R0, A
;set DPTR to LSW data
;select DAC LSW register
MOV R0, #003h
MOV A, #005h
MOVX @R0, A
;get LSW from code memory
;write Accu to DAC LSW register
;select DAC control register (to update DAC)
;DAC update, normal operation, fast mode
;write Accu to DAC control register
INC DPTR
MOV A, DPL
CJNE A, #TABLE_END_L, T0_isr_end
MOV A, DPH
;set DPTR to next MSW
;test end of table
CJNE A, #TABLE_END_H, T0_isr_end
MOV DPTR, #TABLE_START ;end of table reached –> start again
T0_isr_end: RETI
END
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
17

TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (E
ZS
)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (E
G
)
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (SINAD)
Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.
18
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265

www.ti.com
30-Jan-2016
Orderable Device
TLV5613CDW
TLV5613CDWG4
TLV5613CPW
TLV5613IDW
TLV5613IPW
TLV5613IPWG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
SOIC
SOIC
DW
DW
20
20
25
25
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TSSOP
SOIC
TSSOP
TSSOP
PW
DW
PW
PW
20
20
20
20
70
25
70
70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
MSL Peak Temp
(3)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Op Temp (°C)
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
Device Marking
(4/5)
TLV5613C
TLV5613C
TV5613
TLV5613I
TY5613
TY5613
TLV5613IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 TY5613
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples

www.ti.com
30-Jan-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2

www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
TLV5613IPWR
Package
Type
Package
Drawing
TSSOP PW
Pins
20
SPQ
2000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
16.4
A0
(mm)
6.95
B0
(mm)
7.1
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.6
8.0
16.0
Q1
Pack Materials-Page 1

www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
TLV5613IPWR
Package Type Package Drawing Pins
TSSOP PW 20
SPQ
2000
Length (mm) Width (mm) Height (mm)
367.0
367.0
38.0
Pack Materials-Page 2

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Audio
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
OMAP Applications Processors
Wireless Connectivity www.ti.com/audio amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
Applications
Automotive and Transportation
Communications and Telecom
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
Medical
Security
Space, Avionics and Defense
Video and Imaging www.ti-rfid.com
www.ti.com/omap TI E2E Community www.ti.com/wirelessconnectivity www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated