Implementation of Microprocessor-based Power
System Stabilizer
Zlatka Te ec
KON AR Electrical Engineering Institute, Zagreb, Croatia
Power electronics and control department
Abstract — In this work, I present our experience gained
through implementation of the IEEE PSS2B type of power
system stabilizers (PSSs). The work describes a particular
case of implementing this type of PSS in microprocessorbased digital voltage regulator with limited processing
resources. The following issues have been elaborated: (i)
choice of sampling time and its influence on the
performance of the PSS and on the processor utilization, (ii)
selection of the lead-lags time constants and their influences
on the noise amplification and (iii) scaling associated with
the integer arithmetic. The abovementioned problems have
been analyzed by simulations and experimentally on a
laboratory power plant, and appropriate solutions have
been proposed. Finally, the PSS2B has been implemented on
real power plants, and a simple method for field verification
of tuned PSS2B parameters is explained.
T
I.
INTRODUCTION
he power transfer capability in power systems is,
among others, limited due to low frequency
electromechanical oscillations within frequency range
between 0.1 and 4 Hz. These oscillations can arise due to
the lack of damping of the systems mechanical mode and
are additionally generated due to the usage of high gain
fast-acting automatic voltage regulators (AVRs). To
provide damping of the oscillations, supplementary
excitation control subsystems have been developed.
Among others, power system stabilizer (PSS) is probably
the most frequently used device for providing damping of
the above mentioned power oscillations. The PSS basic
function is applying an additional signal to excitation
system, creating electrical torque that damps out low
frequency power oscillations in the range of 0.1 to 4 Hz.
At the beginning of the nineties, manufacturers [1], [2],
[3] offered dual input digital PSS based on integral of
acceleration power [4]. It is known as PSS2B type of
power system stabilizer in IEEE Std 421.5 [5], [6]
(PSS2B in further text). This structure of PSS has
significantly improved performances of power systems
comparing to the previous PSS3A type [6].
Although the problems associated with the design of
power system stabilizers have been well documented in
the literature, problems related to their implementation in
the microprocessor systems were left undocumented in
large part. However, during commissioning of PSS, one
is facing problems related to interfacing, noise and
performance of PSS. Noise level and performance
problems are closely associated with capability of digital
system in use, i.e. compromises on the number of bits in
use, the use of integer or floating-point arithmetic and the
sampling time.
Our intention is not to deal with the well known PSS2B
structure, but present some of the problems that we have
experienced during implementation and commissioning
process. It is presented how the choice of sample time,
selection of lead-lags time constants and scaling
associated with integer arithmetic affects the performance
of the PSS, the quality of the PSS output signal and the
processor utilization.
The paper is structured as follows. The second section
presents structure of an existing digital voltage regulator
(DVR) within which PSS2B has been implemented on
real power plants. Basics of PSS2B structure and tuning
of the parameters are briefly presented in the third
section. For testing damping effects of PSS detailed
simulation model of the power plant is developed and
presented in section four. The fifth section presents the
problems occurred during implementation of PSS2B
structure in existing DVR and shows applied solutions.
The last section of the paper contains field results of
implemented PSS2B and the useful practical steps used
during its commissioning.
II.
DIGITAL VOLTAGE REGULATOR
The synchronous generators within the power plants are
equipped with digital voltage regulator based on the
KON AR microprocessor system for the control and
regulation of excitation systems [7], [8], Fig. 1. The
PSS2B described in this article is implemented in DVR
replacing the previously used PSS3A IEEE type of PSS.
The microprocessor system is built around a
programmable central processing unit (CPU) that enables
real-time execution of control and regulation tasks.
Modular hardware environment is based on MC68302
microprocessor [9] and industrial VMEbus system.
Software environment is comprised of software for
design and development of application program, system
software support and software utilities [8], [7]. Software
for design and development of application program is
based on graphical block-diagram oriented programming
package.
PC
generator
variable
measurem.
AD / DA
Converter
s
VME bus
Excitation
transformer
measuring
and
thyristor
control
measurement
regulation
gate
control
output
amplifier
control and
monitoring
protection
CPU
thyristor
converter
I/O bus
DVR
control system
GS
Station
battery
deexcitation
synchronous
generator
common AC
service
Control
panel
digital
I/O
communication
superimposed
control system
field flashing
Figure 1. Structure of the digital voltage regulator
The system software consists of real-time kernel and
system programs. Real-time kernel handles tasks
according to the pre-emptive fixed priority-based
scheduling policy [10], [11]. It can be shown [10], [11]
that with this policy scheduling a set of n periodic tasks is
feasible if:
1
PUB =
Ci
≤ n 2 n −1 ,
T
i
1≤ i ≤ n
(1)
where PUB = processor utilization bound, Ci =
computation time of task i, Ti = sample time of task i and
n = number of tasks. The current implementation
involves 9 tasks what gives PUB of 0.72. It can be shown
[10] that the scheduling of this particular task set is
feasible even when PUB approaches 0.88. However, due
to the fact that certain margin is needed for proper
operation during possible increase of voltage frequency
(generator run away), it has been decided to limit allowed
processor utilization bound to 72%.
III.
PSS2B STRUCTURE AND TUNING
The block diagram of the PSS2B power system
stabilizer is shown in Fig. 2. This two inputs PSS is
compound of two parts.
The first part is a filter that derives the integral of
accelerating power from speed and electrical power of the
synchronous generator according to electro-mechanical
equation:
1
1
(Pm − Pe ) =
Pacc = ,
(2)
2H
2H
where ω = rotor speed, H = generator inertia constant, Pe
= electro-mechanical (air-gap) power, Pacc = accelerating
power and Pm = mechanical power.
In practice, the speed signal is the result of calculation
of the frequency of a terminal voltage. The resulting
integral of accelerating power has the characteristics of
speed at lower frequencies and electrical power at higher
frequencies. In this way the integral of accelerating power
on interesting frequency range replaces speed signal and
avoids usage of toothed wheel/speed transducer.
According to most recent literature [5], [12], [13], [14]
parameters of the filter’s part do not change significantly
depending on system parameters and their values are
given in TABLE I. The ramp tracking filter time constants
T8 and T9 are selected to provide enough attenuation at
all shaft torsion frequencies and in the same time is able
to track a ramp in electrical power change. If the filter
time constants satisfy relation T8/T9=N (Fig 2.) stabilizer
exhibits zero steady-state error when the mechanical
power is ramped.
Figure 2. Block diagram of the PSS2B
Signal of the integral of accelerating power is input to
the second part of PSS2B consisting of three conventional
lead-lag filters specified with time constants T1 – T5 and
T10. Time constants of the lead-lag filters are selected to
compensate for phase lag of the system at frequencies of
interest. System phase lag is determined by measuring
frequency response of transfer function between terminal
voltage (Vt) and voltage reference (Vref) and depends on
synchronous machine parameters, variation in loading
condition and system parameters.
TABLE I.
PSS2B SETTINGS
Tw
T6
N
T8
T9
Max=Min
KS1
KS2
10s
0
4
0.5s
0.125s
0.1
T7
T1
T2
T3
T4
T10
2Hs
0.3s
0.12
0.25s
0.05s
0.05
1
0.99
T5
KS3
0.01
6
IV.
SIMULATION MODEL OF A POWER PLANT AND
PSSS2B
For the purpose of testing PSS2B performance and
determining initial PSS parameters before implementing it
within DVR on real power plant, a simulation model of
the power plant in MATLAB/Simulink simulation software
was developed. The power plant consists of a single
machine equipped with control systems and connected to
infinite bus. The simulation model uses continuous sample
time.
Simulation model of the real power plant is shown in
Fig.
3.
Synchronous
machine
block
from
MATLAB/Simulink SimPowerSystems [15] is used to
represent a simulation model of the synchronous
generator connected to an infinite bus (Three-phase
programmable voltage source block) through three-phase
transformer and transmission line.
Figure 3. Simulation model of the real power plant, parameters of synchronous generator listed in APPENDIX I
Vref
Vref
Pe, PSS
Pe, PSS
Pe, no Pss
Pe, no Pss
(p.u.)
(p.u.)
0.95
0.95
Magnitude (dB)
40
1
1
0.9
0.9
LEAD LAG 1 Bode Diagram
LEAD LAG 2
LEAD LAG 3
Pacc to PSSout
30
20
10
0
0.85
0.85
30
30
31
31
32
32
33
34
33 Time (s)34
Time (s)
35
35
36
36
37
37
Figure 4. Dynamic active power signal response of a step
Figure 4. Dynamic active power signal response of a step
change in voltage reference of 3 % , with and without PSS
change in voltage reference of 3 % , with and without PSS
DVR is modeled in accordance with the structure of
digital voltage regulator installed on the real plant [8].
PSS2B shown in Fig. 2 was integrated in simulation
model of DVR. Parameters of PSS are selected to
compensate for phase lag of the system in the frequency
range between 0.1 and 2 Hz. Selected parameter values
are given in TABLE I.
Fig. 4 shows dynamic active power signal response of a
3% step change in voltage reference with and without
PSS2B. It is obvious that the developed PSS produces
good damping of low frequency power oscillations (local
mode). It has to be emphasized that response in Fig. 4 is
obtained within the simulation that uses continuous
sample time. Discretization and process noise typical for
real DVR will affect real response of the PSS.
V.
PSS2B IMPLEMENTATION
The PSS2B is integrated into the existing application
program of DVR by adding additional program module.
The program module was developed within the task
executed with time period (sample time) of 3 ms.
Preliminary tests of the implemented PSS2B were
performed on physical model of a single machine infinitebus power system available in the laboratory (synchronous
generator parameters are given in APPENDIX II). The
physical model had similar DVR and application program
as the real power unit on which PSS had to be
implemented.
During preliminary tests several problems occurred.
The first one was high level of noise in PSS2B output
signal, and the second one was undesired high
contribution of the PSS2B program module to total
processor utilization (load). The problems and applied
solutions are presented hereafter.
A. Noise problem
In many cases, parameters of lead-lag filters are
optimally tuned in frequency range between 1 to 3 Hz, but
at the same time they can produce very high gain at range
of sampling frequency. During the tuning process of PSS,
one has to be aware that the amount of noise in PSS
output signal is among other things a function of the leadlag filter gain at frequency near the sample frequency, and
the value of input signal to the lead-lag, especially in the
case of digital systems with integer arithmetic.
Phase (deg)
-10
90
45
0
-2
10
-1
10
0
1
2
10
10
Frequency (Hz)
3
10
10
Figure 5. Bode response of lead-lag filters
Let us consider lead-lag filters with time constants listed
in TABLE I. Bode response of the lead-lags is given in
Fig. 5. The lead-lags are discretized with sample time of
3 ms.
Although Bode response shows that PSS optimally
compensate for system lag in the frequency range
between 0.1 to 3 Hz, it has too much lead on higher
frequency. From the magnitude response of third lead-lag
block we can see that this lead-lag filter in the range of
the sampling frequency contributes to the total PSS gain
with factor 15 and in the same time, at interesting
frequency range (0.1 – 4Hz) it produces no significant
phase lead. Fig. 6 shows voltage reference step change
response of internal PSS signals along the sequence of
considered three lead-lag filters without PSS in function.
Input to first lead lag is actual signal of integral of
accelerating power. It is obvious that third filter because
of high gain contribution at range of sampling frequency
adds significant level of noise to the PSS output signal.
Such PSS output signal causes noisy field voltage that
finally produces noisy reactive power, i.e. PSS is in this
case almost ineffective due to the need of using low
gains.
input,Pacc
after LEAD-LAG3
after LEAD-LAG2
after LEAD-LAG1
200
150
100
50
0
-50
-100
-150
-200
-250
1
1.5
2
Time (s) 2.5
3
0.3s+1
0.25s+1
0.05s+1
0.12s+1
0.05s+1
0.01s+1
LEAD-LAG 1
LEAD-LAG 2
LEAD-LAG 3
3.5
Figure 6. Dynamic response of internal PSS2B signals where
accelerating power is an input
B. Processor utilization problem
The implementation of PSS2B within the task with 3ms
sample time caused the increase of PUB beyond allowed
72%. The PSS2B contributed with almost 10%.
Therefore, we have to search for more appropriate
solution.
C. Applied solution
To solve the problem related to high processor
utilization almost all program elements within PSS
program module was moved to slower task executed with
time period of 12 ms. For this reason lead-lag filter time
constants T1-T5 and T10 had to be retuned with respect to
new sampling period.
To solve problem related to high level of noise in PSS
output signal we first additionally smoothed the signal of
integral of accelerating power by running input low pass
and washout filters within faster task with time period of 3
ms. Second, we retuned lead-lag filters with taking into
account influence of lead-lags parameters at range of
sampling frequency.
In systems with integer arithmetic and limited number
of bits reducing the entire available numerical range
further contributes to the noise level and affects
characteristic of filters in use. So, to additionally reduce
noise level in PSS output signal we scaled internal signals
of PSS in the way that signals that enter lead-lag filters
have as great value as possible. That means one has to
judge maximum and minimum value of each internal PSS
signal and than multiply the signal in accordance with
assumed limits. Output of third lead-lag, of course, has to
be divided with multiplying factors.
After described changes were applied, the noise level
was considerably reduced and processor utilization was
reduced to 70%. PSS2B in applied solution contributed to
the processor utilization with only 2.5%.
TABLE II.
FINAL PSS2B SETTINGS
Tw
T6
N
T8
T9
Max = -Min
KS1
KS2
T7
T1
T2
T3
T4
T10
T5
KS3
2H s
0.08 s
0.025 s
0.08 s
0.025 s
0.3
0.4
20
400
output PSS signal
Pacc
after LEAD-LAG1
300
200
100
0
-100
-200
COMMISSIONING OF PSS2B
During commissioning of PSS it is necessary to
(re)tune and verify PSS settings before putting PSS in
service. In practice, this includes measuring frequency
responses of the system (i.e. transfer function Vt/Vref),
tuning of lead-lag blocks parameters, PSS gain
verification and tests of generator responses on step in
reference voltage [12], [16], [17].
System frequency response is measured using
additionally developed utility within application program
of DVR. Simple utility adds a small sinus signal in
voltage reference and determines frequency response of
the system by recording phase shift between terminal and
reference voltage at frequency range 0.1 to 5 Hz.
10s
0
4
0.5 s
0.125 s
0.1
1
0.99
frequency after applying a small step in reference voltage
while generator is synchronized on grid and without PSS
in service. Namely, PSS2B parameters for certain
operating point are optimally tuned if: (i) the signal of
integral of accelerating power is in phase with speed
signal (i.e. terminal voltage frequency), and (ii) the phase
shift between output PSS signal and signal of integral of
accelerating is approximately the same as measured
system phase lag at frequency range of the local
oscillations. If recorded signals have mentioned phase
relation, PSS2B can be put in service without fear that it
will jeopardize the stability of power system.
Fig. 7 shows signals of electric power, integral of
accelerating power and PSS2B output in case when
PSS2B is out of service. Fig. 8 shows the same signals in
-300
-400
phase lead from lead-lags
4
5
6
7 Time (s)
8
9
10
4
x 10
Pe, no PSS
1.2
Pe (pu)
VI.
PSS lead-lags parameters ware initially set to values
obtained during simulation process (TABLE I) but
additionally tuned considering guidelines given in part V.
Also, difference between simulated and measured
frequency responses wares take into account. New PSS
settings are listed in TABLE II.
Quick on-field check of PSS parameters can be made
by recording output PSS2B signal, signal of integral of
accelerating power and signal of terminal voltage
PSS signals (pu)
So, if we want to obtain effective PSS, time constants
of the lead-lag filters have to be carefully selected in
respect to gain that the filter produce in the range of
sampling frequency, even if it means lower lead-lags
phase lead.
1.15
1.1
1.05
4
5
6
7 Time (s)
8
9
Figure 7. Dynamic response of active power, PSS2B internal and
output signal (3% step change in voltage reference without PSS)
10
100
50
PSS signals (pu)
REFERENCES
output PSS signal
Pacc
after LEAD-LAG1
[1]
[2]
0
-50
[3]
phase lead from lead-lags
-100
[4]
-150
4
x 10
5
6
4
7
Time (s)
8
9
[5]
[6]
Pe
1.2
Pe (pu)
10
1.15
[7]
1.1
1.05
4
5
6
7 Time (s)
8
9
10
[8]
Figure 8. Dynamic response of active power, and PSS2B internal
and output signal (3% step change in voltage reference with PSS)
situation when PSS2B, implemented with all specified
changes in section V, is in function. We can see that level
of noise in output PSS signal is very low and also that
implemented PSS provides good damping of local mode
electromechanical oscillations.
VII. CONCLUSION
Emphasis of the paper is on presenting practical
solutions of the problems that we have experienced during
implementation process of IEEE PSS2B type of PSS
within DVR with limited processing resources.
We showed that simulation made without taking into
account the target microprocessor system can lead to
poorly tuned PSS. Additionally, we presented necessary
steps to achieve the reduction of noise level of PSS output
signal with minimum demands on processing resources.
Furthermore, the simple method of on-site verification of
proposed PSS parameters is described.
The level of damping electromechanical oscillations
fully met the customer demands.
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A P PENDIX I.
GENERATOR P ARAMETERS (L ABORATORY P HYSICAL MODEL OFA
SINGLE GENERATOR INFINITE - BUS P OWER SYSTEM)
Parameter
Sn
Vn
fn
Cos
H
Xd
Xq
X’’d
X’’q
X’d
X’q
Rs
T d0’
T d’
T d’’
T q’’
Value
100 kVA
400 V
50 Hz
0.8
0.55
2,437
1,407
0,148
0,1256
0,2553
0,76
0.01575
1,21 s
1.125 s
0.0039 s
0.0101 s
APPENDIX II.
GENERATOR PARAMETERS (REAL POWER PLANT)
Parameter
Sn
Vn
fn
Cos
Xd
Xq
X’’d
X’’q
X’d
X’q
Td0’
Td’
Td’’
Tm
Value
20 MVA
10,5 kV
50 Hz
0.8 ind
1,38
0,96
0,18
0,28
4,28 s
0,87 s
0.12 s
5,25 s