Semiconductor Test : DFT : News : Trends : Technology : Commentary
THE FINAL
TEST REPORT
FTR
Vol. 20
No. 11
November 2009
Memory Chip Sales Climb –
But Memory Tester Sales Fall
T
he global DRAM market has finally begun to improve after declining annually since 2007. According to iSuppli, DRAM revenue decreased by 7.5 percent in 2007 and 25.1 percent in
2008. And, despite a strong recovery in the second and third quarters of this year, the weak conditions in the first quarter mean that
global DRAM revenue will to decline by 12.9 percent in 2009, according to its preliminary estimate. However, it says that the DRAM
industry will continue to rebound in 2010 and beyond. Global average selling prices (ASPs) for DRAM rose by 21 percent in the third
quarter following a 19 percent increase in the second quarter, according to iSuppli. The second quarter marked the first sequential
increase in DRAM pricing since the fourth quarter of 2006, the firm
said. It estimates that global DRAM revenue was up 35 percent sequentially in the third quarter, following a 34 percent sequential
increase in the second quarter. DRAM demand is expected to improve in 2010 with the general global economic recovery.
1.5
FTR INDEX
0.91
1.3
1.1
0.9
0.7
0.5
Oct
2006
Apr
Oct
2007
Apr
Oct
2008
Apr
Oct
2009
FTR'
FTR'ss index of ATE, chipmakers, and PC makers vs. the Dow-30, tumbled in October as investors again moved away from chip-related stocks.
iSuppli said, “Improved thirdquarter earnings
from Samsung,
Micron and the
Taiwanese
DRAM makers
point to increasing sales and further progress toward profitability,” said Mike
Howard, iSuppli
senior DRAM
analyst, in a report released last
month
The FLASH memory market is already changing from a situation that
favored buyers to favoring NAND
suppliers over the next few years, according to IC Insights’ in its mid-year
update to the McClean Report. Unit
shipments and bit volume demand is
set to increase but there has been a
declining investment in FLASH
memory manufacturing capacity for
a couple of years now. IC Insights
expects that in 2009 capital expenditures dedicated to FLASH memory
will fall to about $3 billion – just 25
percent of what it was in 2008.
Continued on page 2
iNSIDE iNFO
Page
Another TAP Co. is Gone!
3
Global Billings Report
4
Chip Equipment B/B
4
Who Will Be No.1 in 2018?
5
TAP Co. CQ3 Reports
6
Focus On — Electroglas
7
Products — LTX-C IMA
8
Optimal Enhanced S/W
9
ADV Sales up 46% QoQ
10
So Few Pins
11
Freddy’s Test Report
12
COPYRIGHT 2009 by IKONIX Corporation. All rights reserved. Photocopying copyrighted material is a federal offense.
No part of this report may be reproduced, in any form, without the written permission of the Publisher. Editor: J. Mulady
THE FINAL TEST REPORT is published by IKONIX Corporation, P.O. Box 1938, Lafayette, CA 94549 USA.
Tel:925-939-7909 Fax: 925-906-9427 e:mail: ftr@ikonix.com. Subscription rates and a sample issue are available upon request.
Vol. 20
No. 11
Continued from page 1
IC Insights says the volume of
NAND FLASH memory unit sales is
set to increase 2009 despite the economic challenges. Driven by demand
for handheld and wireless consumer,
computer and communications devices FLASH bit volumes increased
by triple-digit figures between 2005
and 2008. FLASH bit volume is forecast to increase by 83 percent in 2009
and is expected to double each year
through 2013. However, it also notes
that, “No significant expansion of
CAPEX spending plans has been announced for 2010. The resulting rise
in ASPs is set to last well into 2012
as it will take approximately a year
for any capacity expansion to be
brought on-line.”
However, there is no sign that the
brighter outlook for DRAM and
NAND makers has yet to do very
much for memory tester vendors.
Advantest – the dominant maker of
memory testers – commented in its
financial report for its second fiscal
quarter of 2009 (July-September)
that its memory tester sales grew 56
percent sequentially in the quarter, to
US$16.4 million, “mainly on increased shipments of DDR3 testers.”
However that was down 86.1 percent (in yen) from US$ 110.1 million
in the same quarter of 2008.
Verigy, in its report for its fiscal
quarter ended July 31, noted that
“Memory ATE purchases continued
to be slow for all competitors, and
we expect investments to continue
at low levels through the remainder
of calendar 2009." Its memory sales
remained flat at $4 million, even
though they benefitted from collections for systems that were shipped
last year but for which revenue was
not recognized due to collectability
issues.
Its CEO, Keith Barnes commented.
“I think that memory makers are trying to squeeze their testers as far as
they can go, but the DDR3 testing
that’s occurring is happening below
1 gigabit per second, and if you have
to test devices at a higher speed then
you need a different system."
THE FINAL TEST REPORT
Teradyne’s CEO, Mike Bradley,
noted in his analyst call for its third
quarter, ended Oct. 4, 2009, that
FLASH and high-speed memory test
demand remains much lower than in
prior periods. We’ve seen our first
new ordering for FLASH this quarter,
after virtually no business in the first
half of the year. So, we are now more
optimistic, albeit cautiously that
FLASH could start to participate more
in the recovery.” He did also note
that Teradyne has received multiple
orders for its UltraFLEX High Speed
Memory system. He added, “These
systems are now installed at our customers in both engineering and production and we expect full acceptance and revenue recognition for
them in this the fourth quarter.
He was asked by a Morgan Stanley
analyst – “Advantest reported yesterday and if I add their DDR3 test units
and add a couple of units from you,
we are still at a handful of DDR3
units. If I look at the rate of DDR3
migration from DDR2, clearly the
premium has gone away for DDR3.
That migration rate has been quite
steep. As per our estimate it’s probably around 30- 40 percent DDR3
right now. Has it surprised you on
how few DDR3 testers have been
bought given the rate of DDR3 migration we have seen?
Bradley replied, “If you’ve asked
that question six or nine months ago,
the answer would have been yes,
because most people were assuming
that tooling for DDR3 would have to
take place in ‘09 at a much heavier
rate than is happening. In the last
three to six months, everyone has
recognized that the reuse and the
stretching of the DDR2 testers into
the DDR3 low frequency range for
lower speed grades has been heavily
used by customers. So, there’s been
a heavy reduction in CAPEX as a result and that has been the major factor in depressing DDR3 buys.”
FormFactor CEO, Mario Ruscev, in
his analyst call for its third quarter,
was bit more optimistic saying, "We
have already seen the crossover from
DDR2 to DDR3 in our order activity.
Page 2
November
2009
We expect the broad industry
crossover point to be in the fourth
quarter. Therefore, we believe that
we are in the early stage of a recovery in memory spending with several
key growth drivers for DRAM such as
good transition to DDR3, transition to
5x nanometers followed by 4x nanometers process nodes and the transition from one gigabyte to two
gigabyte devices."
One result of chipmakers failure to
invest in additional, and better, test
capability was addressed by G. Dan
Hutcheson, president of VLSI Research. He said at the ISMI Symposium last month that the problem is
that ‘’no one wants to pay for test,
but the practice has backfired in the
consumer market." he said. This is
causing what he calls ‘techno-stress'’
or a condition that end-user products
are difficult to learn or will fail. “The
electronics industry is taking short
cuts, or, in some cases, curtailing
their in-house memory test procedures. This in turn has caused an inordinate amount of failures for
DRAMs, NAND and related devices in
the consumer market. The reason for
the memory failures is that OEMs,
test houses and chip makers have cut
back—or taken shortcuts—on the
memory test process in an effort to
cut costs," he said. He cited a recent
study by Google, indicating, there is
a huge problem for DRAM. ‘’Errors in
dynamic random access memory
(DRAM) are a common form of hardware failure in modern compute clusters. The study indicates that presently DRAM error rates are orders of
magnitude higher than previously
reported, with 25,000 to 70,000 errors per billion device hours per Mbit
and more than 8 percent of DIMMs
affected by errors per year.” He
added, “there is also an inordinate
amount of failures for NAND devices,
causing problems for USB FLASH
drives and other products.”
If he is correct, memory device
customers will demand better performance memory chips from chipmakers and eventually they will be forced
to buy more, and better testers.
Vol. 20
No. 11
THE FINAL TEST REPORT
November
2009
IN FTR'S OPINION
Yet another TAP equipment supplier bites the dust!
As is described on p. 7 of this issue,
one of this industry’s pioneers has
effectively moved to the dust bin of
history. It appears
that Electroglas
will no longer be a
supplier of wafer
probers, but will
become a company dedicated to
supporting its already installed base.
Its demise is also interesting in that
it was one of the seven companies
that successfully completed their first
public stock offerings (IPOs) during
1993 – by far the best year for ATErelated IPOs in history. The others
were Aseco, Aetrium, Credence,
Mosaid, Megatest and MCT – six of
which have now disappeared from
the scene – at least as ATE suppliers.
The other five are:
• Megatest went public at $12.00/
share and was acquired by Teradyne
in 1994 for $22.00/share.
• Handler maker Aseco that went
public at $10.25/share was acquired
by MCT for $4.00/share in January
2000.
• Mosaid went public at C$6.00
and still exists as a semiconductor IP
company, but sold all of its chip test
IP assets to Teradyne for $17 million
in February 2007.
• Credence, which went public at
$4.00/share (adjusted) was acquired
by LTX in August 2009 at $1.20/
share.
• MCT went public at $12.00/
share and filed for bankruptcy on
August 18, 2009.
So, as of this time, Aetrium is the
lone survivor of the “Class of ‘93". It
went public at $5.83/share continues
to operate – although in during a very
difficult period in 2004 it said it was
looking at strategic alternatives. Its
shares closed last month at $2.79 -but it has reported small losses for its
first three quarters of 2009.
The reasons for the demise of each
of these companies are somewhat
different, but all could arguably be
the result of very poor top management at some time previous to their
failure. Electroglas is a classic example of what has happened to a
number of ATE-related companies.
The company closed its initial public offering on July 1, 1993, at $16.00/
share and its stock climbed to over
$75 in August 1995 – before splitting
2:1 in December of that year. At the
time, Electroglas was the second largest prober supplier worldwide, just
behind TEL., and the largest supplier
in the non-Japanese market – selling
more than half of the probers used in
the U.S. and Europe.
Electroglas’ transition from General
Signal to an independent company
was led by Neil Bonke, who had been
president of General Signal’s Semiconductor Equipment Operations. In
general he did a good job as CEO,
with the exception of his final decision – to recruit Curt Wozniak from
Xilinx, where he had been its president/COO – as the company’s CEO.
Bonke remained as the company’s
chairman for a year, until Woziniak
replaced him in that position as well.
One of Wozniak’s first moves was
to purchase 21.5 acres of land in
South San Jose, CA to build what was
originally planned as a 400,000 sq. ft.
campus for the company. The company moved to the new facilities in
1999. Wozniak also set-out to expand
Electroglas’ product lines to include
data analysis and post-fab inspection
with a series of generally unsuccessful acquisition. In 2000, Electroglas
reported a profit of $40.5 million on
sales of $225 million – and its stock
hit a high of $44.00. But, in 2001 its
sales tumbled to $57.1 million – and
an operating loss of $80.5 million. Its
revenues have remained in that range
ever since. Wozniak laid-off most of
its manufacturing employees and
moved manufacturing of its wafer
probers to Singapore.
Page 3
However by March of 2003 its
stock had fallen to $0.83 and
Wozniak admitted that “the
company’s short term goal is survival.” In October 2003, he was
forced by the company’s board to
resign and was replaced as CEO/
Chairman by Keith Barnes – who had
been acquired by Credence Systems
along with his company IMS in May
2001. When Barnes took over the
company its shares had recovered to
about $3.40 as he began selling-off
the product lines which Wozniak
had acquired. He also sold its twentyacre, 263,000 square-foot facility to
Integrated Device Technology.
However, apparently realizing that
Electroglas was too far gone to turn
around, Barnes resigned to take the
Chairman/CEO/President positions
at Verigy. During Barnes last fiscal period at Electroglas – Jan. ‘05 through
May ’06 (17 months, as it had
changed its fiscal year during 2005)
the company had a loss of $34 million on revenues of $44.3 million.
On April 10, 2006 Thomas M. Rohrs, a member of the company’s
board replaced Barnes as CEO/Chairman. He moved to exchange $25.0
million of its Notes for 4,268,000
shares of its common stock and $7.5
million in cash, but adding $17.6 million to its operating loss. He also canceled the Sidewinder strip test handler, resulting in a $3.4 million writeoff adding to the company’s loss for
the quarter of $5.7 million.
In February of this year Rohrs was
replaced by its COO, Warren
Kocmond, Jr. In July 2009 Electroglas
filed for Chapter 7 bankruptcy.
This writer has often opined about
the difficulties of successfully running an ATE company – but too often
a combination of incompetence and
greed makes it impossible.!
But, that's just my opinion.
Vol. 20
No. 11
THE FINAL TEST REPORT
$400
0.5
SEM I TAP Bk /BILL
0.25
U.S.TAP VENDORS'
Book & Bill
$350
$300
0
November
2009
$32
$28
Monthly & 3 Mos. Av.
Worldwide Chip Sales (US$B)
$250
-0.25
3-M o. Avg.
-0.5
-0.75
Se p M ar Se p
2007
2008
$24
$200
Source: SEMI
$150
M ar
Se p
2009
$ M illion
$100
Bill
$50
$20
2 Yr. Av
$16
Book
$0
Sep Jan May Sep Jan May Sep
2007
2008
2009
SEMI Sept. 2009
Eqpt. B/B at 1.17
SEMI said that No. American chipequipment suppliers reported bookings of $732.8 million (3-month average) for September, up 19.3 percent
from August bookings of $614.5 million and up 12.8 percent YoY. Total
equipment billings were $624.6 million in September, up 7.7 percent
from August billings of $580.0 million, but down 32.6 percent YoY.
The resulting book-to-bill was 1.17
Total equipment bookings and billings
were $649.9 million and $927.3 million, respectively, in Sept. 2008.
Dan Tracy, director of industry research at SEMI, noted, "September
2009 is the first time since May 2007
that YoY bookings have risen and is
in-line with the gradually improving
CAPEX outlook for the remainder of
this year and into next year."
Front-end equipment bookings
were $566.6 million in Sept., up 17.8
percent MoM and up 10.6 percent
YoY. Billings were $497.0 million' up
7.0 percent MoM, but down 32.1
percent YoY. The Front-end equipment B/B for in September was 1.14.
Test, Assembly and Packaging
(TAP) equipment bookings were
$166.2 million in September, up 24.5
percent from the $133.5 million reported in August, and up 21.0 percent YoY. Billings were $127.6 million, up 10.3 percent MoM but down
34.5 percent YoY. The resulting September 2009 TAP equipment B/B
was 1.30.
TAP Eqpt Book-to-Bill
Aug’09 Sep’09
Book $133.5 $166.2
Sep’08
$137.4
Bill
B/B
$194.9
0.70
$115.7 $127.6
1.15
1.30
August 2009 WW Chip Sales
The SIA reported on Oct. 2 that three-month average worldwide chip sales
in August were $19.06 billion, an increase of 5.0 percent from July 2009
when sales were $18.15 billion, but down 16.1 percent from August 2008,
when sales were $22.71 billion. Sales were up sequentially in all geographic
regions. Year-to-date sales through August were down 21.3 percent to
$133.8 billion from $170.1 billion at this time last year. It noted that, “The
rate of decline has slowed from the first six months of ‘09 during which
sales fell by 25 percent YoY.”
MoM
US$Billion
YoY
Jul'09
Aug'09
%Change
Aug'08
%Change
Americas
3.08
3.25
5.4%
3.32
-2.3%
Europe
2.32
2.41
3.9%
3.45
-30.1%
Japan
3.22
3.36
4.4%
4.22
-20.4%
Asia-Pacific
9.54
10.04
5.3%
11.72
-14.3%
18.15
19.06
5.0%
22.71
-16.1%
Page 4
3 Mos. Av.
$12
Aug-07 Feb-08 Aug-08 Feb-09 Aug-09
August Actual Chip
Sales Dwn 12.9% YoY
August ‘actual’ chip sales were
$19.01 billion, down just 12.9 percent from the $21.83 billion in sales
recorded in August 2008, according
to the WSTS. This was a dramatic
turnaround from June when actual
global chip sales were $19.27 billion,
but that was 24.5 percent behind
where they were in June 2008.
One factor was the Americas region, where the chip market was
ahead of its value in August 2008,
becoming the first region to show
YoY growth since September of
2008. All other regional markets
were lower than they were in August
2008. Nevertheless, year-to-date chip
sales in the Americas Region were
still down 12.3 percent compared
with the same period in 2008.
Over all IC revenues were down
13.5 percent as ASPs fell 6.1 percent
and units shipped fell 7.8 percent
YoY. The most notable YoY gainer in
August was NAND FLASH that for
each month since December ‘08 has
shown sequential revenue growth. In
August NAND ASPs rose 11.6 percent, units shipped rose 27.9 percent
and revenue rose 42.8 percent YoY.
Aug ‘09 Regional Chip Sales
(US$Billion)
Market
Total
Monthly
Market
Sales
Americas $3.22
MoM
3.2%
YoY
7.6%
Europe
Japan
$2.37
$3.27
-0.4% -27.4%
-5.4% -21.2%
ROA
TOTAL
$10.15
$19.01
2.2% -11.2%
0.6% -12.9%
Vol. 20
No. 11
THE FINAL TEST REPORT
''A few of the other current top 10
companies should make the list, although some of them could be in
Close Change
52 Week
other forms due to mergers or other
Ticker
10/30 Month High
Low
combinations. A few new companies
AEHR
$1.32 0.6% $3.10 $0.75
should make the top 10 by 2018 from
ATRM
$2.79 26.2% $2.99 $0.80
the ranks of today's number 11 to 50."
ATE
$22.11 -19.3% $28.04 $10.64
"Could be a new company not
ranked
today be in the top 10 by
CSCD
$5.40 6.3% $5.59 $1.81
2018?
Not
likely; even though comCOHU $11.38 -16.1% $14.51 $7.00
panies in this industry can grow
ESIO
$10.94 -18.3% $14.60 $4.69
quickly, it would be extremely diffiFORM $16.99 -29.0% $26.08 $11.36
cult for a company in less than ten
INTT
$0.59 89.7% $0.88 $0.10
years to go from start-up to the $10
billion or so in revenue required to
KLIC
$4.65 -22.9% $6.68 $1.11
make the top 10 in 2018,'' he said.
LTXC
$1.34 -18.8% $1.90 $0.09
"It is also unlikely a broadbased
TER
$8.37 -9.5% $10.67 $2.80
chip maker will rule in 2018. The
VRGY
$9.84 -15.3% $15.11 $6.14
trend over the last 30 years is not the
country in which the companies are
Av g. Change
-2.2%
based. All of the top 10 companies
are multinational. The key trend is
the disappearance of the broadline
semiconductor company,'' he said.
''In 1978, all top 10 companies
In 1978, Texas Instruments and
were
basically broadline semiconMotorola were the top two chip comductor
suppliers. Of the 2008 top 10,
panies, followed by NEC and Hitachi.
only
Toshiba
and Infineon can be
By 1988, Japanese companies occuconsidered
broadline
suppliers. The
pied the top three spots. Ten years
trend
toward
focused
companies
will
later, Intel moved to No 1, Where it
continue,"
says
Jewell.
''The
high
remains today. (See chart below)
costs of fabs, R&D, and IC design
So, which companies will be in the
make it difficult for any company to
top 10 in 2018?
sustain a broad product line.
''I think it is safe to say Intel and
''The chip market is moving toward
Samsung will be there,'' said Bill
two
major product types: commodJewell, principal of Semiconductor
ity
and
application specific. ComIntelligence LLC (Dallas, TX), a semimodity
devices,
such as DRAM and
conductor research firm.
FLASH, are very dependent on economies of
Top 10 Semiconductor Suppliers
scale. Memory companies need huge capital
1978
1988
1998
2008
investment for their
1 TI
NEC
Intel
Intel
fabs, thus they generally
2 Motorola Toshiba
NEC
Samsung
do not have the re3 NEC
Hitachi
Motorola Toshiba
sources to develop
other product lines.
4 Hitachi
Motorola
Toshiba
TI
ASICS require design
5 Philips
TI
TI
STMicro
expertise for the end
6 Toshiba Intel
Samsung Renesas
application, requiring a
7 National Fujitsu
Hitachi
Sony
significant amount of
engineering resources.
8 Fairchild Mitsubishi Philips
Qualcom
Most of the ASIC com9 Intel
Matsushita STMicro Hynix
panies are small to me10 Siemens Philips
Infineon
Infineon
dium sized and use waSource: Gartner, Dataquest, iSuppli
fer foundries," he said.
ATE STOCKS
Who Will Be Number
One in 2018?
Page 5
November
2009
FINANCIAL REPORTS
Aetrium Inc.
Q3 Ending Sept. 30 : $000
2009
Sales
2008
$3,028
$5,509
Ops. Pft.
(549)
329
Net
(338)
252
Per shr.
(0.03)
0.02
Cascade Microtech Inc.
Q3 Ending Sept. 30 : $000
2009
Sales
$13,971
Ops. Pft.
Net
(1,717)
2008
$21,128
(1,569)
(1,419)
(1,291)
(0.11)
(0.10)
Per shr.
COHU Inc.
Q3 Ending Sept. 26 : $000
Sales
Ops. Pft.
2009
2008
$44,062
$48,016
(798)
Net
(71)
Per shr.
0.00
(1,275)
37
0.00
Electro Scientific Ind. Inc.
FQ2 Ending Sept. 26 : $000
Sales
2009
2008
$27,638
$49,610
Ops. Pft.
(9,370)
(2,294)
Net
(6,120)
(4,109)
Per shr.
(0.22)
(0.15)
FormFactor, Inc
FQ3 Ending Sept. 26 : $000
2009
Sales
$43,773 $
2008
$52,584
Ops. Pft. (23,803)
(28,894)
(23,901)
(14,041)
Net
Per shr.
(0.48)
(0.29)
Teradyne, Inc
FQ3 Ending Oct 4 : $000
2009
$262,162
Ops. Pft.
8,772
Net
6,675
Sales
Per shr.
Orders
0.04
$288,048
2008
$297,255
(17,276)
(22,689)
(0.13)
$198,072
Vol. 20
No. 11
CQ3'09 TAP Company
Financial Reports
TAP equipment makers generally
reported yet another quarterly loss
for the third calendar quarter of 2009.
(See p.4.) The major exception was
Teradyne which reported a profit of
$0.04/share. Cohu reported about
breakeven results for the quarter.
Teradyne
Reported revenues for its Q3’09,
ended Oct. 4, of $262 million, up
$92.6 million or 55 percent sequentially. Semi test contributed $70 million of this increase for a total of $173
million and system test contributed
$22 million of the growth for a total
of $89 million. Semi test service revenue was $40.6 million, up from
$37.6 million a quarter ago. In semi
test product turns business was 50
percent versus 62 percent a quarter
ago. Memory revenue, all FLASH
memory, was $7.9 million in the
quarter, up from $2 million a quarter
ago, also all FLASH memory.
Mike Bradley, Teradyne CEO commented, “In Q2 our overall semi test
bookings doubled from the level of
Q1. In this third quarter, we topped
the Q2 total with bookings of just
over $230 million or about a 70 percent growth sequentially. IDM and
fabless specifiers led the way with
bookings more than double the level
of Q2. OSAT business totaled about
$50 million, flat sequentially.
From a device segment perspective, we saw very strong growth in
power management applications,
while our wireless business was still
strong and was complemented by micro controller, storage and analog
segments, which posted healthy
growth in the second quarter.
We are pleased with the upsurge in
business from our Eagle Test product
line, which recorded its strongest
quarterly bookings in years. Demand
for automotive and image sensor systems remains below our historical
levels, so we’ve got some segments
that will add to revenues as the recovery broadens.
THE FINAL TEST REPORT
In addition, FLASH and high-speed
memory test demand remains low.
We saw the first new orders for
FLASH test this quarter, after virtually
no business in the first half of the
year. So, we are now more optimistic,
albeit cautiously, that FLASH could start
to participate in the recovery.
In the high-speed memory area,
we’ve met the important milestone
of receiving multiple orders for our
UltraFLEX memory tester. These systems are now installed at our customers in both engineering and production and we expect full acceptance
and revenue recognition for them in
this quarter." Bradley also noted that
when reporting its memory revenue
and orders. It will not breakout HSM
and FLASH separately.
Bradley added that, For the present
(December) quarter our semi test
revenue will again grow sequentially
while our systems test revenues decline due to the lumpy nature of
some of their businesses. In short, we
will have system test shipping at the
past Q2 level while semi test will
have doubled over that same time
frame. However the rapid ramp in
the semi test business has put strains
into our supply chain.
The front part of the ramp was
achieved through some inventory
drawdown throughout the supply
chain. With that inventory consumed, we are experiencing more
part shortages which is moving our
lead times out of a bit."
Teradyne said that at the end of the
third quarter its backlog stood at
$336 million, of which, 83 percent is
scheduled to ship within the next six
months."
Teradyne said it expects fourthquarter revenue of between $255
million and $270 million and GAAP
EPS range of $0.04 to $0.09. It added
that its guidance for the quarter includes the full reversal of a temporary
pay cuts and a more normal product
mix, but excludes the amortization of
acquired intangibles, the purchase
accounting inventory step-up charge,
and the non-cash imputed interest on
the convertible debt.
Page 6
November
2009
Cohu, Inc.
Reported sales were $44.1 million
for the third quarter ended September 26, 2009 compared to $38.4 million for the previous quarter and
$48.0 million for the same quarter in
2008. Its loss for the quarter was
$71,000 or $0.00/share compared to
net loss of $22.6 million or $0.97/
share in the previous quarter and net
income of $37,000, or $0.00/share in
the same quarter last year. (The loss
for the previous quarter includes a
non-cash charge of $19.6 million, or
$0.84/share, for a valuation allowance against deferred tax assets.)
Sales of semiconductor equipment
were 72 percent of third quarter
sales. Orders for chip equipment
grew 41 percent sequentially, to
$46.9 million On a unit basis highspeed handlers were 76 percent,
thermal handlers 22 percent, and
other products 2 percent. Semiconductor equipment related revenues
for Q3 were approximately 83 percent international and 17 percent
domestic. International sales were
90 percent Asia-Pacific, 7 percent the
Americas, and 3 percent other.
James Donahue, its president/CEO
commented that, “Customer forecasts strengthened as the quarter progressed and this trend has continued
into the fourth quarter. Orders for
handling equipment were broad
based across customers and products. Unit orders for pick & place
handlers were at the highest levels
since the first quarter of 2008 and
orders for gravity handlers were the
highest since the third quarter of last
year. We received initial orders from
a large US-based IDM for a new high
parallel fast index time MATRiX that
will be used by this customer for testing high performance analog ICs.
And we’re excited about a major
win for Rasco as a large IDM placed
a multi-system order for Rasco’s strip
handler, and then placed an even
larger follow-on order for more systems. We also booked several additional orders for Pyramid, our nextgeneration handler that incorporates
our proprietary thermal technology.”
Vol. 20
No. 11
THE FINAL TEST REPORT
November
2009
FormFactor, Inc.
Reported that revenues for its third
fiscal quarter 2009, ended on September 26, were $43.8 million, up 40.4
percent from $31.2 million in the
previous quarter, but down 16.7 percent from $52.6 million for the year
ago quarter. Its loss for the quarter
was $23.9 million or $0.48/share,
compared to a loss for the prior quarter of $65.8 million or $1.33/share
and a loss for the same quarter of
2008 of $14.0 million or $0.29/share.
Its non-GAAP loss for the quarter was
$20.9 million or $0.42/share.
Third-quarter revenue for DRAM
was $36.4 million, up 44 percent sequentially and flat YoY. The FLASH
business grew sequentially in the
third quarter due to a pickup in NOR
probe card demand to $2.1 million,
up 13 percent sequentially, but still
down 75 percent YoY. Revenue in
the SoC business was up 34 percent
sequentially to $4.6 million due to a
pickup in order activity in the microprocessor segment, and an increase
in activity coming from the automotive industry. However, YoY its SoC
business declined 39 percent.
It said it expects that its revenue for
the present (December) quarter will
be down approximately 10 percent
sequentially. Mainly because while it
shipped a number of probe cards for
advanced DRAM for engineering use,
it does not expect production buys
until the first half of 2010
Mario Ruscev, CEO of FormFactor
said, “During our third quarter, we
saw improvement across all business
segments. The improvement was
driven by market share gain in
DRAM, acceleration in DDR3, positive mobile DRAM activity and improved results in both FLASH and
SoC markets.
We also continued our efforts to
transition the back-end of our manufacturing to Asia. As we go through
our ramp up of our Asian manufacturing facilities and our new technology
over the coming quarters, We expect
costs related to the ramp up before
we more fully see the benefits of
lower manufacturing costs.
FOCUS ON
O
n October 20 a Delaware
bankruptcy court approved
the sale of Electroglas’ wafer
probe assets, including name and
trademarks, to private financial group
EG Systems – formed specifically for
this purpose – for an undisclosed
amount. The re-formed company will
be headed by a new president/CEO
Raj Kaul. He is also president/CEO of
Kensington Labs. Hayward, CA based
Kensington provides automation
products for semiconductor and
other industries.
Electroglas was established in 1960,
as Specialty Products, producing
glass capillaries for the just-emerging
semiconductor industry. After pioneering wafer prober technology during the 1960s, in 1973 Electroglas
introduced the revolutionary 1034X
wafer prober, which reduced operator involvement with a high-speed,
friction less, automatic positioning
system. It was based on a proprietary
linear motor technology, the “Sawyer
motor” which was originally developed in the ’70s to drive large scale
plotters. The company was acquired
by General Signal in 1980 as part of
that company’s ultimately unsuccessful effort to establish a position in the
semiconductor equipment market.
In June 1993, Electroglas was
“spun-off” from General Signal in
arguably the most successful IPO of
any of the seven ATE companies –
Aseco, Aetrium, Credence, Megatest.
Mosaid and MCT – which came public that year. It closed its IPO on July
1, 1993, at $16.00 and its stock
climbed to over $75 in August 1995
– before splitting 2:1 in December of
that year. At the time, Electroglas was
the second largest prober supplier
just behind TEL and the largest supplier in the non-Japanese market
Page 7
It had more than half of the prober
marked in the U.S. and Europe.
However, in recent years the company had lost most of that market
share and its revenues had stagnated
to just $46.4 million, $44.3 million,
$ 44.6 million and $45.4 million for
its fiscal years ended June 2006
through 2009 respectively. It reported losses of $13.9 million, $34.0
million, 18.8 million and 15.9 million
for those same years. On March 23 of
this year the Nasdaq market suspended trading of its stock on that
market.
In February 2009, Electroglas and
FormFactor had entered into an
agreement for Electroglas to supply
tools and technology to FormFactor.
After Electroglas filed bankruptcy,
the Delaware Bankruptcy Court approved FormFactor’s acquisition of
intellectual property rights and certain technology assets of Electroglas
related to precision motion control
automation for an unannounced
price. The purchase provides FormFactor with IP and physical assets the
company will use in its manufacturing operations.
EG Systems said that it plans to continue to support Electroglas’ new
wafer prober systems as well as its
installed base of 16,500+ systems
(300-mm, 200-mm, and legacy) with
spares, upgrades, service, and application support.
“Refocusing on the customers will
be the key to making Electroglas successful again, Kaul noted in a statement. “Foremost, we will be bringing
the company’s focus back to concentrate on our worldwide customer
base, which understandably was unclear during the turbulent financial
times for the company and the industry in general,” he added.
Vol. 20
No. 11
,Integrated
.6
LTX-C'''s
Multi-system
Architecture (IMA)
Test/Design
Pr
oducts
Products
L
TX-Credence, late last month,
unveiled what it calls “a new
system architecture” – its Integrated Multi-system Architecture
(IMA). The new offering supports the
assembly of ‘’optimized test system
arrays using compact, low-cost test
systems as building blocks to create
high-pin count ATE systems.
The IMA system allows customers
to create large ‘tester arrays’ and the
ability to break them apart into individual test cells as production needs
change.
LTX-Credence claims that ‘’Putting
together an array or breaking one
apart is done on the production floor
in less than half a day with no support
required from LTX-C.
The company also notes that, "Test
programs will not need to be
recompiled between configurations,
nor will edits need to be made when
moving from single testers to IMA
systems and vice versa.
THE FINAL TEST REPORT
The basic premise of the IMA architecture is:
1. Testers can be integrated together to obtain very high levels of
resources to address the increasing
number of sites customers would
like to test in parallel. For example,
it enables unprecedented number of
sites for strip test applications.
2. The customer’s existing fleet of
testers can become modules in an
IMA system. The initial version of
IMA will support testers of the same
type and configuration and will run
the same test program on each individual tester in the group (i.e. no resources are shared a cross the systems).
3. The IMA controller provides a
single point of control for the communications with the test cell and
interfacing to the operator.
From a software point of view, the
IMA system does not break the relationship between the test head and
the individual tester’s controller. The
IMA adds an additional controller on
top of the existing individual controllers. With this architecture the IMA
Array allows the distribution of multisite overhead over the individual
tester controllers.
While traditional test system architectures add test overhead leading to
diminishing efficiencies as test sites
increase, the IMA test arrays virtually
eliminate this effect by utilizing parallel processing in the multi-system
architecture. This results in near 100
percent multi-site efficiency as additional testers are added to an array,
the company claims.
The company’s first
offering using IMA is
with its Diamond platform. For example, an
IMA array using three
air-cooled Diamond
test systems provides
customers with up to
2,400 digital/analog
pins, in a footprint requiring half the floor
space compared to traditional high pin count
platforms.
Page 8
November
2009
The IMA software will allow up to
10 Diamonds to be integrated together. However, it notes that “while
a single loadboard is practical up to
the X3 limit, beyond that, interfacing
to a handler requires cable docking.”
However, LTX-C said that Integrated Multi-system Architecture is
not dependent on a specific tester, it
could be any tester in the LTX-C portfolio – and potentially with testers
from other vendors – according to a
company spokesman.
"LTX-Credence pioneered the concept of a single, scalable test platform, and now the future of our industry is in IMA compliant tester arrays,” said Bruce MacDonald, VP of
marketing at LTX-Credence.
Price and availability
availability:
The IMA system is priced “at less
than $100K and production shipments will commence in calendar Q1
of 2010, the company said.
Rudolph's Die Sort
Classification S/W
Rudolph Technologies announced
the release of its Discover Fast Review and Die Sort Classification Software for back-end manufacturing. It
is specifically designed to reduce the
time and cost of reviewing back-end
manufacturing defects detected by its
NSX Series automated macro defect
inspection system.
Discover automatically classifies
defects, either on-line or off-line,
eliminating the need to review multiple instances of similar defects. It
also distinguishes nuisance defects
that do not have an impact on yield
from those that should receive further off-line investigation, reducing
labor-intensive manual review.
"We have seen improvements in
review efficiency ranging from 18 to
40 percent, with commensurate reductions in time and cost of the review process," Rajiv Roy, Rudolph's
VP director of back-end marketing,
said.
Discover is now available on new
NSX Systems or as a retrofit for existing NSX installations.
Vol. 20
No. 11
,.6
Optimal Enhances its
Test Management S/W
OptimalTest, a supplier of enterprise-wide test management and optimization software for the semiconductor industry, will introduce new
capabilities and enhancements for its
Optimal Enterprise solution at the
International Test Conference (ITC)
in Austin TX on November 3-5. The
company said its Optimal Enterprise
solution "Provides additional automated expert processes and applications to establish test and test data as
value-added strategic management
tools."
OptimalTest introduced its Test
Management Solution in 2006 that
addresses many test management
and operational issues in a solution
that is agnostic to hardware, process,
product and business model. It provides semiconductor companies
with a range of capabilities, based on
Adaptive Test. Its latest capabilities
and enhancements, allow semiconductor partners - the fabless, IDMs,
foundries, and OSATs to work together to meet rapidly changing business needs. According to the company its enhanced solution now delivers highly reliable quality test data
for informed decision-making across
enterprise partners.
Debbora Ahlgren, OptimalTest’s VP
for sales & marketing, commented,
“We’re providing an alternative to
traditional CAPEX investment by allowing companies to do much more
than simply modify existing test strategies. It now brings the benefits of
highly automated statistical process
control that front-end semiconductor
processes have long employed to
back-end test.”
THE FINAL TEST REPORT
Building on its existing test management solution set, Version 3.6 introduces new capabilities focused on
the Optimal Enterprise
:Proxy Enabler and Expert Engine.
OptimalTest’s new software “proxy”
acts as a stand-in for test-cell station
controllers in situations where a
faster, more easily deployed and
lower cost capability is needed. It
enables a “lite” version of test floor
control, with no need to revise and
re-document how test operations are
run. In an accelerated “near-time”
dimension, the proxy enables an
early detection solution independent
to STDF, allowing transfer of efficient
data formats from tester to control
room. It delivers test results from
across distributed global operations
and value-chain partners in minutes
rather than days or hours. Because it
detects issues in test processes, products and operations, it helps ensure
access to high quality data quickly,
enhancing time-to-actionable data.
OT-Portal, an in-depth expert decision-support and visualization tool
that offers the flexibility to create and
store management reports at various
levels and for various user communities. It also supports off-line analysis
and simulation for adaptive test algorithms such as Test time Reduction
and Outlier Detection.
OT-Rules 2, is an enhancement to
OT-Rules, the company’s original algorithm library and engine. It includes a new “global” rules creation
enabler that allows easy proliferation
of algorithms across globally distributed operations or multiple enterprises. A streamlined “smart” rules
deployment engine allows flexible
creation of multiple hierarchical
rules in a rigid “tree” model. Hardcoded limits OT-Post
rules can be executed
before lot end. It also includes new rules fami- COMPANY
lies for Overall Equipment Efficiency, Opera- Cadence
tions, Yield recovery and Mentor
Yield Learning
Synopsys
These enhancements Av g. Change
are available now, it said.
Page 9
November
2009
Teradyne/Teseda to
Develop Scan Tool
Teradyne announced a development agreement with Teseda to produce Scan Workbench, a next-generation portable scan debug and yield
enhancement tool. It is based on industry-standard data protocols and
the existing Teseda Workbench and
Diagnostic Manager products. Scan
Workbench will allow test engineers
to better perform rapid silicon debug,
design validation, failure analysis and
yield monitoring resulting in decreased time-to-market and improved
profitability, according to the two
companies.
Scan Workbench provides a consistent debug and optimization environment based on IEEE 1450.0-1999
Standard Test Interface Language
(STIL) and the new STDF V4-2007
datalog standards. The software will
initially be deployed on the Teradyne
FLEX and J750 platforms which will
provide Scan Workbench with access to an installed base of over 5,000
testers. The new toolset is expected
to be shipping in the second half of
2010.
"We are pleased to be working with
Teradyne to help define, develop and
jointly market Teseda's new Scan
Workbench toolset," said Armagan
Akar, Teseda president/CEO. "This
new partnership allows us to work
with the industry leader in ATE to
offer our next-generation scan diagnostic tools to the largest potential
market – the FLEX family and J750
installed base. In this ultra-competitive market, we concur with
Teradyne's unique approach to support EDA- and ATE-agnostic tools in
the marketplace."
EDA STOCKS
Ticker
Close Change
10/30 Month
CDNS
$6.11
MENT
$7.30 -17.3%
SNPS
$22.02
-2.6%
3.7%
-5.4%
52 Week
High
Low
$8.18
$2.55
$9.73
$3.34
$23.58
$13.94
Vol. 20
No. 11
THE FINAL TEST REPORT
Advantest FQ2’09
Sales up 46.6% QoQ
Focus
on
ASIA
1.6
SEAJ Eqpt Book/Bill
1.4
3-M onth Average
1.2
1.0
0.8
0.6
0.4
0.2
Sep Mar
2007
Sep Mar
2008
Sep
2009
SEAJ Sept. B/B at 1.28
The SEAJ reported that Japan-based
chip equipment makers posted
¥61,567 million (US$672.942) in orders in September 2009 (3-month
average). The bookings figure is up
11.0 percent from its final August
2009 level of ¥55,457 million, but
down 22.2 percent from the Sept.
2008 bookings of ¥79,152 million.
The 3-month average of billings in
September 2009 was ¥48,219 million
(US$527.045), up 25.0 percent from
the August 2009 level of ¥38,569 million, but down 42.2 percent from the
September 2008 billings level of
¥83,408 million.
The SEAJ book-to-bill for September
was 1.28, down from 1.44 in August.
JAPANESE ATE STOCKS
Close
INDEX
NIKKEI 225
Ticker 10/30
N225
10,035
Change
Month
-1.0%
Adv antest
6857
2,060
-17.3%
JEM
6855
639
-3.9%
MJC
6871
1,472
-7.9%
TEL
8035
5,240
-8.6%
TSK
7729
1,158
-4.2%
Yokogaw a
6841
750
-5.7%
Av erage change in Oct.
Yen/US$
90.565
Advantest posted a fiscal secondquarter loss of ¥3.3 01 billion ($33.86
million) on revenues of ¥11.156 million (US$114.4 million) for the three
months ended Sept. 30, down 57
percent from ¥26.062 billion in the
same period last year. Advantest,
along with other chip equipment
makers have been faced by a 45 percent YoY drop in CAPEX by chipmakers to about US$24.3 billion.
The company’s operating loss widened to ¥3.446 billion (US$35.55
million) from ¥2.089 billion a year
earlier. Sales slumped 57 percent to
¥11.2 billion (US$114.4 million). Its
bookings for the quarter were ¥14.4
billion (US$147. 7 million), down
20.4 percent YoY but up from ¥11.6
billion in the previous quarter,
Memory tester sales fell to ¥1.6 billion (US16.4 million) from ¥11.5 billion in the same quarter last year. The
company commented that “orders
and sales of DDR3 DRAM test systems increased in anticipation of
growing demand for PCs that utilize
these high-speed memory devices.”
None-memory tester sales were ¥5.5
billion (US$56.4 million) up 84 percent sequentially as a result of increased shipments of T2000 modules
for MPU test, it said.
Handler and interface sales were
¥2.1 billion (US$21.5 million), down
59.6 percent YoY.
Orders for semiconductor and component testers sales fell 32.7 percent
YoY to ¥ 7.7 billion (US$79.0 million). Orders for handlers and interfaces rose 65.9 percent YoY to ¥ 4.7
billion (US$48.2 million).
-7.9%
0.9%
Q2'09 Sales by Region
¥ Billion
Japan
2.7
24.1%
America
Europe
1.4
0.4
12.5%
3.6%
November
2009
Advantest’s sales in Japan were just
24.1 percent of its total sales for the
quarter. Notably its largest sales geographically were in the Rest-of-Asia
(ROA), at ¥3.6 billion which would
indicate that its sales in China – although not specified by the company
– were quite substantial and China
may have been its largest regional
customer – exceeding even Japan.
Looking to the future, Advantest
said that although the global tester
market is forecast to shrink to US$1.4
billion in 2009 – even lower than initial estimates. But, it expects it will
begin to recover in 2010, rising to
US$2.3 billion and then more than
double 2009 sales at US$3.2 million
– slightly above the 2008 level.
Advantest also said that it is now
focusing on the non-memory tester
market, which it sees as both much
larger, and more stable than the
memory tester market. It said it is targeting a 30 percent share of the nonmemory market – while retaining a
70 percent share of the memory
tester market – but it did not specify
a time frame to meet those targets.
It also said it plans “near-future”
additions to its lineup of device interfaces and consumables, including
probe cards with new proprietary
technology. It will also expand its
lease and rental offerings, in addition
to direct sales.
Advantest said that its visibility extends no further than FQ3’09 and
thus it did not provide a full-year forecast. However, it said that if orders
in FQ4’09 hit ¥20 billion, it could be
profitable in the next fiscal year.
(Q3'09 Yen/Dollar used was 93.7)
Advantest Coporation
FQ2 Ending Sept. 30 :
US$Million except for per share.
So. Korea
Taiwan
2.0
1.1
17.9%
9.8%
ROA
Total
3.6
11.2
32.1%
100.0%
Page 10
¥
2009
Sales
$$114.437
2008
$249.455
Ops. Pft.
(35.554)
(19.995)
Net
(33.861)
(26.705)
Per shr.
Orders
(0.19)
(0.15)
$147.714
$173.246
Vol. 20
No. 11
Design & Test
Issues
So many
functions–so few
pins!
O
ne of the inevitable results of
increasing the density of transistors as chips move to ever
smaller manufacturing technologies,
is that the number of I/O pins on the
external interface remains the same
or is actually shrinking in some cases.
For engineers designing test programs for new devices, there is more
to test with fewer control and observation points to do it with.
Some of the reasons for the reduced number of digital test pins include:
• Packaging issues and the costs of
additional pins.
• Reduced ATE interface, either
for test pins or the functional I/O
pins, or both. This can be for actual
tester hardware limitations or in an
effort to use less expensive (and less
capable) testers.
• Multi-site testing, that is, testing
multiple devices in parallel.
• Wafer test and the goal to minimize the contact points per die.
• Growing analog content in SoC
chips..
• Use of more high-speed serial
pins to transfer parallel data over serial streams.
More and more IC design companies are dealing with one or more of
these reasons for fewer test pins and
need help to implement a good digital test within these limitations.
In a recent ‘white paper’ Bruce
Swanson a Technical Marketing Engineer in the Silicon Test division at
Mentor Graphics, outlined a couple
of approaches being used by design
and test engineers to deal with the
problem
The first is reduced pin-count test
(RCPT) and the second is low pincount test (LPCT).
THE FINAL TEST REPORT
The RPCT approach is a methodology that uses existing boundary scan
logic to reduce the number of functional pins that interface to the ATE
during scan test. Boundary scan refers to the IEEE 1149.1 standard that
adds some hardware on the device
around the boundary of the chip.
Each pin pad is connected to a special boundary scan cell, and they are
stitched together into a boundary
scan chain.
The logic is controlled by a state
machine, and the external interface
is called a test access port (TAP) with
either four or five pins total. The
1149.1 standard was originally created to test the circuit board interconnections between ICs, but since
then, additional test techniques have
taken advantage of this existing test
interface.
If special RPCT boundary scan cells
are used on the functional pins
where test values are normally supplied or captured during scan test,
the TAP interface and boundary scan
chain can be used to control and observe those values instead of hooking
up all those pins to the ATE. This
approach results in a large reduction
in the number of test pins needed
while keeping the test quality the
same. The technique works for both
stuck-at and at-speed transition scan
patterns.
The TAP interface can also be used
for controlling on-chip built-in selftest (BIST) logic. BIST logic is usually
added to designs to test the internal
memories and sometimes it is also
used for testing digital logic blocks or
modules – MBIST and LBIST respectively. The BIST controllers reside onchip and interface to the memories
or logic they are designed to test. The
BIST approach eliminates the storing
of test patterns on ATE because the
whole test is contained within the
device. The TAP controller can be
designed with some custom instructions and registers to control the BIST
tests and capture the test results. The
TAP interface can eliminate the need
separate external pin access to the
ATE system.
Page 11
November
2009
The most common manufacturing
test technique for digital logic is to
use scan patterns created by an automatic test pattern generation (ATPG)
tool. This technique replaces the
design’s flip-flops with scan cells and
stitches them into scan chains. The
scan chains connect directly to scan
channels on the ATE pin interface for
shifting in test patterns and shifting
out the captured test responses for
comparison with expected results.
LPCT refers to using the on-chip
test compression logic to reduce the
number of ATE pins needed to provide the test patterns. The on-chip
compression logic talks to the ATE
scan channels and to the internal
scan chains, but the relationship is
one-to-many instead of traditional
ATPG’s one-to-one form.
This does allow the tester interface
pin count to be very low, even down
to one scan channel per design, or
one per block if it is used in a modular fashion. However, while these solutions can reduce the number of
pins needed, they can increase test
time if they use techniques such as
serial to parallel converter to lower
the pin count requirements.
ATE/DFT MEETINGS
ITC 2009
3-5 November, 2009
Austin Convention Center.
Austin, TX
http://www.itctestweek.org/
SEMICON JAPAN 2009
2-4 December 2009
Makuhari Messe, Chiba, Japan
http:/www.semiconjapan.org
Vol. 20
No. 11
FREDD
Y’S TEST
REDDY
REPOR
EPORTT
INDUSTRY
Kim Jong-kap, CEO of Hynix forecasts a short DRAM supply situation
to continue for the whole of 2010.
“Even if Taiwanese and Japanese
players ramp up production, the possibility of oversupply is slim as worries over a double-dip in the global
economy are easing,” Kim said.
Semico Research is predicting 20
percent IC revenue growth next year,
with equipment suppliers looking at
“a couple of good years,” followed by
two years of stable growth. Another
downturn will follow in 2013, with
revenues declining in the face of continued good unit growth that year, it
said.
SEMI said at Semicon Taiwan that
the U.S. will spend more on new chip
equipment this year than any other
country, for the first time since 1994
– replacing Japan. New factory
spending plans by Intel and Globalfoundries put U.S. chip equipment
spending on track to reach $3.56 billion this year, it said.
THE FINAL TEST REPORT
November
2009
COMPANIES
PEOPLE
FormFactor unveiled its TouchMatrix
– a 300-mm full-wafer contact probe
card for NAND FLASH chips. It enables testing of FLASH devices down
to sub 32-nm process nodes, including those integrating three-bit and
four-bit memory cell architectures.
John Pollock has been named to
newly created position of president of Aetrium
Aetrium. He has been
with Aetrium for 14 years and
most recently was General Manager of its North Saint Paul, MN
facility.
Aehr Test Systems said that the Nasdaq Stock Market said it has regained
compliance with the $1.00 minimum
closing bid price requirement.
Brian Halla will step down as
CEO of National Semi as of November 3, but will remain as its
executive chairman through next
May. Donald Macleod
Macleod, currently
National’s president and COO,
will succeed Halla as CEO.
Plastronics Socket introduced a reusable, reconfigurable, and repairable socket for burn-in. Its president
David Pfaff claims, “Our new ES
socket series allows customers to
reuse, reconfigure, or refurbish their
sockets, saving both time and money.
ALLVIA, the first through-silicon via
(TSV) foundry, has purchased a
manufacturing facility in Hillsboro,
OR for production of their TSV technology products. It currently imanufactures in Sunnyvale, CA
STATS ChipPAC said its revenue for
Q3'09 rose 21.5% sequentially to
$389.8 million but down 17.5% YoY
Its net was $25.1 million or $0.01/
share. Its CAPEX for the quarter was
$40.9 million or 10.5% of revenue
compared to $97.3 million or 20.6%
of revenue in Q3 2008.
Thomas Seifert has been named
Sr. VP and CFO for AMD. He succeeds Robert Rivet
Rivet, who was
promoted to chief operations and
administrative officer. Seifert
joins AMD from Qimonda AG,
where he most recently was
COO/CFO.
Dr. Shang-Yi Chiang has rejoined
TSMC as its Sr. VP of R&D. He left
TSMC temporarily three years ago
to take care of his ailing father,
who recently passed away.”
Dr. Aart de Geus, CEO and cofounder of Synopsys, has been
named this year’s recipient of the
GSA's Exemplary Leadership
Award.
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