Notes on High Level Implementation of DICD Coursework
Ben Cope
Department of EEE
Imperial College London
btc00@imperial.ac.uk
1 Introduction
Figure 1 shows a typical cell (solid line) and two neighbouring cells (dashed lines). Two dimensions of height and
pitch are shown. Notice that the cell above the ‘typical cell’
has the same pitch and the one to its right the same height.
The other dimension in each case can be arbitrary.
This is an ideal situation, in some cases it may not be
possible or appropriate to have matching cell heights. In
this case cells should be packed as tightly as possible, maintaining equal pitch in each column of cells. The reason for
a constant pitch will become apparent later.
Finally notice how the cells are overlapped in the horizontal direction. The reasoning for this is the sharing of
power rails (VDD and GND) between the cells.
This document gives a brief overview of some of the high
level design factors which should be considered when designing an integrated circuit. This is aimed at the Digital
Integrated Circuit Design fourth year/MSc coursework.
It is important to consider these issues early in the design
process. This saves time in later stages of design (when
connecting high level blocks) and leads to a neater solution.
Examples are used to demonstrate a neat well laid out
circuit, however, you are encouraged to think carefully
about layout and also to develop your own ideas.
Section 2 will show logic cell dimensions. The routing
of power rails is discussed in section 3. Section 4 suggests
how data should be routed in the chip. The clock routing is
presented in section 5. Section 6 concludes.
VDD
C
E
L
L
CELL
CELL CELL
Height
C
E
L
L
C
E
L
L
C
E
L
L
... ... ... ...
GND
Pitch
Figure 2. Routing of Power Rails
Figure 1. Dimensions of a Chip
3 Routing of Power Rails
2 Cell Dimensions
There are many methods for distribution of power within
an integrated circuit. A neat and simplistic solution is
shown in figure 2. As always you are encouraged to investigate further methods.
One of the first considerations is the size of each logic
cell. A logic cell could be, for example, a ‘comparator’, an
‘and gate’ or a ‘register’.
1
In the example, it is noticed that the power rails are running parallel to each other, in this case vertically. The distance between the rails is constant for all cells, however as
discussed above this can be vary for different columns.
VDD and GND alternate and are shared between cells.
This is why the cells in figure 1 overlap. During all stages
of design one must be careful to consider the alternating and
sharing of power rails between cells.
One may wish to route VDD and GND along both top
and bottom of the design to improve performance - think
about why this is so?
M1
VDD
CLK
DATA
M2
M1
VDD
GND
Figure 4. Clock routing
DATA
DATA
... ... ... ...
The example shows a layout similar to that shown in the
previous sections. Notice that the height of the cells is now
varied, however the pitch of the cells remains constant.
A clock signal is required for the middle column of cells,
which may be registers. This is routed down through the
chip, and is therefore in the same metal layer as the power
rails. Notice that through routing mainly down in metal 1
and across in metal 2, power, clock and dataflow can be
routed easily.
M2
GND
Figure 3. Dataflow and metal layers
6 Conclusion
4 Dataflow
A brief summary of some of the points to consider in a
layout of an integrated circuit have been presented. This
has been done through one example of how a chip may be
laid out. Many permutations of this are possible and valid
solutions and students are encouraged to investigate other,
perhaps more optimal solutions.
Perhaps the most important and difficult to design aspect
of the implementation is the dataflow. One must carefully
consider which signals should be routed together. For example, if signals a1 and a2 were frequently operated on as
a pair then it would be sensible to route them together.
An example showing how dataflow through cells may be
implemented is given in figure 3. Notice that the dataflow
is at 90 degrees to the power rails. The dataflow is routed
in a separate metal layer to the power rails, in our example
power and dataflow are in metals 1 and 2 respectively. This
makes the routing less complicated as the design scales in
size.
The arrows on the diagram are to represent the direction of dataflow, data will not pass through all blocks unmodified. Finally the labels for the cells are removed from
this example.
In conclusion the main factors to consider are:
• Maintain constant cell pitch
• Route across the chip in one metal layer and down in
another.
• Share power rails between adjacent cells
• Think very carefully about dataflow
Good Luck with the coursework!
5 Clock Routing
An IC design typically involves the use of a clock or
other synchronisation signals. In this section, how best to
route such a signal is shown, see figure 4.
2