LM3248
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SNVSA01A – JULY 2013 – REVISED SEPTEMBER 2013
LM3248 2.7 MHz, 2.5A Adjustable Boost-Buck DC/DC Converter
with Boost and Active Current Assist and Analog Bypass (ACB)
Check for Samples: LM3248
FEATURES
DESCRIPTION
•
The LM3248 is a PWM/PFM Boost-Buck DC/DC
converter that provides efficient utilization of battery
power over a wide voltage range. The device
architecture is suitable for advanced RF front-end
systems that demand dynamic voltage and current to
support converged power amplifier architectures
operating in 2G/3G/4G and 3GPP/LTE modes. For
example, the LM3248 is designed to produce higher
output voltages while maintaining PFM mode as
required by some new reduced-power CMOS PAs.
The extremely fast Boost-Buck function reduces RF
PA overhead power dissipation, extending battery talk
time. The device will operate at input voltage VIN
range of 2.7V to 5.5V and an adjustable output
voltage VOUT range of 0.4V to 4.0V at a maximum
current load of 2.5A.
1
2
•
•
•
•
•
•
•
•
Output Voltage VOUT Adjustable from 0.4V to
4.0V (typ.)
Input Voltage Range VIN from 2.7V to 5.5V
Boost-Buck and Buck (Boost-Bypass)
Operating Modes with Seamless Transition
2.5A Load Current Capability
High Conversion Efficiency (> 90% typ.)
High-Efficiency PFM/PWM Modes with
Seamless Transition
Very Fast Transient Response: 10 µs
ACB Reduces Inductor Size Requirements
Dither to aid RX Band Noise Compliance
APPLICATIONS
•
•
•
The LM3248 is available in a 30-bump, lead-free thin
DSBGA package.
Multi-mode 2G/3G/4G and 3GPP/LTE Smartphones and Tablets
Hand-Held Radios
RF Mobile Devices
Typical Application Diagram
1 F Low ESL
1.0 H
10 F
VBATT
2.7V to 5.5V
SW_
BOOST
OUT_
BOOST
PVIN_
BUCK
VDD1_
BUCK
VDD2_
BUCK
FB_
BUCK
PVIN_
BOOST
ACB
10 F
SW_
BUCK
ACB
BYPASS
BUCK
BOOST
VDD_
BOOST
1.5 H
VCC_PA
10 F
CONTROL
BGND
DGND
1 nF
VCON
PGND
SGND_
BOOST
BOOST_
SGND_
ENABLE GATE MODE BUCK
FB
1.8V Logic
Apps
Processor
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LM3248
SNVSA01A – JULY 2013 – REVISED SEPTEMBER 2013
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DESCRIPTION (CONTINUED)
The LM3248 utilizes step-up (Boost) and variable output step-down (Buck) DC/DC converters. Combining a
cascaded Boost and Buck converter in a single package is ideal for powering the latest multimode/multi-standard
RF power amplifiers. The Boost converter provides the RF power subsystem the capability to operate at lower
battery voltages as well as to maintain increased PA linearity and transmit power margins over a wider battery
voltage supply range.
The Buck has a unique Active Current assist and analog Bypass (ACB) feature to minimize inductor size without
any loss of output regulation for the entire battery voltage and RF output power range, until dropout. ACB
provides a parallel current path, when needed, to limit the maximum inductor current while still driving a 2.5A
load. The LM3248 may also be configured as a Buck-only converter with a boost bypass feature to enable
highest efficiency operation with minimal dropout voltage when the Boost is not needed.
The LM3248 automatically and seamlessly transitions between Pulse Width Modulation (PWM) and Pulse
Frequency Modulation (PFM) modes for high-efficiency operation with both full and light load conditions.
Connection Diagram
A
VDD_
BOOST
PVIN_
BOOST
PVIN_
BOOST
OUT_
BOOST
OUT_
BOOST
B
BOOST_
GATE
SGND_
BOOST
SW_
BOOST
SW_
BOOST
SW_
BOOST
C
MODE
VDD1_
BUCK
SGND_
BUCK
PGND
PGND
D
ENABLE
VCON
NC
SW_
BUCK
SW_
BUCK
E
ATB1
FB_
BUCK
DGND
PVIN_
BUCK
PVIN_
BUCK
F
ATB2
VDD2_
BUCK
BGND
ACB
ACB
2
3
4
5
1
Figure 1. 30-Bump Thin DSBGA Package (0.4 mm pitch)
(Top View, bumps down)
2
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Pin Descriptions
Pin #
Name
I/O
A1
VDD_BOOST
-
Power supply voltage input for Boost Analog blocks. Connected to VBATT supply.
PVIN_BOOST
-
Power supply voltage input for Boost Bypass FET.
OUT_BOOST
O
Boost converter output. When Boost and Buck are active, OUT_BOOST must be externally
connected to PVIN_BUCK. A 10 µF capacitor must be placed between this node and GND.
Internally connected to BUCK voltage input and feedback to inverting input of Boost error
amplifier.
B1
BOOST_GATE
I
Digital input. A Low-to-High transition wakes up the boost converter and positions it to a high
level in preparation for a possible VCON change.
B2
SGND_BOOST
-
Analog Ground for the Boost Analog blocks.
SW_BOOST
I/O
C1
MODE
I
C2
VDD1_BUCK
C3
SGND_BUCK
-
Analog Ground for the Buck Analog Blocks.
PGND
-
Power Ground for output FETs.
D1
ENABLE
I
Input. Chip enable. Setting ENABLE = High biases up the Buck and initiates VCON regulation
by the Buck.
D2
VCON
I
Analog voltage control input which controls Buck output voltage.
D3
NC
-
No connect; leave this pin floating.
SW_BUCK
O
Buck converter switch node for external filter inductor connection.
E1
ATB1
-
Test pin. Connect to SGND or System Ground.
E2
FB_BUCK
-
Feedback input to inverting input of error amplifier. Connect Buck output voltage directly to this
node.
E3
DGND
-
Ground for Boost, Buck, and RFFE digital blocks.
PVIN_BUCK
-
Power supply input for Buck PFET and ACB FET. A 10 µF capacitor must be placed between
this node and PGND. Must be externally connected to OUT_BOOST.
F1
ATB2
-
Test pin. Connect to SGND or System Ground.
F2
VDD2_BUCK
-
Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCK
when used with Boost.
F3
BGND
-
Ground for ACB bypass circuit.
ACB
-
Active Current assist and Bypass output. Connected to the Buck converter output filter
capacitor.
A2
A3
A4
A5
Description
B3
B4
Boost converter switch node. When Boost and Buck are active, SW_BOOST is typically
connected to VBATT supply through external power inductor.
B5
C4
C5
D4
D5
E4
E5
F4
F5
Digital input. Low = 3G/4G (PWM/PFM) operation; High = 2G (PWM only) operation.
Power supply voltage input for Buck Analog PWM blocks. Internally connected to PVIN_BUCK
when used with Boost. If Buck-only mode is used then must be directly connected to VBATT
supply.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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LM3248
SNVSA01A – JULY 2013 – REVISED SEPTEMBER 2013
ABSOLUTE MAXIMUM RATINGS
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(1) (2)
VBATT pins to GND (PVIN_BOOST, VDD_BOOST, SW_BOOST, PVIN_BUCK,
VDD1_BUCK, VDD2_BUCK, SW_BUCK, ACB, SGND_BOOST, SGND_BUCK, BGND,
PGND)
BOOST_GATE, MODE, ENABLE, OUT_BOOST, FB_BUCK, VCON
Junction Temperature (TJ-MAX)
+150°C
−65°C to +150°C
Storage Temperature Range
Continuous Power Dissipation
(3)
Internally Limited
Maximum Lead Temperature
(Soldering, 10 sec)
+260°C
ESD Rating (4)
Human Body Model
(1)
(2)
(3)
(4)
−0.2V to +6.0V
(GND −0.2V to PVIN_BOOST +0.2V)
2 kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.5V.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ < 130°C (typ.).
The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7)
RECOMMENDED OPERATING CONDITIONS
(1)
Input Voltage Range VBATT
2.7V to 5.5V
Boost Output, Buck Input Range
2.7V to 5.5V
Recommended Load Current
0A to 2.5A
Junction Temperature (TJ) Range
−30°C to +125°C
Ambient Temperature (TA) Range
−30°C to +90°C
(1)
All voltages are with respect to the potential at the GND pins. The LM3248 is designed for mobile phone applications where turn-on after
power-up is controlled by the system controller, and where requirements for a small package size overrule increased die size for internal
Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds
2.5V.
THERMAL PROPERTIES
Junction-to-Ambient Thermal Resistance (θJA)
30-bump DSBGA
(1)
4
(1)
38°C/W
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7 and is board dependent.
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ELECTRICAL CHARACTERISTICS (BOOST)
Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating ambient temperature range
(−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 3.0V and Buck in IDLE state.
Symbol
Parameter
Condition
ILIM-BOOST,PFET
PFET valley current limit
Open Loop (1), VCON = 1.44V,
VOUT_BUCK = 3.6V
FOSC-Boost
Boost internal oscillator
frequency
2G/3G/4G mode, PWM mode, average
(1)
Min
Typ
Max
Units
4.1
A
2.7
MHz
Current limit is built-in, fixed, and not adjustable.
SYSTEM CHARACTERISTICS (BOOST)
The following spec table entries are specified by design and verifications providing the component values in the Typical
Application Diagram are used: L = 1.0 µH (TOKO 1276AS-H-1R0N); CIN = 10 µF (Murata GRM155R61A106M); and COUT =
1µF (Taiyo Yuden LWK107B7105KA-T) + 10 µF (Murata GRM155R61A106M). These parameters are not verified by
production testing. (1) (The Boost stage output voltage equation is given in (2).) Min and Max values are specified over the
ambient temperature range TA = −30°C ≤ TA ≤ 90°C. Unless otherwise noted, typical values are specified at VBATT = 3.0V,
Buck in IDLE, and TA = 25°C.
Symbol
Parameter
Condition
Min
Boost Bypass mode
VOUT_BOOST
VGOTOBOOST
Boost output voltage
Boost turn-on threshold voltage
Typ
2.7
VCON = 1.60V , MODE = LOW (3G/4G),
Load = 100 mA (2)
4.45
VCON = 1.46V , MODE = HIGH (2G),
Load = 100 mA (2)
4.65
MODE = LOW; BOOST_GATE = HIGH;
SW_BOOST = switching;
VCON = (VBATT - VGOTOBOOST)/2.5
MODE = HIGH; BOOST_GATE = HIGH;
SW_BOOST = switching;
VCON = (VBATT - VGOTOBOOST)/2.5
0
Minimum time to assert
BOOST_GATE signal before
next TTI slot boundary
BOOST_GATE signal must remain HIGH
during this interval
45
IIN-BOOST-MAX
Max input current averaged
across a 2G burst (RMS)
VBATT = 2.7V, VOUT_BOOST = 4.2V
PA active during GSM burst (2)
3.5
Duty CycleMAX-
PWM maximum duty cycle
IOUT-BOOST < 1 mA
70
Line transient response
VBATT = 3.4V to 3.7V, ΔV = ±300 mV,
TR =TF = 10 µs, VOUT_BUCK = 3.7V,
RLOAD_BUCK = 4Ω, MODE = 3G/4G (2)
150
VLOAD-TR
Load transient response
VBATT = 2.7V, IOUT_BUCK = 10 mA to 850
mA,
IOUT, TR = TF = 10 µs
VOUT_BUCK = 3.7V, MODE = 3G/4G (2)
600
VBOOST-RIPPLE
Boost ripple voltage at worstcase conditions
VBATT = 2.7V, VBOOST = 3.4V, IOUT = 2A,
2G mode (Sufficient overhead between
VBOOST and VOUT )
100
TBOOST_GATE_Active
BOOST
VLINE-TR
(1)
(2)
V
37
125
Initially in Idle State: Boost in 0% duty cycle
(bypass)
BOOST_GATE
Units
5.5
mV
–50
Minimum time from ENABLE =
HIGH (and remains steady) to
BOOST_GATE rising edge
TENABLE to
Max
25
µs
A
%
mVpp
mVpp
Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing,
but do represent the most likely norm.
VOUT-BOOST = VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)].
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LM3248
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ELECTRICAL CHARACTERISTICS (BUCK)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 3.8V.
Symbol
Parameter
Condition
(1) (2)
VFB,MIN
Feedback voltage at low setting
VCON = 0.16V, MODE = HIGH
VFB,MAX
Feedback voltage at high setting
VCON = 1.6V, MODE = HIGH, VBATT = 5.0V
ILIM,PFET,Steady
Positive steady state peak current
limit
VOUT = 1.5V
State
(1) (2)
(3)
IP-ACB,2G
Positive Active Current assist
Bypass current limit
ILIM,NFET
NFET Switch negative peak
current limit
VCON = 1.0V
ISHDN
Shutdown supply current IBATT
ENABLE = LOW
IQ_PFM
IQ_PWM
FOSC
(1)
(2)
(3)
(4)
6
DC bias current from VBATT
Internal oscillator frequency
VCON = 0.6V, VACB = 2.8V
(3)
Min
Typ
Max
0.35
0.4
0.45
3.88
4.0
4.12
1.34
1.45
1.65
1.40
1.70
2.0
−1.50
−1.31
(3)
(4)
0.02
4
ENABLE = HIGH
260
350
ENABLE = HIGH
1010
1100
2.7
2.916
2G/3G/4G mode, PWM mode, average
2.484
Units
V
A
µA
MHz
The parameters in the electrical characteristics table are tested under open loop conditions at VBATT = 3.8V unless otherwise specified.
For performance over the input voltage range and closed-loop results, refer to the datasheet curves.
VOUT-BOOST = VCON * 2.5 + [≈ 450 mV(3G/4G) or ≈ 950 mV(2G)].
Current limit is built-in, fixed, and not adjustable.
Shutdown current includes leakage current of PFET.
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SYSTEM CHARACTERISTICS (BUCK)
The following spec table entries are specified by design and verification providing the component values in the Typical
Application Diagram are used: L = 1.5 µH (TOKO 1285AS-H-1R5N); CIN = 10 µF (Murata GRM155R61A106A); and COUT =
10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These
parameters are not verified by production testing. (1) Min and Max values are specified over the ambient temperature
range TA = −30°C ≤ TA ≤ +90°C. Typical values are specified at VBATT = 3.8V and TA = 25°C unless otherwise stated.
Symbol
TWarm-Up
TRESPONSE
ILIM,PFET,Transient
IOUT_MAX, PWM
Parameter
Condition
Time Delay required after
BOOST_GATE = HIGH (before
VCON can change)
ENABLE = High
Time for VOUT to rise from 0V to
3.4V (90% or 3.06V)
VBATT = 3.8V, RLOAD = 68Ω,
VCON = 0V to 1.36V
Time for VOUT to fall from 3.4V to
0V (10% or 0.34V)
VBATT = 3.8V, RLOAD = 68Ω,
VCON = 1.36V to 0V
Time for VOUT to rise from 0.8V to
3.3V (90% or 3.05V)
VBATT = 3.8V, RLOAD = 20Ω,
VCON = 0.32V to 1.32V
Time for VOUT to fall from 3.3V to
0.8V (10% or 1.05V)
VBATT = 3.8V, RLOAD = 20Ω,
VCON = 1.32 to 0.32V
Time for VOUT to rise from 1.4V to
3.4V (90% or 3.2V)
VBATT = 3.8V, RLOAD = 6.8Ω,
VCON = 0.56V to 1.36V
Time for VOUT to fall from 3.4V to
1.4V (10% or 1.6V)
VBATT = 3.8V, RLOAD = 6.8Ω,
VCON = 1.36V to 0.56V
Time for VOUT to rise from 1.8V to
2.8V (93% or 2.73V)
VBATT = 3.8V, RLOAD = 2.2Ω,
VCON = 0.72V to 1.12V
MODE = 2G
Time for VOUT to fall from 2.8V to
1.8V (7% or 1.87V)
VBATT = 3.8V, RLOAD = 2.2Ω
VCON = 1.12V to 0.72V
MODE = 2G
Positive transient peak current
limit
VOUT = 1.5V
Maximum load current in PWM
mode
Max
µs
10
µs
10
15
1.9
VBATT ≥ 2.88V, VCON = 1.48V (VOUT =
3.7V), PWM mode, switcher plus ACB
current
2.0
VBATT ≥ 3.0V, VCON = 1.48V (VOUT = 3.7V),
PWM mode, switcher plus ACB current
2.3
VCON = 1.2V (VOUT = 3.0V), PWM mode,
switcher plus ACB current
2.5
35
VBATT/VOUT = 3.6/3.3V, 4.2/4.0V,
BOOST_GATE = LOW
IOUT_MAX, PFM
Maximum load current to enter
into PFM mode
D < 0.85 or SW_BOOST = switching
IOUT,PU
Maximum output transient pullup
current limit
Units
15
(2)
Load current to enter into PFM
mode at high duty cycle (D > 0.85
AND Boost in Bypass)
2.1
A
A
mA
85
mA
3.0
PWM mode
(2)
, switcher plus ACB current
IOUT,PD_PWM
PWM maximum output transient
pulldown current limit
VOUT_ACC
VOUT accuracy over output voltage
VOUT = 0.6V to 3.6V
range
(2)
(3)
Typ
30
IOUT_PFM
(1)
Min
A
−3.0
(3)
−3
+3
%
Parameter is specified by design, characterization testing, or statistical analysis. Typical numbers are not verified by production testing,
but do represent the most likely norm.
Current limit is built-in, fixed, and not adjustable.
Accuracy limits are ±3% or ±50 mV, whichever is larger.
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SYSTEM CHARACTERISTICS (BUCK) (continued)
The following spec table entries are specified by design and verification providing the component values in the Typical
Application Diagram are used: L = 1.5 µH (TOKO 1285AS-H-1R5N); CIN = 10 µF (Murata GRM155R61A106A); and COUT =
10 µF + 4.7 µF (Murata GRM155R61A106A, GRM155R61A475MEAA) + 4 x 1.0 µF (Murata GRM033R60J105M). These
parameters are not verified by production testing.(1) Min and Max values are specified over the ambient temperature
range TA = −30°C ≤ TA ≤ +90°C. Typical values are specified at VBATT = 3.8V and TA = 25°C unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Ripple voltage at no pulse
skipping condition
VOUT = 0.4V to 3.6V, ROUT = 2.2Ω,
2G mode (4)
4
10
Ripple voltage at pulse skipping
condition
VBATT = 4.2V to dropout,
VOUT = 3.6V, ROUT = 2.2Ω,
2G mode (4)
14
20
PFM ripple voltage
VOUT = 1.0V,
IOUT = 40 mA
9
15
VLINE-TR
Line transient response
VBATT = 3.6V to 4.2V,
TR = TF = 10 µs,
VOUT = 1.0V, IOUT = 600 mA
70
VLOAD-TR
Load transient response
VOUT = 3.0V,
TR = TF = 10 µs, IOUT = 0A to 1.2A,
2G mode
150
FSW_PFM
Minimum PFM frequency
VBATT = 3.2V, VOUT = 1.0V,
IOUT = 10 mA
100
VOUT_RIPPLE
(4)
(4)
Units
mVpp
mVpk
kHz
Ripple voltage should be measured at COUT node on a well-designed PC board, using suggested inductor and capacitors. Ripple
voltage is defined as the maximum peak-to-peak output voltage variation measured over a 100 µs period.
SYSTEM CHARACTERISTICS (BOOST-BUCK)
See SYSTEM CHARACTERISTICS (BOOST) and SYSTEM CHARACTERISTICS (BUCK) for test conditions.
Symbol
η
Parameter
Boost-Buck Efficiency
Min
Typ
VBATT = 4.0V, VOUT = 3.4V,
IOUT = 2A (2G, PWM mode)
86
VBATT = 4.0V, VOUT = 2.5V,
IOUT = 800 mA (2G, PWM mode)
89
VBATT = 4.0V, VOUT = 3.0V,
IOUT = 400 mA (2G, PWM mode)
93
VBATT = 3.4V, VOUT = 4.0V,
IOUT = 850 mA (3G/4G, PWM mode)
90
VBATT = 3.4V, VOUT = 3.0V,
IOUT = 500 mA (3G/4G, PWM mode)
94
VBATT = 3.4V, VOUT = 2.5V,
IOUT = 70 mA (3G/4G, PFM mode)
90
VBATT = 3.4V, VOUT = 0.9V,
IOUT = 200 mA (3G/4G, PWM mode)
86
VBATT = 3.6V, VOUT = 3.3V,
IOUT = 20 mA (3G/4G PFM mode)
92
VBATT = 3.4V, VOUT = 0.6V,
IOUT = 20 mA (3G/4G, PFM mode)
78
Time for VOUT to rise from 0.4V
to 4.0V (93% or 3.75V)
VBATT = 2.7, 3.2V. RLOAD = 11.4Ω,
VCON = 0.16V to 1.6V; Trise = Tfall = 1 µs
MODE = 2G (HIGH)
Time for VOUT to fall from 4.0V
to 0.4V (7% or 0.65V)
VBATT = 2.7, 3.2V. RLOAD = 11.4Ω,
VCON = 1.6V to 0.16V; Trise = Tfall = 1 µs
MODE = 2G (HIGH)
TRESPONSE
8
Condition
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Max
Units
%
15
µs
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ELECTRICAL CHARACTERISTICS (CONTROL INTERFACE)
Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating ambient temperature range
(−30°C ≤ TA ≤ +90°C). Unless otherwise noted, all specifications apply with VBATT = 2.7V to 5.5V.
Symbol
Parameter
Condition
VIH
Input high level threshold
BOOST_GATE, MODE,
ENABLE
VIL
Input low level threshold
BOOST_GATE, MODE,
ENABLE
Min
Typ
Max
Units
1.35
V
0.50
MODE, ENABLE,
BOOST_GATE Pins - HIGH
Input Current
VDD_BOOST = VDD2_BUCK = PVIN_BOOST = 3.8V
SW_BOOST = OUT_BOOST = VDD1_BUCK =
PVIN_BUCK = NO CONNECT
1) ENABLE = 1.8V, all remaining pins = GND
2) MODE = 1.8V, all remaining pins = GND
3) BOOST_GATE = 1.8V, all remaining pins = GND
MODE, ENABLE,
BOOST_GATE Pins - LOW
Input Current
VDD_BOOST = VDD2_BUCK = PVIN_BOOST= 3.8V
SW_BOOST = OUT_BOOST = VDD1_BUCK =
PVIN_BUCK = NO CONNECT
1) ENABLE = 0V, all remaining pins = 1.8V
2) MODE = ENABLE = 0V, all remaining pins = 1.8V
3) BOOST_GATE = ENABLE = 0V, all remaining pins =
1.8V
IIN
–1
0
1
µA
5 s
10 s
30 s
25 s
STARTUP TIMING
ENABLE
BOOST_GATE
t0
ENABLE must transition HIGH min. 25 µs
before BOOST_GATE is brought HIGH.
BOOST_GATE must transition HIGH min.
t1 45 µs before slot boundary. LM3248 AutoBoost cycle begins.
VCON
VCON signal change must start min. 15 µs
t2 before slot boundary. VOUT transition follows
VCON change. OUT_BOOST tracks at VOUT +
450 mV / 950 mV (3G4G/2G).
OUT_BOOST
t3 VOUT settles to within 90% of final value.
VOUT
Slot Boundary. LM3248 Boost cycle ends. New
ts boost output target selected. Start of next TTI
power control.
IOUT
Note: the BOOST_GATE minimum duration is
shown. To minimize boost circuit current drain,
the BOOST_GATE falling edge should occur as
soon after this minimum time as possible and
before the start of the next Tx slot.
PA RF POUT
t0
t = -70 s
t1
t = -45 s
Tx Slot N-1
t2
t = -15 s
t3
ts
t = 0 s
Tx Slot N
Figure 2. Startup + Optional Boost Timing Sequence
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TYPICAL CHARACTERISTICS
For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.
Switching Frequency
vs
Input Voltage
3.6
3.0
3.4
2.9
Output Voltage (V)
Switching Frequency (MHz)
Output Voltage
vs
Input Voltage (VOUT = 3.0V)
2.8
2.7
3.2
3.0
2.8
500mA
2.6
800mA
2.4
1A
2.6
1.5A
2.2
2.5
2.7
3.1
3.9
4.3
Input Voltage (V)
4.7
5.1
2.7
5.5
2.9
3.1
3.3
3.5
3.7
3.9
Figure 4.
Output Voltage
vs
Input Voltage (VOUT = 3.2V)
Output Voltage
vs
Input Voltage (VOUT = 3.4V)
3.6
3.4
3.4
3.2
3.2
2.8
500mA
2.6
800mA
2.4
1A
3.0
2.8
500mA
2.6
800mA
2.4
1A
1.5A
1.5A
2.2
2.2
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
Input Voltage (V)
4.3
2.7
3.1
3.3
3.5
3.7
3.9
4.1
Input Voltage (V)
Figure 6.
Efficiency vs Load Current
VBATT=3.4V, MODE=3G4G, TBOOSTGATE=1ms
Efficiency vs Load Current
VBATT=3.7V, MODE=3G4G, TBOOSTGATE=1ms
100
95
90
90
85
80
75
70
0.8Vout
1.5Vout
2.5Vout
3.5Vout_Boost
65
60
0.2
0.3
0.4
0.5
0.6
0.7
Load Current (A)
0.8
0.9
85
80
75
70
1.0Vout
2.0Vout
3.0Vout
4.0Vout_Boost
0.8Vout
1.5Vout
2.5Vout
3.5Vout
65
60
1.0
4.3
C005
Figure 5.
95
0.1
2.9
C006
Efficiency (%)
Efficiency (%)
100
0.1
C009
Figure 7.
10
4.3
C007
Figure 3.
3.0
4.1
Input Voltage (V)
C008
Output Voltage (V)
Output Voltage (V)
3.6
3.5
0.2
0.3
0.4
1.0Vout
2.0Vout
3.0Vout
4.0Vout_Boost
0.5
0.6
0.7
Load Current (A)
0.8
0.9
1.0
C010
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.
100.00
100
95.00
95
90.00
90
Efficiency (%)
Efficiency (%)
Efficiency vs Load Current
VBATT=3.4V, MODE=3G4G, TBOOSTGATE=10ms
85.00
80.00
75.00
70.00
0.8Vout
1.5Vout
2.5Vout
3.5Vout_Boost
65.00
60.00
0.1
0.2
0.3
0.4
0.5
0.6
0.8
0.9
85
80
75
70
1.0Vout
2.0Vout
3.0Vout
4.0Vout_Boost
0.7
0.8Vout
1.5Vout
2.5Vout
3.5Vout
65
60
1.0
Load Current (A)
Efficiency vs Load Current
VBATT=3.7V, MODE=3G4G, TBOOSTGATE=10ms
0.1
0.2
0.6
0.7
0.8
0.9
1.0
C003
Efficiency vs Load Current
VBATT=3.7V, MODE=3G4G, BOOST_GATE=LOW
100
95
90
90
Efficiency (%)
Efficiency (%)
Efficiency vs Load Current
VBATT=3.4V, MODE=3G4G, BOOST_GATE=LOW
85
80
75
70
65
60
0.01
0.4Vout
0.8Vout
1.5Vout
2.5Vout
0.6Vout
1.0Vout
2.0Vout
3.0Vout
0.10
85
80
75
65
60
0.01
1.00
0.10
1.00
C004
Figure 12.
Efficiency vs Load Current
VBATT=3.0V, MODE=2G, TBOOSTGATE=4.62ms
100
95
90
90
Efficiency (%)
95
85
80
75
70
60
0.15
0.6Vout
1.0Vout
2.0Vout
3.0Vout
Load Current (A)
C001
Figure 11.
65
0.4Vout
0.8Vout
1.5Vout
2.5Vout
3.5Vout
70
Load Current (A)
Efficiency (%)
0.5
Figure 10.
95
100
0.4
Load Current (A)
C002
Figure 9.
100
0.3
1.0Vout
2.0Vout
3.0Vout
4.0Vout_Boost
Efficiency vs Load Current
VBATT=3.4V, MODE=2G, TBOOSTGATE=4.62ms
85
80
75
70
0.8Vout
1.8Vout
3.0Vout
1.0Vout
2.5Vout
3.4Vout
65
60
0.15
1.50
Load Current (A)
C012
Figure 13.
0.8Vout
1.8Vout
3.0Vout
1.0Vout
2.5Vout
3.4Vout
1.50
Load Current (A)
C013
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.
100
95
95
90
90
Efficiency (%)
Efficiency (%)
100
Efficiency vs Load Current
VBATT=3.7V, MODE=2G, TBOOSTGATE=4.62ms
85
80
75
70
85
80
75
70
0.8Vout
1.8Vout
3.0Vout
65
60
0.15
1.0Vout
2.5Vout
3.4Vout
60
0.15
1.50
C015
Figure 15.
Figure 16.
Efficiency vs Load Current
VBATT=4.0V, MODE=2G, BOOST_GATE=LOW
Line Transient
VBATT=3.6V↔4.2V, TR=TF= 10µS, VOUT=1.0V, Load=600mA
3.6V to
4.2V
VBATT
90
Efficiency (%)
1.0Vout
2.5Vout
3.4Vout
Load Current (A)
C014
95
500mV/DIV
85
80
VBUCK_OUT(AC)
100mV/DIV
IOUT
500mA/DIV
75
70
0.4Vout
0.8Vout
1.8Vout
3.0Vout
65
60
0.01
0.10
1.00
Load Current (A)
0.6Vout
1.0Vout
2.5Vout
3.4Vout
10.00
100µS/DIV
C011
Figure 17.
Figure 18.
Load Transient
VBATT=3.8V, VOUT=3.0V, MODE=LOW, Load= 0A↔1.2A,
TR=TF=10µS
Load Transient
VBATT=3.0V, VOUT=3.6V, MODE=1.8V, Load=0↔2A,
TR=TF=10µS
500mV/DIV
VBATT
VBATT
500mV/DIV
50mV/DIV
VBUCK_OUT(AC)
500mA/DIV
IOUT
50mV/DIV
IOUT
100µS/DIV
500mA/DIV
100µS/DIV
Figure 19.
12
0.8Vout
1.8Vout
3.0Vout
65
1.50
Load Current (A)
100
Efficiency vs Load Current
VBATT=4.0V, MODE=2G, TBOOSTGATE=4.62ms
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
For all Efficiency vs Load Current graphs, L1=1276AS-H-1R0N, L3=1285AS-H-1R5N.
Startup in Auto-Boost Mode
VBATT=2.7V, Load=200 mA, MODE=2G, VOUT=0.4↔4V,
TR=TF=10µS
Timed Output Current Limit into Short Circuit
VBATT=4.3V, VOUT=2.5V, Load=6.8Ω/Short to GND
2V/DIV
ENA
VOUT
2V/DIV
2V/DIV
BOOST_GATE
SW_BUCK
2V/DIV
500mV/DIV
VCON
1A/DIV
1V/DIV
VOUT
IL (Buck)
20µS/DIV
40µS/DIV
Figure 21.
Figure 22.
VCON Transient with Boost Active
VBATT=3.2V, MODE=2G, VOUT= 0.4↔4 V, Load=11.4Ω
VCON Transient Response
VBATT=3.8V, VOUT= 0.8V↔3.3V, MODE=LOW
BOOST_GATE=LOW, Load=20Ω, TR=TF=10µS
2V/DIV
TRISE = 7.8µS
ENA
TFALL = 7.6µS
2V/DIV
BOOST_GATE
VBUCK_OUT
500mV/DIV
500mV/DIV
VCON
1V/DIV
VOUT
IOUT
50mA/DIV
1V/DIV
VCON
20µS/DIV
20µS/DIV
Figure 23.
Figure 24.
VCON Transient Response
VBATT=3.8V, VOUT= 1.4V↔3.4V, MODE=LOW
BOOST_GATE=LOW, Load=6.8Ω, TR=TF=10µS
VCON Transient Response
VBATT=3.8V, VOUT=1.0V, MODE=LOW
BOOST_GATE=LOW, Load=0A↔60mA, TR=TF=10µS
TRISE = 6.8µS
TFALL = 6.2µS
VOUT
500mV/DIV
IOUT
200mA/DIV
VOUT_AC
10mV/DIV
IOUT
20mA/DIV
1V/DIV
VCON
20µS/DIV
20µS/DIV
Figure 25.
Figure 26.
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FUNCTIONAL DESCRIPTION
The LM3248 is a high-efficiency boost-buck DC/DC converter used in mobile phones and other battery-powered
RF devices to improve overall system efficiency by tailoring RF PA stage supply rail voltages to RF output power
levels. The LM3248 optimizes efficiency over a wide range of power levels when using Li polymer battery cells
operating as low as 2.7V.
The LM3248 architecture is comprised of a step-up (boost) DC/DC switching converter followed by a step-down
(buck) DC/DC switching converter. This cascaded boost-buck architecture allows the device to support output
voltages that are either above or below the input battery voltage, while simultaneously providing excellent output
transient and noise performance. See Figure 27 for more details. The LM3248 minimizes 3G/4G/4G-LTE
Advanced current consumption in User Equipment (UE) transmit power distribution environments and, in
addition, supports higher power 2G functionality.
1 F Low ESL
1.0 H
10 F
VBATT
2.7V to 5.5V
SW_
BOOST
OUT_
BOOST
PVIN_
BUCK
VDD1_
BUCK
VDD2_
BUCK
FB_
BUCK
PVIN_
BOOST
ACB
10 F
SW_
BUCK
ACB
BYPASS
BUCK
BOOST
VDD_
BOOST
1.5 H
VCC_PA
10 F
CONTROL
BOOST_
SGND_
ENABLE GATE MODE BUCK
BGND
DGND
1 nF
VCON
PGND
SGND_
BOOST
FB
1.8V Logic
Apps
Processor
Figure 27. Typical Application: Boost-Buck
Boost Converter
The Boost DC/DC converter enables the LM3248 to support output voltages that are either above or below the
input battery voltage. The Boost converter can be operated in either Boost or Boost-Bypass (Buck Only) modes.
Both modes of operation require the device to be enabled (ENABLE) and either 2G or 3G/4G mode (MODE) to
be selected. Boost mode automatically engages the boost circuit when needed and requires an additional digital
control signal, BOOST_GATE. The Buck output settles to new VCON levels approximately 45 µs after
BOOST_GATE transitions from LOW to HIGH (see Figure 2).
The Boost converter output (OUT_BOOST) is externally (and internally) connected to the Buck input
(PVIN_BUCK) supply voltage. The Boost converter enables increased PA efficiency and higher linearity at higher
Tx power settings when the battery voltage is lower than normally required. A unique synchronization scheme
allows the Boost and Buck voltage transitions to occur with minimal time-critical programming. The LM3248
should be operated in Boost-Bypass mode (Buck-Only, BOOST_GATE=LOW) when it is known that the Buck
output voltage will be lower than the battery voltage, such as at low transmit RF power levels. This practice
reduces unnecessary battery drain caused by boost bias circuits and improves efficiency.
When Boost operation is selected (BOOST_GATE=HIGH), the LM3248 monitors the input voltage and compares
it with the VCON output control voltage setting. The Boost circuit is activated on the rising edge of
BOOST_GATE when VBOOST, the target boost output voltage, is greater than the input or battery voltage (VBATT)
to achieve the desired output voltage level, according to the equations:
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VBOOST = VCON * 2.5 + 0 mV [VBOOST > VBATT] (3G or 4G mode)
or
VBOOST = VCON * 2.5 + 125 mV [VBOOST > VBATT] (2G mode)
Once in Boost mode, the Boost voltage automatically adjusts according to the following equations:
VBOOST = VCON * 2.5 + 450 mV [VBOOST > VBATT] (3G or 4G mode)
or
VBOOST = VCON * 2.5 + 950 mV [VBOOST > VBATT] (2G mode)
In Boost mode, internal circuitry will automatically engage the large bypass switch to prevent the Boost output
from ever falling below the battery voltage, VBATT, by more than a few hundred millivolts (200 mV typ.) when
Boost-Bypass conditions are not met. This functionality is described below.
When operating in Boost mode, the BOOST_GATE signal should be toggled between HIGH and LOW logic
levels at a rate synchronous with the Transmission Time Interval (TTI) frame, per the Startup Timing
requirements given in Figure 2. This provides sufficient setup time for the Boost bias circuits to activate before
the new (possibly higher) Buck output level is updated, ensuring a smooth transition between levels.
Note that VBOOST programmed output levels are determined by the VCON command voltage; not by the Buck
DC/DC converter output voltage, VCC_PA. This is necessary to minimize Boost output voltage tracking delay
times.
Boost active due to VCON * 2.5
crossing VBATT-VBYP threshold
(VBOOST §9&21* 2.5 + Voverhead)
Boost transitions to
Bypass due to VBOOST
target (VCON * 2.5)
dropping below
VBATT-VBYP threshold.
Voverhead §0.45V (3G/4G)
§0.95V (2G)
VBATT
VBOOSTBYP §5BOOST * Input Current
VBOOST (in Bypass)
VBATT ± 0mV (3G/4G)
VBATT ± 125mV (2G)
VBYP §(RBOOST + RBUCK) *
LoadCurrent
VCON * 2.5
Figure 28. Boost Operation showing VCON-VBATT Relationship
Boost-Bypass Function
The LM3248 provides a bypass function with very low dropout resistance when the Boost stage is not needed to
support the output voltage requirements. The Boost circuit automatically enters Boost-Bypass mode when
BOOST_GATE is high and the VCON voltage is approximately less than VCON(max), as shown below:
VCON(max) =
VCON(max) =
[VBATT í 0 mV]
2.5
[VBATT í 125 mV]
2.5
(3G or 4G mode)
(2G mode)
In Boost-Bypass mode, the low resistance (75 mΩ typ.) bypass circuit effectively connects the PVIN_BOOST and
OUT_BOOST pins in parallel with the boost inductor and boost output power transistor. The Boost-Bypass circuit
is active at all times when BOOST_GATE=LOW. When Boost-Bypass is active, the minimum total dropout
resistance of the path between the PVIN_BOOST and OUT_BOOST pins is 60 mΩ (typ.). The Boost-Bypass
mode of operation is valid for 2.7V < VBATT < 5.5V.
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Buck Converter
The Buck converter output voltage, VCC_PA, is directly proportional to the VCON control voltage, which level is
determined by the applications processor, BBIC or RFIC RF output Power Amplifier control algorithm. The user
can dynamically program the Buck output voltage from 0.4V to 4.0V (typ.) by adjusting the VCON voltage setting,
per the equation: VCC_PA = VCON * 2.5.
The LM3248 has been designed to make rapid, smooth VCC_PA output transitions required by fast 3G/4G and 2G
burst ramp profiles.
The current consumption of RF Power Amplifier modules (RF PAs) typically increases with supply voltage.
Accordingly, DC/DC converter output power requirements increase as the RF PA module VCC_PA voltages
increase. Two operating methods, Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM), are
used to optimize system efficiency over a range of PA power levels. When the LM3248 is not needed, the device
can be set to shutdown mode (ENABLE = LOW) to minimize battery current drain. Current overload protection
and thermal overload shutdown are also provided.
2G vs. 3G/4G Modes
The MODE pin enables selection of either constant PWM (2G) or automatic PWM/PFM (3G/4G) operation.
To maintain higher efficiency at light loads, the 3G/4G mode setting is used. When in Boost-Bypass, and average
inductor current drops below 45 to 90 mA (typ.), PFM operation is active. The switching frequency is reduced to
improve efficiency. Conversely, the LM3248 transitions back to PWM operation from PFM when the average
inductor current increases to values above 90 to 160 mA (typ.). Automatic transition into PWM operation also
occurs if the output voltage falls more than 25 mV due to a load current increase.
Active Current and Analog Bypass (ACB)
Fast transient 2G power bursts require high current levels to be sourced or sunk from the LM3248 Buck DC/DC
converter. The Active Current assist and analog Bypass (ACB) feature, built into the Buck DC/DC converter,
enables smooth waveform transitions with load currents as high as 2.5A using smaller footprint inductors and
meets all of the transient requirements when supplying VCC_PA voltages for the latest multi-mode RF Power
Amplifier modules. The ACB circuit provides an additional current path when the load current exceeds 1.4A (typ.)
or as the switcher approaches dropout. Similarly, the ACB circuit enables the LM3248 to respond with faster
output voltage transition times by providing extra output current on rising and falling output edges. The LM3248
handles bypass events by sensing input voltage, output voltage, and load current conditions, and then
automatically and seamlessly transitioning the converter into analog bypass, while maintaining output voltage
regulation and low output voltage ripple. Full bypass (100% duty cycle) will occur if the total dropout resistance in
bypass mode (≈ 50 mΩ) is insufficient to regulate the output voltage.
Shutdown
When the LM3248 ENABLE = LOW, the Buck and Boost DC/DC converters and control circuits are programmed
into an OFF (Shutdown) state and the output power switches are placed in a tri-state condition. The Shutdown
state reduces system current consumption to less than 4 µA.
Output Current Protection
The Buck DC/DC converter and the ACB circuit each have output current protection. The Buck converter
includes a steady-state current limit which monitors load currents and enables the ACB circuit. During transient
over-current conditions the peak current limit detector turns off the PFET switch within the current PWM cycle
and initiates the timed output current limit.
Timed Output Current Limit
If the output load current rises above the ILIM,PFET,Transient threshold continuously for more than 11 μs, and the
output voltage falls below 0.3V (typ.), the LM3248 Buck DC/DC converter switch node (SW_BUCK pin) is put into
a high-impedance state, and the ACB circuit is disabled. The power switch then remains disabled for a period of
35 µs to force the inductor current to ramp down. If the short circuit condition continues, the cycle will repeat.
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Thermal Overload Protection
The LM3248 IC has thermal overload protection that disables the device, protecting it from short-term misuse
and overload conditions. If the junction temperature exceeds 150°C (typ.), all of the power functions will be
turned off. Normal operation resumes after the temperature drops below 130°C (typ.), and the LM3248 will
attempt to return to the operating state before the over-temperature condition occurred. Prolonged operation in
thermal overload condition may damage the device and is therefore not recommended.
Digital Control Signals
The BOOST_GATE, MODE and ENABLE pins are 1.8V logic-level inputs for controlling the LM3248. A logic
LOW level applied to the ENABLE pin puts the LM3248 into a Shutdown state, where minimum current is drawn
from the battery. The MODE pin allows the user to select whether PWM (2G) or PWM/PFM (3G/4G) operation is
allowed. The BOOST_GATE pin enables the Boost DC/DC converter circuitry and related functionality.
Manufacturing Considerations
Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow
techniques, as detailed in Texas Instruments Application Note AN-1112 (SNVA009). Please refer to the section
Surface Mount Assembly Considerations. For best results in assembly, local alignment fiducial markers on the
PC board should be used to facilitate placement of the device.
The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that
the solder-mask opening is larger than the pad size. This prevents a lip that would otherwise form if the soldermask and pad overlap, which would hold the device off the surface of the board and interfere with mounting. See
Application Note AN-1112 (SNVA009) for specific instructions how to do this.
The 30-bump(5x6) DSBGA package used for the LM3248 has the following Non-Solder Mask Defined (NSMD)
mounting specifications:
• Solder ball diameter: 0.265 mm
• Copper pad size: 0.225 mm ± 0.02 mm
• Solder mask opening: 0.325 ± 0.02 mm
The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep
corners. Symmetry is important to ensure the solder bumps re-flow evenly and that the device solders level to
the board. In particular, special attention must be paid to the pads for bumps A1-A5, C4, C5, E4, E5, F4 and F5
since PVIN_BOOST, OUT_BOOST, PGND, PVIN_BUCK and ACB may be connected to large copper planes
and inadequate thermal reliefs can result in inadequate re-flow of these bumps.
Typical Solution Size
C1
1005
t4.25mmt
L1
3225
C9
0603
C8
1005
C2 0816
FB1
1005
LM3248 IC
2.5 mm x 2.8 mm
Boost + Buck
L3
2016
C7
1005
t7.25mmt
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APPLICATION INFORMATION
Recommended External Components
Inductor Selection
The LM3248 was designed to work with 1.0 µH and 1.5 µH buck inductors. The largest current magnitudes
encountered with the LM3248 are in 2G mode (that is, 2.5A for 2G vs. <1A for 3G/4G). Because of the low duty
cycles encountered with 2G transmission bursts, the maximum RMS current encountered is much less than the
peak.
Suitable inductors are typically rated for maximum current with two different numbers:
1. ΔL/L = 30% (or similar) which means the current level that causes a 30% drop in the inductance value (due
to core saturation), and
2. ΔT = 40°C (or similar) which means the current level that causes a 40°C rise in the inductor's temperature.
Because of the “peaky” nature of 2G current waveforms (low duty cycle, high peak-to-average ratio), the
“ΔL/L=30%” (or similar) current limit will typically be reached long before the “ΔT=40°C” (or similar) current value.
This means that selection of the inductor is saturation-limited.
Another way of saying this is that the inductor core saturation is proportional to the peak current value, while the
temperature rise is due to the RMS current value. As a result, candidate inductors which may appear too small
for the application when looking at the “ΔT=40°C” (or similar) current specification, may be sufficiently sized, as
long as the “ΔL/L = 30%” (or similar) current value is less than the peak current required for the application.
If the “ΔL/L = 30%” (or similar) current value is not specified, or it is not clear whether the max current rating for
the part refers to either one of these rules of measure, this information should be requested from the supplier.
The LM3248 automatically manages the inductor peak and RMS current (or steady-state current peak) through
the SW_BUCK pin. The SW_BUCK pin has two positive current limits. The first is the 1.45A typical (or 1.65A
maximum) overcurrent protection which sets the upper steady-state inductor peak current (as detailed in the
ELECTRICAL CHARACTERISTICS (BUCK) parameter "ILIM,PFET,SteadyState"). It is the dominant factor limiting
currents from surpassing the buck inductor ISAT specification. The second is an over-limit current protection
"ILIM,PFET,Transient" found in the SYSTEM CHARACTERISTICS (BUCK) table. It limits the maximum peak inductor
current during large signal transients (i.e., < 20 µs) to 1.9A typical (2.1A maximum). When selecting the buck
output inductor, the user should insure that a minimum of 0.3 µH is maintained when peak currents reach the
ILIM,PFET,Transient current limit.
The ACB circuit automatically adjusts its output current to keep the steady-state inductor current below the
ILIM,PFET,Steady State current limit. The inductor RMS current will always be less than this value during the transmit
burst, thus keeping the inductor within its thermal operating limits.
For good efficiency, the inductor's resistance should be less than 0.15Ω. Low DCR inductors (< 0.15Ω) are
recommended. Table 1 suggests some inductors and their suppliers. The slightly larger inductors listed in
Table 1 were observed to enhance efficiency 1 to 2% under some VIN/VOUT/Load conditions.
Table 1. Suggested Inductors and Their Suppliers
Boost Inductor 1.0 µH, 3225, 3.0A, 60 mΩ
Model
Vendor
Dimensions (mm)
ISAT (–30%) (A)
DCR (mΩ)
1276AS-H-1R0N
TOKO
3.2 x 2.5 x 1.0
3.9
48
CIG32W1R0MNE
Samsung
3.2 x 2.5 x 1.0
3.0
60
1277AS-H-1R0M
TOKO
3.2 x 2.5 x 1.2
4.6
37
Model
Vendor
Dimensions (mm)
ISAT (–30%) (A)
DCR (mΩ)
Buck Inductor 1.5 µH, 2016 or 2520, 2.2A, 150 mΩ
18
1285AS-H-1R5N
TOKO
2.0 x 1.6 x 1.0
2.2
120
LQM2MPN1R5MG
Murata
2.0 x 1.6 x 1.0
2.0
110
MAKK2016T1R5M
Taiyo-Yuden
2.0 x 1.6 x 1.0
1.9
115
VLS201610MT-1R5N
TDK
2.0 x 1.6 x 1.0
1.4
151
1239AS-H-1R5N
TOKO
2.5 x 2.0 x 1.2
3.3
60
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Capacitor Selection
The LM3248 is designed to use ceramic capacitors for input and output decoupling. Use a 10 μF capacitor for
the input and approximately 10 μF actual total output capacitance. Capacitor types such as X5R and X7R are
recommended for both filters. These provide an optimal balance between small size, cost, reliability and
performance for cell phones and similar applications. Table 2 lists suggested part numbers and suppliers. DC
bias characteristics of the capacitors must be considered while selecting the voltage rating and case size of the
capacitor. Smaller 0402 (1005) case size capacitors are recommended for filtering. Use of multiple 2.2 μF or 1
μF capacitors can also be considered. For RF Power Amplifier applications, split the output capacitor between
DC-DC converter and RF Power Amplifiers: 10 μF (COUT1) + 4.7 μF (COUT2) + 3 x 1.0 μF (COUT3) is
recommended. The optimum capacitance split is application dependent, and for stability the actual total
capacitance (taking into account effects of capacitor DC bias, temperature de-rating, aging and other capacitor
tolerances) should target 10 μF with 2.5V DC bias (measured at 0.5 VRMS). Place all the output capacitors very
close to the respective device. A high-frequency capacitor (3300 pF) is highly recommended to be placed next to
COUT1.
Table 2. Suggested Capacitors and Their Suppliers
Capacitance
Model
Dimensions (mm)
Vendor
10 µF 6.3V X5R
CL05A106MQ5NUNC
1.0 x 0.5
Samsung
4.7 µF 10V X5R
GRM155R61A475M
1.0 x 0.5
Murata
1 µF 10V X5R
LWK107BJ105MV
0.8 x 1.6
Taiyo Yuden
1 µF 10V X5R
CL03A105MP3NSNC
0.61 x 0.3
Samsung
0.22 µF 6.3V X5R
C0603X5R0J224M
0.61 x 0.3
TDK
0.01 µF 6.3V X5R
C0603X5R0J103K
0.61 x 0.3
TDK
1000 pF 25V X7R
GRM033R71E102KA01D
0.61 x 0.3
Murata
100 pF 25V X7R
GRM033R71E101KA01D
0.61 x 0.3
Murata
3300 pF 6.3V X5R
C0402X5R0J332K020BC
0.41 x 0.2
TDK
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LM3248
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PCB LAYOUT CONSIDERATIONS
Overview
PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board
layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also
addressing manufacturing issues that can have adverse impacts on board quality and final product yield.
PCB
Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC
converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to
poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or
degraded performance of the converter.
Energy Efficiency
Minimize resistive losses by using wide traces between the power components and doubling up traces on
multiple layers when possible.
EMI
By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to
minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the
LM3248, switches Ampere-level currents within nanoseconds, and the traces interconnecting the associated
components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is
maintained within tolerable levels.
To help minimize radiated noise:
• Place the LM3248 DC-DC converter, its input capacitor, and output filter inductor and capacitor close
together, and make the interconnecting traces as short as possible.
• Arrange the components so that the switching current loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3248 and the
inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of
each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3248 by the
inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing
these loops so the current curls in the same direction prevents magnetic field reversal between the two halfcycles and reduces radiated noise.
• Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return
paths, where possible, to further minimize trace inductances.
To help minimize conducted noise in the ground-plane:
• Reduce the amount of switching current that circulates through the ground plane by connecting the ground
bumps of the LM3248 and the boost output/buck input filter capacitors together using generous componentside copper fill as a pseudo-ground plane. Then connect this copper fill to the system ground-plane by
multiple vias. The multiple vias help to minimize ground bounce at the LM3248 by giving it a low-impedance
ground connection.
To help minimize coupling to the DC-DC converter's own voltage feedback trace:
• Route noise sensitive traces, such as the voltage feedback path (FB_BUCK), as directly as possible from the
switcher FB_BUCK pad to the VOUT pad of the output capacitor, but keep them away from noisy traces
between the power components.
20
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To help minimize noise coupled back into power supplies:
• Use a star connection to route from the VBATT power source to the LM3248 PVIN_BOOST pins and to
the PA device VBATT pins.
• Include sufficient decoupling capacitance, for both low and high frequency, at the PA VBATT connections.
• Route traces for minimum inductance (short, wide connections) between supply pins and bypass capacitor(s).
• Route traces to minimize inductance between bypass capacitors and the ground plane.
• Utilize necessary power supply trace inductance(s) to reduce coupling between function blocks.
• Inserting a ferrite bead in series with the VBATT power supply trace may offer a favorable tradeoff between
board area and additional shunt bypass capacitors, by attenuating noise that might otherwise propagate
through the supply connections.
4. LM3248 RF Evaluation Board
VBATT_PA
L1
VBATT
C34
1 nF
C1
10 nF
C27
1 µF
Lo ESL
1.0 µH
C28
10 µF
GPO1
GPO2
GPO3
DAC
ENABLE
BOOST GATE
MODE
VCON
LM3248
PVIN_BUCK
SW_BOOST
C2 BOOST
10 µF
OUT_BOOST
U2
PVIN_
SW_
BUCK
L3
1.5 µH
VOUT
C8
3.3 nF
C7
10 µF
VCC_PA_2G
FB_
BUCK
C3
4.7 µF
ACB
PGND SGND
C5
3.3 nF
BGND
VCC_PA_3G
BB or
RFIC
PA
C19
330 pF
C20
2.2 µF
PA(s)
VBATT_PA
Figure 29. Simplified LM3248 RF Evaluation Board Schematic
LM3248 PCB Placement Considerations
1.
2.
3.
4.
5.
Input Capacitor C2 should be placed closer to LM3248 than C1.
Optional to add a 1 nF (C34) capacitor on the input of LM3248 for high frequency filtering.
Bulk Output Capacitor C7 should be placed closer to LM3248 than C8.
Connect GND terminals of C7, C8 and C34 directly to System RF GND layer of phone board.
Connect GND terminals of boost output C27 and buck input C28 capacitors to copper PGND island on the
component side. This island is then tied to the system ground layer through several vias.
6. Connect bumps SGND_BOOST(B2), SGND_BUCK(C3), DGND(E3), and BGND (F3) directly to system
ground layer.
7. Small high-frequency filtering capacitors (e.g., C34) work better when they are connected to system ground
instead of the PGND island. These capacitors should be 0201 (0603 metric) or 01005 (0402 metric) case
size for minimum footprint and best high frequency characteristics.
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LM3248
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RF Evaluation Board Layout Overview
DC-DC
converter
section
3G PA
section
MMMB PA
section
Figure 30. Top View of RF Evaluation Board
The LM3248 RF Evaluation board consists of the LM3248 DC/DC converter and two RF Power Amplifier
stages – a standard 3x3 mm footprint “3G PA” and a Multi-Mode MultiBand (“MMMB PA”) 2G+3G/4G Power
Amplifier. These circuits are outlined in Figure 30.
22
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Layout Recommendations
Multi-Layer Chip-Capacitors (MLCC), rather than Tantalum, should be used in the LM3248 DC/DC converter, in
order to minimize ESR effects.
One of the most important details is routing the power feed in a way that does not induce noise between the PA
and DC/DC converter circuits that are connected to the common power feed. The “star connection” previously
mentioned is illustrated below in Figure 31. The key is to route the power connections from the VBATT power
source to the PA and DC/DC converters separately, so that there is no shared current path – they only join at the
power source. If this is not possible, due to other constraints, it is wise to design in pads for ferrite beads in
series with the VBATT connection to the device, at least in prototype layouts, so that additional filtering is available
when performance is validated (see Figure 32).
Cuttable jumper
for ferrite bead
(if needed)
VBATT (+) ³VWDU´
connection to DC/DC
converter
(power feeds join only at
the power source)
Separate VBATT (+)
connection to PA
sections
PA sections
VCC_PA_2G
routing
(layer 4)
Note: this image shows multiple layers.
Figure 31. LM3248 VBATT Star Connection and VCC_PA Routing
Critical Boost Output/Buck Input Capacitors
The most critical placement and connections are the boost output/buck input filter capacitors, C27 and C28,
which should be located as close as possible to the U2 LM3248 device OUT_BOOST/PVIN_BUCK and PGND
pads. These two capacitors decouple the fastest (highest di/dt) switching currents in the power supply. By
minimizing the connection length (inductance) between these capacitor and the LM3248 device pads, the user
minimizes the noise that may propagate back into the VBATT power bus. The best method to connect these
components to the LM3248 is short, direct connecting traces from the capacitor pads to the device pads on the
same layer (vias are resistive+inductive and impede the fast switching current flow). This is illustrated in
Figure 32, below, with arrows indicating the fast circulating current flows. Note the copper PGND island, which
joins the major current-carrying bypass capacitor GND terminals, C2, C27, and C28.
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LM3248
SNVSA01A – JULY 2013 – REVISED SEPTEMBER 2013
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C34 HF
decoupling to
system ground
C27, C28 short,
direct conn., all
on comp layer
PGND
Island
System
Ground
ACB
connection
ties directly
to L3/C7
junction
Figure 32. LM3248 Decoupling Cap Placement
(Top View, Component Layer)
The VBATT supply currents replenish the main decoupling caps mounted to the PGND island through the system
ground by way of several vias, so that the fast switching currents are confined to the component layer. This
technique reduces ground-plane noise by reducing the amount of switching current that circulates through the
system ground plane. An additional high-frequency decoupling capacitor (C34, 1 nF, 0201 case size) is
recommended between the main power (VBATT) feed and the system ground (not to PGND) to return any
common mode switching currents that appear on these surfaces.
The Active Current Assist and Bypass (ACB) trace should be kept short and routed directly from ACB pin to the
junction of output inductor L3 and output capacitor C7 (see Figure 32).
Minimizing Switching Noise
Next, the boost and buck inductors, L1 and L3, should be placed so that routing will minimize exposure of the
“noisy” end of each of these components to surrounding circuitry that ties directly to the SW_BUCK and
SW_BOOST pins. Specifically, the FB_BUCK feedback sense connection should be routed away from the
SW_BUCK (or SW_BOOST) nodes. Ideally, make a short, direct connection from the FB_BUCK pin to the
junction of the output capacitor, C7, and buck output inductor, L3. This trace is a voltage sense connection and
does not carry significant current (trace width is not critical). If this connection must be routed under either L1 or
L3 inductors, there should be a ground layer between this trace and the noisy end of the inductor(s) to provide
shielding. Connect output capacitors C7 and C8 directly to the system ground (not to the PGND copper island).
In this example, C7 and C8 are routed to the Layer 3 system ground through multiple vias (see Figure 32 and
Figure 33), which is acceptable, since they do not carry extremely fast (high di/dt) switching currents.
24
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System
Ground
Noisy end of L3
(SW_BUCK)
FB_BUCK trace
does not run
underneath L3
Figure 33. LM3248 Buck Feedback and Inductor L3 Routing for Low Noise
(Layer 3 shown with Layer 1 Component Overlay)
The SW_BOOST routing to L1 is shown in Figure 34. Note the noisy end of inductor L1 does not cross sensitive
the FB_BUCK trace, but is routed away from it.
Noisy end of L1
(SW_BOOST)
Strap joining
Boost output to
Buck input
Figure 34. LM3248 Inductor L1 Routing for Low Noise
(Layer 2 shown with Layer 1 Component Overlay)
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LM3248
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REVISION HISTORY
Changes from Original (August 2013) to Revision A
•
26
Page
Changed Product Brief for Full Datasheet; 2 figures: Boost/Buck Output Voltage Timing Diagram and Boost
Operation showing VCON-VBATT Relationship .................................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM3248TME/NOPB
ACTIVE
DSBGA
YFQ
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-30 to 90
3248
LM3248TMX/NOPB
ACTIVE
DSBGA
YFQ
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-30 to 90
3248
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM3248TME/NOPB
DSBGA
YFQ
30
250
178.0
8.4
LM3248TMX/NOPB
DSBGA
YFQ
30
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.67
2.95
0.76
4.0
8.0
Q1
2.67
2.95
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3248TME/NOPB
DSBGA
YFQ
LM3248TMX/NOPB
DSBGA
YFQ
30
250
210.0
185.0
35.0
30
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YFQ0030xxx
D
0.600
±0.075
E
TMD30XXX (Rev B)
D: Max = 2.829 mm, Min =2.769 mm
E: Max = 2.453 mm, Min =2.393 mm
4215085/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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