Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
Realization of cascadable electro-optical
hybrid RS flip flop using hybrid NAND
gates
Ekkurthi.Sreenivasa Rao
E.C.E Department,Vasavi College of Engineering, Hyderabad,
e.sreenivasarao@staff.vce.ac.in
M.Satyam,
Professor of E.C.E (Retd.), IIIT, Hyderabad,
satyam@iiit.ac.in
K.Lal Kishore,
Professor of E.C.E (Retd.), J.N.T.University, Hyderabad,
lalkishorek@yahoo.com
Abstract - An Electro-Optical Hybrid Flip Flop is defined as a sequential circuit which accept electrical
and/or optical signals and produces both electrical and optical signals. The basic building blocks for
developing large and complex sequential circuits and systems are flip flops. This paper reports the
feasibility of developing cascadable electro-optical hybrid RS flip flop. The realization of the basic hybrid
RS flip flop using hybrid NAND gates has been discussed and its functionality is demonstrated. The
circuit is found to be working satisfactorily.
Key words: Hybrid Circuits, Hybrid Flip Flops, Hybrid Logic Gates, Optoelectronics, Hybrid
Optoelectronics, Electro-Optical Logic Gates, Electro-Optical Hybrid Flip Flops.
I.
INTRODUCTION
Flip flops are the basic building blocks for developing large and complex sequential circuits and systems.
Several research groups have reported different types of optical flip flops. Chang-Hee Lee et al realized an
optical flip flop [1] with a very simple structure based on optoelectronic feedback using discrete components. T.
Chino et al reported an integrated optoelectronic RS flip flop [2] based on optically coupled inverters. K.
Matsuda et al reported optoelectronic bitable switches and latching device [3-4]. X.An et al demonstrated
optical set-reset memory pixel [5]. The need for optically controlled bistable, astable and tristable devices is
amply explained by S.Noda et al from the point of optical computing [6]. M.K.Ravishankar and M.Satyam
reported a bitable multivibrator [7] which can be triggered optically/electrically. In general, latches and flip
flops are realized using universal logic gates like NOR/NAND. Most of the research groups have reported
latches/flip flops, which responds to only one stimulus namely either electrical or optical signals and most of
them are not cascadable. This paper presents the feasibility of developing cascadable electro-optical hybrid RS
flip flop using universal hybrid NAND gates. Universal electro-optical hybrid logic gates [8] have already been
published by the authors of this paper. The electro-optical hybrid RS flip flop presented in this paper is intended
to demonstrate the functionality of the flip flop. In the first instance, the definition of electrical and optical logic
levels of hybrid NAND gate are presented and thereafter, realization of hybrid RS flip flop is discussed.
II. DEFINITION OF ELECTRICAL AND OPTICAL LOGIC LEVELS
The basic hybrid RS flip flop has been realized using well known concept i.e., by cross coupling two hybrid
NAND gates and the coupling can be either electrical or optical in nature. As the flip flops are used in building
large and complex sequential circuits and systems, it is necessary for each flip flop to have the capacity to drive
the output stage(s) in the system. It means that they must be cascadable. The requirement for achieving
cascadability is that the input logic levels and the output logic levels of the flip flop should be almost the same
or at least they should be within tolerable logic levels, so that there is no degradation in the cascaded system.
Electrical and optical logic levels are defined as per the noise margin criteria for digital logic circuits [9] using
the universal electro-optical hybrid NAND gate and are explained below.
Ideally, electrical LOW input/output logic level is defined as 0V and 5V as electrical HIGH input/output logic
level. The tolerable input voltages VIL and VIH are measured using the points at which the slope of the Voltage
Transfer Characteristics (VTC) of hybrid NAND gate shown in Fig.1 equals −1, where, VIL is the maximum
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
219
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
input voltage that will be recognized as tolerable LOW input logic level and VIH is the minimum input voltage
that will be recognized as tolerable electrical input logic level HIGH. Voltages below VIL are reliably
recognized as electrical logic level LOW at the input of a logic gate, and voltages above VIH are recognized
reliably as electrical logic level HIGH at the input. Voltages corresponding to the region between VIL and VIH do
not represent valid logic input levels and generate logically undefined output voltages. The voltages labeled as
VOL and VOH represent the tolerable electrical output voltages at the −1 slope points corresponding to input
levels of VIH and VIL respectively.
Fig.1. Voltage transfer characteristics of hybrid NAND gate.
There is no access to measure the light intensity of Light Emitting Diode (LED) in the optocoupler.
Therefore, current flowing through the LED has been used to represent the optical logic. A measure of light
intensity can be obtained by noting the current flowing through the LED from the characteristics. From the
transfer characteristics of optocoupler, it is found that when a forward current flowing through LED is 0mA,
there is no light output from the LED and in this case the phototransistor is OFF. When a forward current
flowing through LED is 10mA, the LED produces sufficient high light output and in this case the
phototransistor is ON. Therefore ideally, optical LOW input/output logic level is defined as 0mA and 10mA as
optical HIGH input/output logic level.
Similarly, tolerable optical logic levels are defined in terms of currents from the Current Transfer
Characteristics (CTC) of hybrid NAND gate shown in Fig.2. The tolerable input currents IIL and IIH are
measured using the points at which the slope of the CTC equals −1, where, IIL is the maximum input current
flowing through source LED that will be recognized as tolerable optical input logic level LOW and IIH is the
minimum input current flowing through source LED that will be recognized as tolerable optical input logic
HIGH. Currents below IIL are reliably recognized as tolerable optical logic LOW at the input of a logic gate,
and currents above IIH are recognized reliably as optical logic level HIGH at the input. Currents corresponding
to the region between IIL and IIH do not represent valid optical input logic levels and generate logically
undefined output currents. The tolerable currents labeled as IOL and IOH represent the gate output currents at the
−1 slope points corresponding to optical input logic levels of IIH and IIL respectively. The summary of definition
of electrical and optical logic levels of hybrid NAND gate are given in Table.1.
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
220
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
Fig.2. Current transfer characteristics of hybrid NAND gate.
Table.1 Definition of electrical and optical logic levels of hybrid NAND
gate
Ideal case electrical logic levels (V)
Input LOW
Input HIGH
Output LOW
Output HIGH
0
5
0
5
Tolerable electrical logic levels (V)
VIL
VIH
VOL
VOH
0.733
0.976
0.044
4.483
Ideal case optical logic levels (mA)
Input LOW
Input HIGH
Output LOW
Output HIGH
0
10
0
10
Tolerable optical logic levels (mA)
IIL
IIH
IOL
IOH
5.812
7.975
0.000
9.265
III. REALIZATION OF HYBRID RS FLIP FLOP
The basic hybrid RS flip flop has been realized using well known concept i.e., by cross coupling two hybrid
NAND gates [8] and the coupling can be either electrical or optical in nature. The circuit diagram of electrooptical hybrid RS flip flop using universal hybrid NAND gates is shown in Fig.3. The first hybrid NAND gate
consists of two phototransistors (PT1 and PT2), which are connected in series. The load of NAND gate consists
of a Load LED1 to provide optical output and a series resistor RL1 across which the electrical output is taken.
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
221
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
Similarly, the second hybrid NAND gate consists of two phototransistors (PT3 and PT4), which are connected in
series. The load consists of a Load LED2 to provide optical output and a series resistor RL2 across which the
electrical output is taken. The phototransistors are used as switches, which can be operated with either electrical
or optical input signals.
To realize the electro-optical hybrid RS flip flop, Light Emitting Diode (LED) which can give optical output
and phototransistor which can respond to electrical/optical signals are used. Since alignment of light source and
photo detectors are involved in realizing hybrid RS flip flop, it is proposed to use optocouplers as they are
available with perfectly aligned LED and the phototransistor in a single IC package. Hence, optocouplers
(4N32) have been used for implementing and verifying the functionality of hybrid RS flip flop. The current
source is implemented using BC558A transistor.
+ VEE
+ VEE
Current
Source2
Current
Source1
87KΩ
87KΩ
I = 10mA
I = 10mA
+ VD2
+ VD1
Ii1
386Ω
Load
LED1
Light
Output1
Io1
Source
PT1
LED1
R
Vo1
Vi1
RL1
386Ω
Light
Output2
Io2
Source
Q
200KΩ
Ii2
Load
LED2
Q
PT3
LED2
Vo2
200KΩ
S
500Ω
Vi2
RL2
500Ω
PT4
PT2
200KΩ
200KΩ
Fig. 3 Circuit diagram of hybrid RS flip flop using hybrid NAND gates.
The RS flip flop has two inputs, and the inputs are generally designated "S" and "R" for "Set" and "Reset"
respectively. The RS inputs can be either electrical inputs or optical inputs. The S input is used to set the flip
flop. When the flip flop is set, it is said to store a binary bit 1. The R input resets the flip flop and when it is
reset, it is said to store a binary bit 0. The RS flip flop has two outputs, normal output (Q) and complement
output (Q) which are always in complementary state relative to one another. If the logic level of the Q output is
HIGH, the flip flop is set and if it is LOW, it is reset. The hybrid RS flip flop produces both electrical and
optical outputs. In this circuit, RS inputs for the hybrid flip flop are either electrical inputs (Vi1 and Vi2) and/or
optical inputs Ii1 and Ii2 (current through source LED’s). Vo1/Io1 is the normal electrical/optical output (Q) and
Vo2/Io2 is complement electrical/optical output (Q) of the hybrid RS flip flop. The dotted lines in the circuit
diagram indicates the feed back path between the NAND gates which is either electrical or optical. In this
circuit, the electrical feed back is used.
IV.
PRINCIPLE OF OPERATION OF HYBRID RS FLIP FLOP
The operation of hybrid RS flip flop can be explained by considering the operating modes of the four
phototransistors (PT1, PT2, PT3 and PT4) shown in Fig.3. If both RS inputs of the hybrid flip flop are equal to
electrical and/or optical logic LOW, PT1 of first NAND gate and PT3 of second NAND gate does not conduct.
Hence, most of the current from the current source1 flows through Load LED1 and produces electrical logic
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
222
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
HIGH and optical logic HIGH as normal output (Q). Similarly, most of the current from current source2 flows
through Load LED2 producing electrical HIGH and optical HIGH as complementary output ( Q ). Thus, the
application of electrical and/or optical logic LOW to both of the RS inputs will produce electrical logic HIGH
and optical logic HIGH as normal (Q) and complementary ( Q ) outputs. This contradicts the assumption that Q
and Q must be complementary. This condition where both the inputs of RS flip flop are electrical/optical logic
LOW is Not Allowed (NA).
When R input is electrical/optical logic LOW, and S input is electrical/optical logic HIGH, the PT1 of first
NAND gate is turned OFF and most of the current from the current source1 flows through the Load LED1.
Hence, the hybrid RS flip flop produces optical HIGH and electrical HIGH as normal output (Q). Since, this
normal output (Q) is fed back to the base input of PT4 of second NAND gate, PT3 and PT4 are turned ON and
most of the current from the current source2 flows through them and very negligible amount of current flows
through Load LED2. Hence, hybrid RS flip flop produces optical logic LOW and electrical logic LOW as
complement output ( Q ). Thus, when R input is electrical/optical logic LOW and S input is either
electrical/optical logic HIGH, the hybrid RS flip flop produces electrical logic HIGH and optical logic HIGH as
normal output (Q) and electrical LOW and optical LOW as complementary output ( Q ).
When the R input is electrical/optical logic HIGH, and the S input is electrical/optical logic LOW, the PT3
of second NAND gate is turned OFF and most of the current from the current source2 flows through the Load
LED2. Hence, the hybrid RS flip flop produces optical HIGH and electrical HIGH as complement output ( Q ).
Since, this complement output ( Q ) is fed back to the base input of PT2 of first NAND gate, PT1 and PT2 will
conduct and most of the current from the current source1 flows through them and very negligible amount of
current flows through Load LED1. Hence, the hybrid RS flip flop produces optical logic LOW and electrical
logic LOW as normal output (Q). Thus, when R input is either electrical or optical logic HIGH and S input is
either electrical or optical logic LOW, the hybrid RS flip flop produces electrical logic LOW and optical logic
LOW as normal output (Q) and electrical HIGH and optical HIGH as complementary output ( Q ).
If both the RS inputs of the hybrid latch are equal to electrical and/or optical logic HIGH, the output state
of hybrid RS latch does not change.
V.
EXPERIMENTAL RESULTS
In order to verify the functionality, the hybrid RS flip flop is implemented with a current source of 10mA. The
collector of BC558A transistor behaves as current source, when connected to a power supply. To generate
10mA of current through the current source, a power supply supply voltage (VEE) of 6.2V with a base resistance
of 87KΩ is used. The voltage drop across the source LED/Load LED is around 1.15V, when current of 10mA
flowing through the LED. The value of current limiting resistor is selected as 386Ω to provide an input current
of 10mA through source LED. To produce electrical logic HIGH corresponding to a voltage of 5V, a series load
resistor of value 500Ω is connected to the Load LED. This circuit thus satisfies the conditions that input logic
levels and output logic levels are almost the same and can be used for building cascadable hybrid sequential
circuits and systems. To verify the functionality of hybrid RS flip flop shown in Fig.3, the experiment is
performed for different electrical and/or optical RS input logic level values. The experimental results of hybrid
RS flip flop realized using NAND gates is shown in Table.2. The experimental results of hybrid RS flip flop
using hybrid NAND gates are discussed in the following section.
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
223
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
Table.2 Experimental results of hybrid RS flip flop
Electrical inputs
Optical output
Io (mA)
S
Vi1(V)
R
Vi2(V)
Qn+1
Vo1(V)
Qn+1
Vo2(V)
Qn+1
Io1(mA)
Qn+1
Io2(mA)
0
0
4.8
4.8
9.6
0
5
0
4.8
0
9.6
9.6
5
0
4.8
0
9.6
0
5
5
Qn
Qn
Qn
Qn
Optical inputs
(Current through
source LEDs)
S
Ii1(mA)
R
Ii2(mA)
Electrical output
Vo (V)
Optical output
Io (mA)
Qn+1
Vo1(V)
Qn+1
Vo2(V)
Qn+1
Io1(mA)
Qn+1
Io2(mA)
4.8
4.8
9.6
0
10
0
4.8
0
9.6
9.6
10
0
4.8
0
9.6
0
10
10
Qn
Qn
Qn
Qn
0
0
Hybrid inputs
(Optical and
Electrical inputs)
VI.
Electrical output
Vo (V)
Electrical output
Vo (V)
Optical output
Io (mA)
S
Ii1(mA)
R
Vi2(V)
Qn+1
Vo1(V)
Qn+1
Vo2(V)
Qn+1
Io1(mA)
Qn+1
Io2(mA)
0
0
4.8
4.8
9.6
4.8
0
9.6
9.6
0
9.6
0
Qn
Qn
Qn
0
5
0
10
0
4.8
10
5
Qn
DISCUSSION OF EXPERIMENTAL RESULTS
If both the RS inputs are equal to electrical logic LOW (0V), the hybrid RS flip flop produces electrical
output of 4.8V and optical output of 9.6mA for both normal (Qn+1) and complement ( Q n+1) outputs. This
contradicts our assumption that Qn+1 and Q n+1 must be complementary. This condition where both the inputs
of hybrid RS flip flop are electrical logic LOW is Not Allowed (NA). When R input is electrical logic LOW
(0V) and S input is electrical logic HIGH (5V), the hybrid RS flip flop produces electrical output (Vo1) of 4.8V
and optical output (Io1) of 9.6mA as normal output (Qn). In this case, the hybrid RS flip flop is said to be in set
state. When R input is electrical logic HIGH (5V) and S input is electrical logic LOW (0V), the hybrid RS flip
flop produces electrical output (Vo1) of 0V and optical output (Io1) of 0mA as normal output (Qn). In this case,
the hybrid RS flip flop is said to be reset. If both RS inputs are equal to electrical logic HIGH (5V), the hybrid
RS flip flop does not change output state.
Similar is the case with different combinations of optical input logic level values or hybrid input logic level
values as shown in Table2. Thus, the functionality of hybrid RS flip flop has been demonstrated.
VII. CONCLUSION
The basic building block for a sequential circuit is a flip flop. This paper demonstrated the cascadable
electro-optical hybrid RS flip flop which accept either electrical or optical signals and produce both electrical
and optical signals. The circuit is implemented using universal hybrid NAND logic gates. The hybrid RS flip
flop may be used to construct large and complex hierarchical hybrid memory circuits like registers and counters.
The electro-optical hybrid logic gates have been reported earlier and hybrid RS flip flop in this paper. These
hybrid logic circuits may be used in building cascadable, hierarchical circuits and systems as the input and
output logic levels are almost the same and within the tolerable logic levels. It is felt that this effort would pave
the way for developing new branch of Hybrid Optoelectronic Circuits and Systems which will involve both
electrical and optical signals and have advantages of both the systems.
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
224
Ekkurthi.Sreenivasa Rao et al. / International Journal of Advances in Engineering, Science and Technology (IJAEST)
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Chang-Hee Lee et al, “Optical flip flop using discrete components”, Applied Optics, 25, pp 14, 1986.
T. Chino et al., “Novel Integrated optoelectronic RS flip flop based on optically coupled inverters,” Elec. Letters, 28, pp7, 1992.
K. Matsuda et al., “Integration of optoelectronic bistable switches with a function of optical erasing”, IEEE Trans. Electron Dev., 11,
pp 442-444,1990.
K. Matsuda et al., “Dynamic set and reset optoelectronic latching device”, IEEE Photon. Tech. Lett., 4, pp 483-485, 1992.
X. An et al., “Highly compact integrated optical set-reset memory pixels for optical processing arrays”, IEEE photonics Tech. Lett. 5,
pp 5, 1993.
S. Noda et al ., “Light controlled optical bistable device by bistable laser diode and hetero junction photo transistors”, Electron.
Letters., 26(14), pp. 1069-1070, 1990.
M.K. Ravishankar and M. Satyam., “Optically/Electrically (Symmetrically) Triggerable bistable multivibrator”, IEEE Trans. On
circuits and systems-1: Fundamental theory and applications, 43(7), pp 610-612, 1996.
Ekkurthi Sreenivasa Rao, M. Satyam, K. LalKishore, “Universal Electro-optical hybrid logic gates” Semiconductor Physics, Quantum
Electronics & Optoelectronics, 11(1), pp 96-100, 2008.
J. R. Houser, “Noise margin criteria for digital logic circuits,” IEEE Trans. on Education, vol. 36, no. 4, pp. 363–368, 1993.
ISSN : 2249-913X
Vol. 2 No. 3 Aug-Oct 2012
225